JP2850629B2 - Logic verification system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification system for designing a logic circuit.

[0002]

2. Description of the Related Art Conventionally, when a circuit is designed by dividing it into a plurality of functional blocks, the delay is improved and the parts used are changed in functional block units. It is necessary to re-simulate from the beginning with an integrated model and check the operation.

[0003]

In a conventional logic verification system in which a circuit is designed by dividing it into a plurality of functional blocks, if a circuit is modified to improve the delay in one functional block, the change is correct. In order to confirm that the simulation is performed again from the beginning with a model that integrates functional blocks, re-execution at the stage where sufficient simulation evaluation has been performed requires a lot of man-hours because all previous simulation evaluations are redone There is a problem that is.

[0004] In view of the above problems, the present invention provides a logic verification system which does not require re-simulation with an integrated model even when a circuit of a functional block is changed.

[0005]

SUMMARY OF THE INVENTION A logic verification system according to the present invention is a logic verification system for changing a circuit configuration in units of functional blocks when designing a circuit by dividing the circuit into a plurality of functional blocks. Pre-change data holding means for holding circuit information of a block, post-change data holding means for holding circuit information of a changed functional block, and test pattern generating means for generating a test pattern to be applied to an input pin of the functional block And the circuit information of the function block before the change is inputted from the data holding means before the change, and the test pattern generated by the test pattern generation means is applied to the input pin of the function block based on the inputted circuit information. First expected value generating means for simulating operation and obtaining an expected value at an output pin of the functional block;
The pre-change expected value storing means for storing the expected value generated by the first expected value generating means, and the circuit information of the functional block after the change are inputted from the post-change data holding means, and the functional block of the functional block based on the inputted circuit information is inputted. A second expected value generating means for simulating the operation of the functional block when the test pattern generated by the test pattern generating means is applied to the input pin and obtaining an expected value at the output pin of the functional block;
An expected value storage means for storing the expected value generated by the expected value generation means of the above, and a comparing means for comparing whether the contents stored in the expected value storage means before the change and the expected value storage means after the change are the same. The verification of the matching of the logical operations of the functional blocks before and after the change is performed.

[0006]

The test patterns generated by the test pattern generation means are applied to the function blocks input by the first and second expected value generation means from the pre-change data holding means and the post-change data storage means, respectively. Get. The respective expected values are stored in the expected value storage means before change and the expected value storage means after change, respectively, and are compared by the comparing means for the same or not. If they are the same, simulation of the whole is unnecessary.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The pre-change data holding means 1 is a data file for storing circuit information at a functional block level. The post-change data holding unit 2 stores circuit information after the circuit configuration of the functional block stored in the pre-change data holding unit 1 has been changed. The test pattern generation means 3 extracts the input pins of the functional blocks from the pre-change data holding means 1 and generates a test pattern according to the control information. The expected value generation means 4 generates a simulation model at the functional block level before the change from the circuit information stored in the data storage means 1 before the change, and simulates the test pattern generated by the test pattern generation means 3. To the input pins of the simulation model to generate expected values of data changes at the output pins of the simulation model.

The expected value generating means 5 generates a changed functional block level simulation model from the circuit information stored in the changed data holding means 2 and the test pattern generated by the test pattern generating means 3. To the input pins of the simulated model,
Generate the expected value of the data change at the output pin of the simulated model. The pre-change expected value storage means 6 stores, for each output pin, the expected value at the output pin of the pre-change function block generated by the expected value generation means 4 in correspondence with the input data of the input pin of the simulation model. . The changed expected value storing means 7 stores the expected value at the output pin of the changed functional block generated by the expected value generating means 5 for each output pin in correspondence with the input data of the input pin of the simulation model. . The comparison means 8 compares the data strings for each output pin stored in the expected value storage means 6 before change and the expected value storage means 7 after change, when all the valid data are available. Verify that they are identical. The result is that the functional block after the change is logically equivalent to the functional block before the change (equivalent to the dynamic view)
Indicates whether or not

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. When changing a circuit that is logically equivalent (for example, equivalent when viewed statically), such as improving the delay or changing the components used in the function block,
The circuit information before the change is stored in the pre-change data holding means 1 (step S1). Here, the circuit information is information on the input / output pins of the functional block, information on the components used, and their connection information, and is data necessary for simulation.
Necessary circuit changes are made (step S2), and the changed circuit information is stored in the changed data holding means 2 (step S2).
3). The test pattern generator 3 extracts a clock signal and a master reset signal of the functional block from the circuit information stored in step S1, and generates a test pattern to be applied to the input pin of the functional block (step S4). The expected value generation means 4 generates a simulated model from the circuit information obtained in step S1 and applies the test pattern generated in step S4 to obtain the expected value of the output pin of the functional block before the change, thereby obtaining the expected value before the change. Value storage means 6
To be stored. The expected value generating means 5 generates a simulated model from the circuit information stored in step S3, and obtains the expected value of the output pin of the changed functional block by applying the test pattern generated in step S4. It is stored in the value storage means 7. Finally, the contents of the pre-change expected value storage means 6 and the post-change expected value storage means 7 are compared with the comparing means 8.
The comparison is made for each output pin of the functional block, and if they are all the same, the functional blocks before and after the change are determined to be logically equivalent.

[0010]

As described above, according to the present invention, when a circuit is divided into a plurality of functional blocks and a circuit is designed, it is desired to perform a circuit change at a functional block level without logically changing to improve delay or the like. In this case, by comparing the expected value obtained by inputting the test pattern into the circuit before the change and the expected value obtained by inputting the same test pattern into the circuit after the change by comparing means, the logic of the circuit before and after the change is obtained. If the logical equivalence can be verified, and if the logical equivalence can be verified, it is sufficient to proceed with a new simulation evaluation in a model that integrates all the functional blocks, and it is necessary to restart the simulation evaluation from the beginning. This has the effect that unnecessary man-hours are not required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a logic verification system according to the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pre-change data holding means 2 Post-change data holding means 3 Test pattern generation means 4, 5 Expected value generation means 6 Pre-change expected value storage means 7 Post-change expected value storage means 8 Comparison means

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS)

Claims (1)

(57) [Claims] When a circuit is designed by being divided into a plurality of functional blocks, in a logic verification system that changes a circuit configuration in units of functional blocks, a data pre-change data holding unit that holds circuit information of the functional blocks before the change is provided. A post-change data holding means for holding the circuit information of the function block after the change, a test pattern generation means for generating a test pattern to be applied to the input pin of the function block, and a pre-change data of the circuit information of the function block before the change Simulates the operation of the function block when the test pattern generated by the test pattern generation means is applied to the input pin of the function block based on the input circuit information input from the holding means, and the expectation at the output pin of the function block First expected value generating means for obtaining a value, and a change period storing the expected value generated by the first expected value generating means The value storage means and the circuit information of the changed functional block are input from the changed data holding means, and the test pattern generated by the test pattern generating means is applied to the input pin of the function block based on the input circuit information. Second expected value generating means for simulating the operation of the functional block and obtaining an expected value at an output pin of the functional block; and expected value storing means before change for storing the expected value generated by the second expected value generating means And comparing means for comparing whether the contents stored in the expected value storage means before change and the expected value storage means after change are the same, and verifying the coincidence of the logical operations of the functional blocks before and after the change. Logic verification system that performs