JP2851046B2 - Logic circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to a logic circuit test apparatus for connecting a test pattern control circuit and a device under test with the shortest wiring and performing a high-speed and high-quality test. The purpose of the present invention is to provide a logic circuit test apparatus that facilitates wiring of the shortest distance by using an adapter that satisfies wiring and a pin number conversion circuit. From a test pattern control circuit that is controlled by a central processing unit, In a logic circuit test apparatus for testing a device under test by receiving a response signal corresponding to a test number transmitted to the device under test via an adapter having a corresponding wiring, the logic circuit test device is inserted between the central processing unit and a test pattern control circuit. And a pin number conversion circuit for converting test data so as to satisfy the shortest wiring length of the adapter.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit test apparatus that connects a test pattern control circuit and a device under test with the shortest wiring and performs high-speed and high-quality tests.

Conventionally, an adapter corresponding to the pin number is inserted between the test pattern control circuit and the device under test, but since the pin connection wiring in the adapter is configured to correspond to the device under test, short-distance wiring is Because of the difficulty, it was requested to develop means to solve the problem.

[Prior Art] FIG. 5 is a diagram showing a configuration of a conventional logic circuit test apparatus. In FIG. 5, reference numeral 1 denotes a test pattern control circuit;
Is a pin electronics that provides a test signal to the device under test and receives a response signal. 3 is an adapter, 4 is a device under test (UUT), 5 is a central processing unit (CPU), 6 is a pattern generator, and 11 is a pattern generator. A memory, 12 is a data formatter, 13 is a fail detector, and 14 is a fail memory. The pattern memory 11 to the fail memory 14 are grouped into one group, and are associated with one group of the pin electronics 2 and with one terminal pin of the device under test 4. The test pattern control circuit 1, the pattern generator 6, and the pin electronics 2 are collectively called a tester.

When testing the operation of the device under test 4, test data is stored in the pattern generator 6 in advance, and the test processing is started by the central processing unit 5. Data for the test is supplied from the pattern generator 6 to the test pattern control circuit 1, converted into predetermined test data by the data formatter 12, and applied to the adapter 3 by the driver of the pin electronics 2. Since the device under test 4 is densely integrated and highly integrated, it is required to improve the transmission quality of test data, and it is required that the wiring length from the pin electronics 2 to the device under test 4 be minimized. However, the physical arrangement of the terminal numbers of the device under test 4 in the physical arrangement of the terminal numbers of the pin electronics 2 is often not assigned so that the physical distance between the corresponding numbers is the shortest.

Response data of the device under test 4 in response to the test data applied to the device under test 4 is transmitted from the terminal pins through the adapter 3 in reverse, and is input to the comparator of the pin electronics 2. The output signals “H” and “L” are determined by comparing with a predetermined voltage in a comparator, and input to the fail detector 13 of the tester 1. Here, the signal is compared with a test input signal to detect the presence or absence of an error signal, and the error signal is stored in the fail memory 14 at the pin number where the error has occurred. Next, the pattern generator is incremented, and a test is performed on the next test pattern of the device under test 4 by applying the output of the pattern generator.

[Problem to be Solved by the Invention] Although the test processing using the test machine shown in FIG. 5 has no problem at all for a device under test of a low-density and low-integration circuit,
When the device under test 4 is highly integrated recently, it is necessary to have high-speed and high-quality transmission characteristics for pattern data. Adapter 3 is test pattern control circuit 1
For each of the test piece 4 and the test object 4, the design and production were required so as to satisfy the correspondence of the pin numbers.
This is for performing a physical coupling operation in order to test various types of test objects 4. Actually, the condition cannot always be satisfied, and both ends of the adapter 3 are connected with a coaxial cable of, for example, several tens of centimeters. Has the drawback that the wiring becomes difficult. Problems that occur in the test processing when the wiring is long are such that external noise is picked up to lower the signal quality, reflected waves are generated due to impedance mismatch, leakage signals are increased, and capacitance is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a logic circuit test apparatus which solves the above-mentioned drawbacks and facilitates the shortest distance wiring by using an adapter and a pin number conversion circuit satisfying the shortest distance wiring.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, 1 is a test pattern control circuit, 4 is a device under test,
5 is a central processing unit, 7 is a pin number conversion circuit, and 30 is an adapter.

From the test pattern control circuit 1 controlled by the central processing unit 5, a response signal to the test signal sent to the device under test 4 is received via the adapter 30 having the corresponding wiring for pin connection, and the test of the device under test 4 is performed. The present invention has the following configuration in a logic circuit test apparatus to be performed. That is, the adapter 30 is provided between the central processing unit and the test pattern control circuit 1 and has a pin number conversion circuit 7 for converting test data so as to satisfy the shortest wiring length of the adapter 30.

[Operation] In the configuration of FIG. 1, the adapter 30 is configured so that the wiring length between the test pattern control circuit 1 and the device under test 4 is minimized. The test data arrives at the DUT 4 with high speed and high quality, and the response data from the DUT 4 can similarly respond to the test pattern control circuit 1 in the shortest time. At this time, since the terminal pin numbers of the device under test 4 do not correspond one-to-one with the terminal pin numbers in the test pattern control circuit 1, the pin numbers are converted by the pin number conversion circuit 7. That is, when the central processing unit 5 starts processing to test the terminal pins of the device under test 4 with, for example, the terminal pin No. 0, the test pattern control circuit 1 corresponding to the terminal pin No. 0 of the device under test 4 with the shortest distance wiring The output terminal position of
Since the data of the terminal pin 0 is not always present, the conversion circuit 7 is configured so that the data of the number 0 exists at the terminal position.

Embodiment FIG. 2 is a diagram showing a specific configuration of the pin number conversion circuit 7 in FIG. 1 as an embodiment of the present invention. In FIG. 2, 71 is a pin number counter, 72 is a pin number conversion table, and 73 is a control unit. The pin number conversion table 72 uses the terminal pin number of the device under test 4 as an address as shown in FIG.
The data content is the terminal pin number of the test pattern control circuit 1. The output of the pin number counter 71 is controlled by the control unit 73 so as to be the address of the pin number conversion table 72. The test data is sent to the pin electronics specified by the pin number indicated by the output signal of the pin number conversion circuit 7. Therefore, for example, when transmitting the test data in the order of the pin numbers 0, 1, 2,.
Assuming that the data of the conversion table 72 read by the pin number counter 71 with the counter value "0" is No. 4, the No. 4 pin of the DUT 4 is tested from the No. 4 terminal of the test pattern control circuit 1. Send data. The data is applied to the pin 0 of the DUT 4 via the pin electronics and the adapter 30 as required. Next, pin number counter
The data corresponding to the first address of the table 72 is read out by advancing 71, and the test data of the first pin is transmitted from the output terminal of that number in the test pattern control circuit 1.

The table for performing the pin number conversion stores data set in advance so that the shortest wiring length can be obtained by the adapter 30.

FIG. 3 shows the central processing unit during the operation of pin number conversion.
CPU (corresponding to the central processing unit 5 in FIG. 1)
FIG. 4 is a diagram showing a flow of data from a. In FIG. 3, the data from the central processing unit CPU is transmitted in a state directly corresponding to the data for each pin number of the device under test UUT. The pin number in the data is applied to the pin number conversion table. Then, the data of the table is searched using the value of the pin number counted by the counter as an address. For the data read from the table, for example, pin number 0, the data is the pin number after the number conversion. Next, the 0-pin data of the device under test UUT flows to the corresponding pin on the pin electronics, for example, according to the converted pin number. As shown by a thin broken line below the connection, the data transmitted to the output terminal of the pin electronics (data of the UUT pin 0) reaches the UUT pin 0 via the adapter.

FIG. 4 shows a time chart of the pin number conversion. 4th
FIG. A shows a signal for initializing the pin number counter 71. FIG. 4B shows the output of the pin number counter 71, that is, the address of the pin number conversion table 72. FIG. 4C shows test data from the central processing unit 5. FIG. 4D shows the read values of the pin number conversion table. FIG. 4E shows a data write strobe signal from the central processing unit 5. Fig. 4 F, G, H
Indicates the register data for the pin numbers 4, 5, and 6 built in the pin electronics.

The read value of the conversion table 72 of the address "0" by the pin number counter "0" in FIG. 4B is stored in the terminal No. 4 pin as shown in FIG.
The pin corresponds to the number 6 pin for the counter “2”. Then, as shown in FIG. 4C, the test data for each pin from the central processing unit 5 is transmitted from the number pin obtained at that time to the pin electronics adapter. The test data for each of the terminal pins 0, 1, 2,... Of the device under test 4 is transmitted at the times shown in FIGS.

[Effects of the Invention] As described above, according to the present invention, by using an adapter for simply coupling a logic circuit tester and a device under test at the shortest distance, a test pattern at an input / output terminal of a test pattern control circuit can be used. -The corresponding number of the response data can be converted by the pin number conversion circuit. Therefore, by setting the pin number conversion circuit in advance, the logic circuit tester can be effectively used for a large number of devices under test. Since the logic circuit tester and the device under test are always connected to each other with the shortest distance, the above-described problems do not occur at all, and the test can be performed quickly and accurately.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing a specific configuration of a pin number conversion circuit as an embodiment of the present invention, FIG. 3 is a diagram showing a data flow of FIG. FIG. 4 is an operation time chart of FIG. 2, and FIG. 5 is a diagram showing a configuration of a conventional logic circuit test apparatus. 1 Test pattern control circuit 2 Pin electronics 3, 30 Adapter 4 Device under test 5 Central processing unit 7 Pin number conversion circuit

Claims (1)

(57) [Claims] A test signal is received from a test pattern control circuit, which is controlled by a central processing unit, in response to a test signal transmitted to a device under test via an adapter having a pin-connecting corresponding wiring, and a test of the device under test is performed. A logic circuit test apparatus, comprising: a pin number conversion circuit inserted between the central processing unit and a test pattern control circuit and configured to convert test data so as to satisfy the shortest wiring length of the adapter. Logic circuit test equipment.