JP2852362B2 - Word line drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention has a plurality of main word lines and a plurality of sub-word lines for each of the plurality of main word lines, and a plurality of memory cells are connected to each of the plurality of sub-word lines. The present invention relates to a word line driving device for selectively driving a plurality of main word lines and a plurality of sub-word lines for each of the plurality of main word lines in a storage device having a configuration.

[Prior art]

Conventionally, a word line driving device described below with reference to FIG. 2 has been proposed. That is, it has a plurality of main word lines MWL ₁ , MWL ₂ . Each of the plurality of main word lines MWL ₁ , MWL ₂ ..., That is, the main word lines MWL _i (where i = 1,
2 .........) for a plurality of sub-word lines SWLi1, SWLi2 ...
... Further, each of the sub-word lines SWL _i1 , SW _i2 ..., That is, the sub-word lines SWL _ij (where j = 1,
...) Connected to a plurality of memory cells C _ij1 , C _ij2 .
... Furthermore, Ki is also preparative not a to the input of the main word line selection logic signal MWSS _i, the main word line MWL _i logic signal driver main word line MWDS
_It has a main word line drive circuit MWD _i that outputs _i . In this case, the main word line selection logic signals MWSS ₁ , MWSS ₂ …
... Means that when one of them takes "0" in binary display, all others take "1" in binary display. The main word line driver MWD _i receives the main word line selection logic signal MWSS _i, have a logic circuit M _i constructed using MIS transistor that outputs a main word line driving logic signals MWDS _i Then, when the main word line selection logic signal MWSS ₁ takes “0” in binary display, the main word line drive logic signal MWDS _i is output as taking “1” in binary display, logic signal MWDS _i for driving the main word lines at other outputs as to take "0" in the binary display. Furthermore, the main word line driving circuit MWD _i main word line driving logic signals from MWDS _i, sub-word line SWL _1j, SWL _2j .........
And the sub-word line driving logic signal SWDS is applied to the sub-word line SWL _{ij based} on the common block selection logic signal BSS _j.
It has a sub word line drive circuit SWD _ij that outputs _ij . In this case, the block selection logic signals BSS ₁ , BSS ₂ ………
, When one of them takes "1" in binary display, all others take "0" in binary display. The sub-word line driving circuit SWD _ij includes a NAND circuit ND _ij configured using MIS transistors that input a main word line driving logic signal MWDS _i and a block selection logic signal BSS _j, and the NAND circuit ND _ij.
ij enter the inverter IN _ij constructed using the MIS transistor for outputting a logic signal SWDS _ij for driving the sub-word line
And when the main word line driving logic signal MWDS _i takes "1" in binary representation and the block selection logic signal BSS _j takes "1" in binary representation, The line drive logic signal SWDS _ij is output as a binary display that assumes "1". Otherwise, the sub word line drive logic signal SWDS _ij is output.
DSij is output as a binary value that takes "0". The above is the configuration of the conventional word line driving device. According to the conventional word line driving system having such a configuration, the main word line selection logic signal MWSS _i takes a "0" in binary display, and block select logic signal BSS _j are binary display " When "1" is set, the sub-word line driving logic signal SWDS _ij is given as "1" in binary notation to the sub-word line SWL _ij for the main word line MWL _i . Therefore, the sub word line SWL
_ij has been selectively driven. This means that the memory cells C _ij1 , C _ij2 ... Connected to the sub-word line SWL _ij have been word-selected. Thus, by providing the binary data whereby one selected drive to the memory cell C _ij1, C _ij2 ......... in the memory cell C _ij1, C _ij2 ......... one to store binary data in And their memory cells C _ij1 , C _ij
By selecting one of _ij2 ..., the binary data stored therein can be read. In this case, the memory cell with respect to the main word line MWL _i is the sub-word line SWL _i1; SWL _i2; memory cells C that are connected to _{......... i11, C i12 .........; C} i21, C i22 ... …
…; ………, but those memory cells C _i11 , C
_i12 ………; C _i21 , C _i22 ………;
L _i1 ; SWL _i2 ; ………, and all of the memory cells C _i11 , C _i12 ………; C _i21 , C _i22 ……… are connected to the main word line _MWLi. Absent. Therefore, according to the conventional word line driving device shown in FIG. 2, the current flowing through the memory cells selectively driven as described above is applied to the main word line MWL _i by the memory cells C _i11 , C _i12.
..; C _i21 , C _i22 .........

[Problems to be solved by the invention]

However, the conventional word line driving device shown in FIG. 2 has a drawback that operation cannot be performed at high speed. Therefore, the present invention proposes a novel word line driving device that does not have the above-mentioned disadvantages.

[Means for Solving the Problems]

The word line driving device according to the first invention of the present application
As in the case of the conventional word line driving device described above with reference to the drawing,
A plurality of main word lines MWL ₁ , MWL 2..., A plurality of sub-word lines SWL _i1 , SWL _i2 ... For the main word line MWi (where i = 1, 2,...), And the sub-words line
Based on the plurality of memory cells C _ij1 , C _ij2 ... Connected to SWL _ij (where j = 1, 2,...) _And the input of the main word line selection logic signal MWSS _i , Main word line MWL _i
A main word line driver MWD _i for outputting a main word line driving logic signals MWDS _i to a logic signal MWDS _i for driving the main word line from the main word line driver MWD _i, the sub-word line S
A sub-word line drive for outputting a sub-word line drive logic signal SWDS _ij to the sub-word line SWL _{ij based} on a block selection logic signal BSS _j common to WL _1j , SWL _2j. Circuit SWD _ij . However, the present first word line driving device according to the invention is, in the word line driving device having such a configuration, the main word line driver MWD _i is, a collector connected to the first power supply terminal, an emitter Main word line MW above
Li and a second power supply terminal through a load circuit U _i and a common constant current circuit HA to the main word line drive circuits MWD ₁ , MWD ₂ ... having a bipolar transistor QA _i of the logic signal word line selection MWSS _i or a negative logical signal MWSS _i 'is given. The word line driving device according to the second aspect th invention, in the word line driving device according to the present 1st invention, the load circuit U _i is a collector connected to the emitter of the bipolar transistor QA _i, the emitter connected to the constant current circuit HA, based first resistor R _iA through the bipolar transistor QA _i of connected to the emitter and a second resistor R _iB through the second capacitive element with connected to the power supply terminal I have other bipolar transistor QB _i connected to the first power supply terminal through C _i. Further, the word line driving device according to the third invention of the present application is the word line driving device according to the first invention of the present application or the second invention of the present application.
SWD _ij has a collector connected to the first power supply terminal through a resistor R _ij and connected to the sub-word line SWL _ij through or without _passing through an inverter IN _ij , and the block selection logic is connected to an emitter as a base. signal BSS _j the given sub-word line driver circuit SWD _1j, and the sub-word line driver circuit SWD _1j through common other bipolar transistor QC _j against SWD _2j ........., against SWD _2j ......... connected to said second power supply terminal through a common other constant current circuit HB _j, with another bipolar transistor QD _ij connected to the main word line MWL _i base. The word line driving device according to the fourth invention of the present application is the word line driving device according to the first invention of the present application or the second invention of the present application, wherein the main word line driving circuit is
MWD _i is connected to the main word line selection logic signal MWSS _i at the input end.
And the output terminal is connected to the bipolar transistor QA _i
Diode connected to the base and clamp
Inverter IN to be connected to the third power supply terminal and via the D _{i
have i} .

[Action / Effect]

According to the word line driving device according to the present 1st invention, load the main word line driver MWD _i is, a collector connected to the first power supply terminal, an emitter with are connected to the main word line MWL _i Are connected to a second power supply terminal through a circuit U _i and a common constant current circuit HA to the main word line driving circuits MWD ₁ , MWD ₂ ..., And the main word line selecting logic signal MWSS _i is connected to a base. Or its NOT logic signal MWSS _i ′
2 is the same as that of the conventional word line driving device described above with reference to FIG. 2 except that it has the bipolar transistor QA _i given in FIG. as with the linear drive takes the "0" in the main word line selection logic signal MWSS _i is binary display, and when the block selection logic signal BSSj takes "1" in binary display, main-word Secondary word line for line MWL _i
SWL _ij is supplied with a sub-word line driving logic signal SWDS _ij in binary display as “1”. Therefore, so that the sub-word line SWL _ij is selectively driven. This means that the memory cells C _ij1 , C _ij2 ... Connected to the sub-word line SWL _ij have been word-selected. Thus, by providing the binary data whereby one selected drive to the memory cell C _ij1, C _ij2 ......... in the memory cell C _ij1, C _ij2 ......... one to store binary data in And their memory cells C _ij1 , C _ij
By selecting one of _ij2 ..., the binary data stored therein can be read. In this case, the memory cell with respect to the main word line MWL _i is the sub-word line SWL _i1; SWL _i2; memory cells C that are connected to _{......... i11, C i12 .........; C} i21, C i22 ... …
…; ………, but those memory cells C _i11 , C
_i12 ………; C _i21 , C _i22 ………;
L _i1; SWL _i2; it is connected respectively to ........., the memory cell _{C i11, C i12 .........; C} i21, C i22 .........; all ......... is connected to the main word line MWL _i Not. Therefore, also in the case of the word line driving device according to the first invention of the present application, the current flowing through the memory cell selectively driven as described above is supplied to the main word line MWL _i by the memory cells C _i11 and C _i11 .
_i12 ………; C _i21 , C _i22 ………;
It has the feature of. However, in the present case the first aspect according to the word line driving device, the main word line driver MWD _i is, a collector connected to the first power supply terminal is connected to the main word line MWL _i emitters load circuit U _i a through and the main word line driver MWD ₁ with, MWD ₂ ......... respect connected to the second power supply terminal through a common constant current circuit HA, the main word line selection logic signal to the base Bipolar transistor Q to which MWSS _i or its NOT logic signal MWSS _i ′ is applied.
Because it has a A _i, it is possible to relatively reduce its main word line selection logic signal for driving the bipolar transistor QA _i MWSS _i or a negative logical signal MWSS ', also,
Since the logic amplitude of the main word line driving logic signal MWDS _i output from the bipolar transistor QA _i to the main word line MW _i is relatively small, the main word line MWL _i and the sub word line driving circuit SWD ₁₁ are driven at high speed. it can be, therefore it is possible to drive the sub-word line SWL _ij fast. According to the word line driving device of the second aspect of the present invention, the configuration is the same as that of the word line driving device of the first aspect of the present invention except for the matters described above.
By to have a relatively high value resistor R _iB of, when the main word line driving circuit MWDi is not selected drive, the current flowing through the bipolar transistor QB _i, hence the current flowing in the bipolar transistor QA ₁ relatively Can be small. Further, since constitute a delay circuit by a first resistor R _iB and the capacitor C _i, by leaving choose those values appropriately, when the main word line driving circuit MWD _i is selectively driven The driving speed can be adjusted. Further, according to the word line driving device according to the third invention of the present application, since it has the same configuration as the word line driving device according to the first invention of the present application or the second invention of the present application, except for the above-mentioned matter, Although detailed description is omitted, the same operation and effect as described above can be obtained in the word line driving device according to the first invention or the second invention of the present application, and the bipolar transistors QD _ij and QC _j are used. , Since the logic amplitude can be made relatively small,
The sub-word line SWL _ij application 1st invention or the second aspect
The word line driving device according to the second invention can be driven at a higher speed than in the case of the word line driving device. According to the word line driving device of the fourth aspect of the present invention, the configuration is the same as that of the word line driving device of the first or third aspect of the present invention, except for the above-mentioned matters. Although detailed description is omitted, the first
Same effects as described above with obtained th invention or word line driving device according to the second aspect th invention, since an inverter IN _i having a clamping diode D _i, a bipolar transistor QA _i surely It can be driven with a small logic amplitude.

【Example】

Next, an embodiment of the word line driving device according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted. The word line driver according to the present invention shown in FIG. 1 has the same configuration as that of the conventional word line driver described above with reference to FIG. 2, except for the following. That is, the main word line driver MWD _i is, a collector connected to the first power supply terminal E _1, and a main word line driving circuit through the load circuit U _i with the emitter connected to the main word line MWL _i MWD ₁ , MWD ₂ ……… Common constant current circuit HA
To the second power supply terminal through the main word line selecting logic signal MWSS _i or its negative logic signal MWSS _i ′.
(In the figure, the negative logical signal MWSS _i 'from the output terminal of the inverter IN _i to be described later) having a bipolar transistor QA _i which is given. In this case, the load circuit U _i is, a collector connected to the emitter of the bipolar transistor QA _i, and an emitter connected to a constant current circuit HA, connected to the emitter of the bipolar transistor QA _i the base through a first resistor R _iA and a second resistor R second power supply other bipolar transistor with connected to the terminal E ₂ is connected to the first power supply terminal E ₁ through the capacitive element C _i QB _i through _iR. In addition, the sub word line drive circuit SWSD _ij
(In the figure, through it) with without through or leads that inverter IN _ij is connected to the first power supply terminal E ₁ through R _ij connected to the sub word line SWL _ij, logical block select an emitter to the base signal BSS _j sub-word line driver circuit SWD _1j which is given, SWD _2j through common other bipolar transistor QC _j against ......... and sub-word line driver circuit SWD _1j, common relative SWD _2j ......... connected second to the power supply terminal E ₂ through another constant current circuit HB _j, with another bipolar transistor QD _ij a base connected to the main word line MWL _i. Further, the main word line driving circuit MWD _i is provided with a main word line selection logic signal MWSS _i at an input terminal, and has an output terminal connected to the base of the bipolar transistor QA _i at a negative logic signal MWSi of the main word line selection logic signal MWSSi. 'an inverter iN _i connected to the third power supply terminal E ₃ through clamping diode D _i with are connected to give. The above is the configuration of the embodiment of the word line driving device according to the present invention. The word line driving device according to the present invention having such a configuration has the same configuration as that of the conventional word line driving device described above with reference to FIG. However, the excellent action and effect described in the section of [Action and Effect] can be obtained.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an embodiment of a word line driving device according to the present invention. FIG. 2 is a connection diagram showing a conventional word line driving device.

Continuation of the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) G11C 11/41-11/414 JICST file

Claims (4)

(57) [Claims] 1. A plurality of main word lines MWL _1, and MWL ₂ ........., the main word line MW _i (however, i = 1,2 .........) a plurality of sub word lines for SWL _i1, SWL _i2 ... _.. , A plurality of memory cells C _ij1 , C _ij2 ... Connected to the sub-word line SWL _ij (where j = 1, 2,...), And a main word line selection logic signal MWSS _i A main word line driving circuit MWD _i for outputting a main word line driving logic signal MWDS _i to the main word line MWL _{i based} on an input _; and a main word line driving circuit MWD _i for driving a main word line from the main word line driving circuit MWD _i . Based on the logic signal MWDS _i and the block selection logic signal BSSj common to the sub-word lines SWL _1j , SWL _2j ..., The sub-word line SWL _{ij is connected} to the sub-word line driving logic signal. S
In the word line driving device and a sub-word line driver circuit SWD _ij for outputting a WDS _ij, the main word line driver MWD _i is, a collector connected to the first power supply terminal, the main word line emitter MWL _i Connected to the second power supply terminal through a load circuit _Ui and through a constant current circuit HA common to the main word line driving circuits MWD ₁ , MWD _2. Line selection logic signal MWSS _i or its NOT logic signal MWSSi ′
Word line driving apparatus characterized by having a bipolar transistor QA _i which is given. 2. A plurality of main word lines MWL _1, and MWL ₂ ........., the main word line MW _i (however, i = 1,2 .........) a plurality of sub word lines for SWL _i1, SWL _i2 ... _.. , A plurality of memory cells C _ij1 , C _ij2 ... Connected to the sub-word line SWL _ij (where j = 1, 2,...), And a main word line selection logic signal MWSS _i A main word line driving circuit MWD _i for outputting a main word line driving logic signal MWDS _i to the main word line MWL _{i based} on an input _; and a main word line driving circuit MWD _i for driving a main word line from the main word line driving circuit MWD _i . Based on the logic signal MWDS _i and the block selection logic signal BSS _j common to the sub-word lines SWL _1j , SWL _2j ..., The sub-word line SWL _{ij is connected} to the sub-word line driving logic. Signal S
In the word line driving device and a sub-word line driver circuit SWD _ij for outputting a WDS _ij, the main word line driver MWD _i is, a collector connected to the first power supply terminal, the main word line emitter MWL _i together are connected to connected to the second power supply terminal through a common constant current circuit HA to the load circuit and through the U _i the main word line driving circuit MWD1, MWD2 ......... to, the main word line selection based Logic signal MWSS _i or its NOT logic signal MWSS _i ′
Has a bipolar transistor QA _i which is given, the load circuit U _i is a collector connected to the emitter of the bipolar transistor QA _i, an emitter connected to the constant current circuit HA, the base first resistor R _iA connected to the emitter of the bipolar transistor QA _i and a second
Word line driving unit through the resistor R _iB and having another bipolar transistor QB _i connected to the first power supply terminal through the capacitive element C _i together are connected to the second power supply terminal . 3. The word line drive device according to claim 1, wherein the sub-word line drive circuit SWD _ij connects a collector to the first power supply terminal through a resistor R _ij. with connected without or leads it through an inverter INij to the sub word line SWL _ij, the said block selection logic signal BSS _j is given the emitter to the base sub-word line driver circuit SWD _1j, the SWD _2j ......... are and the sub-word line driver circuit SW through common other bipolar transistor QC _j for
D _1j, other bipolar transistor connected to said second power supply terminal through a common other constant current circuit HB _j, a base connected to the main word line MWL _i against SWD _2j .........
A word line driving device having QD _ij . 4. A word line driving device of the claim 1 or claim 2, wherein the main word line driver MWD _i is the main word line selection logic signal MWSS _i is applied to the input terminal , the word line driving device according to claim output terminal to an inverter iN _i connected to the third power supply terminal through clamping diode D _i with connected to the base of the bipolar transistor QA _i.