JP2852899B2 - Method for manufacturing thin film transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor. 2. Description of the Related Art Conventionally, a display panel using an active matrix has attracted attention as a method capable of realizing a large-sized panel having a large number of dots, since the matrix size can be made much larger than that of a dynamic system. In particular, in a light-receiving element such as a liquid crystal, the driving duty in the dynamic system is limited, and application of an active matrix to a television display or the like is considered. FIG. 1 shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to cause the signal on the data line Y to be stored as charge in the holding capacitor 3. Until the data is written again, this capacitor 3
And drives the liquid crystal 4 at the same time. Where VC
Is a common electrode signal. Since the leakage of the liquid crystal is very small, it is enough to hold the charge for a short time. The manufacture of the transistor and the capacitor 3 here is exactly the same as the normal IC process. FIG. 2 shows an example in which the cell of FIG. 1 is formed by a silicon gate process. A transistor 10 and a capacitor 11 are formed on a single crystal silicon wafer. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon).
Is made of Al, and the contact holes 7, 8, 9 connect the substrate Al, polysilicon and Al, respectively. [0005] A matrix substrate according to a normal IC process has the following major disadvantages. [0006] Since the manufacturing process of the matrix substrate is the same as that of the IC, a process of performing a heat treatment at about 1000 ° C is included in the process, and the element material is limited in the substrate material due to the high temperature process. In particular, when the size of the display is increased, it is necessary to use a low-resistance metal material for the gate material and use inexpensive glass for the substrate.
Difficult with current high temperature processes. A method of manufacturing a thin film transistor according to the present invention is directed to a method of manufacturing a thin film transistor in which a gate electrode and a channel region of the thin film transistor are opposed to each other via a gate insulating film on a substrate. Forming a silicon thin film to be one electrode of the channel region and the storage capacitor; and irradiating the silicon thin film to be the one electrode of the channel region and the storage capacitor with a laser beam or an electron beam for annealing. It is characterized by the following. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention is to form a thin film transistor using a silicon thin film as a channel. FIG. 3 shows a matrix cell used in the present invention, which is different from FIG. 1 in that a GND wiring including a capacitor 18 is newly provided. And retention is the same. GND in this case
The potential means a constant bias voltage, regardless of a bias level or a signal level. In addition, the input of the display data is regarded as a capacity for the data line Y to hold the sun blue.
A capacitor 21 between the address line X and the GND line or a capacitor 22 between the address line X is used. Embodiment 1 A structural example of a cell according to a first embodiment of the present invention is shown based on a plan view of a cell in FIG. 4A and a cross-sectional view taken along a line AB in FIG. A first silicon thin film 28 that forms the source, drain, and channel of a transistor on a transparent substrate 33, a second silicon thin film that forms a gate line serving as a gate of the transistor, or an equivalent wiring layer 26 and a GND line 2
7. Further, a data line 25 made of a transparent low-resistance material, for example, a Nesa film such as SnO ₂ , a gold layer having a thickness of several hundreds or less, or the like.
And a liquid crystal drive electrode 31, and a contact hole 29 for establishing conduction between layers. A portion where the GND line 27 and the liquid crystal drive electrode overlap each other serves as a charge holding capacitor (FIG. 3-18). Transistor source / drain 3
The 4,35 N ⁺ diffusion (P-channel if P ⁺⁾ is made is a gate insulating film 3 channel 30 under the gate electrode 38
An insulating film 37 such as an oxide film is formed around the gate electrode. The feature of the configuration example shown in FIG. 4 is that, first, the gate insulating film of the transistor becomes a gate self-alignment by oxidizing or forming the first silicon thin film on the silicon thin film. The reduction in mobility and the reduction in speed with respect to the bulk silicon element can be prevented by reducing the parasitic capacitance by converting the parasitic capacitance to self-alignment, thereby preventing the deterioration in speed. The other is a charge holding capacitor (FIG. 3-1).
8) Capacities for data line sample-and-hold (Fig. 3-2)
A second object of the present invention is to use an oxide film of a second silicon thin film or an insulating film on the thin film as a dielectric film of a capacitor for forming (1, 22). In the conventional bulk silicon type, the gate insulating film and the charge holding capacitor of the transistor all use the thermal oxide film of bulk silicon. However, the impurity doping is performed by the gate cell alignment shown in FIG. In the case of the method, under the silicon thin film of the second layer which forms one electrode of the capacitor, high-concentration impurities do not enter, and the capacitor is unstable as it is as it is, and it is difficult to use it. An extra step of doping only the lower electrode of the capacitor with a high concentration impurity is required. Therefore, as shown in FIG.
By forming the dielectric film for forming the holding capacitor on the second silicon thin film, the process, which is the object of the present invention, can be simplified and the capacitor can be stabilized. FIG. 5 shows a manufacturing process of the active matrix cell shown in FIG. The low-temperature process of the present invention uses glass or a high-melting-point glass such as Pyrex or Corning as a transparent substrate, and is a processing step at 600 ° C. or lower, and is characterized in that the substrate itself is inexpensive. In the low temperature process, first, a silicon thin film is formed on a substrate 33 by CVA such as plasma CVD or low pressure CVD.
It is formed by a sputtering method, a sputtering method, or the like, and is formed into a required shape by photoetching. Thereafter, the surface is oxidized in an O ₂ plasma atmosphere. Further, an equivalent insulating film may be deposited by a CVD method. As a result, an oxide film 41 serving as a gate insulating film is formed on the silicon thin film 40 (FIG. 5A). Thereafter, the second layer of silicon thin film is deposited and photo-etched in the same manner as the first layer of silicon thin film, and then the oxide film 41 is formed using the second layer of silicon thin film 45 as a mask.
Is etched to form a gate insulating film 41, and at the same time, a window for diffusion is formed. When diffusion is performed by ion implantation, sources and drains 42 and 43 are formed.
(B)). After that, plasma treatment is again performed in an O ₂ atmosphere to form a plasma oxide film 46 on the surface,
Annealing is performed at 600 ° C. (FIG. 5C). The feature of this process is that the silicon thin film is directly oxidized by plasma treatment, and the mobility is improved as compared with the oxide film formed by the CVD method as a gate insulating film of a transistor or a dielectric film for a capacitor. And reliability is improved. The steps after FIG. 5C are as follows.
A contact hole for forming a contact between the wiring portion and the first or second layer is opened, and a material serving as the wiring and the transparent driving electrode, a Nesa film, a metal having a thickness of several hundreds or less, or the like is formed by sputtering or vapor deposition. Apply and photoetch. When it is difficult to directly contact a silicon thin film such as a Nesa film, a contact-dedicated material such as Au or Ni-Cr is added to the contact portion. The transistor formed by the above method has low mobility only by the above-described processing, and therefore requires the following measures. FIG. 6A shows the mobility at 10 V of a transistor formed by a high-temperature process by forming a first-layer silicon thin film by a low-pressure CVD apparatus while changing the deposition temperature. Deposition temperature is 60
It has been found through experiments that the mobility is sharply improved at 0 ° C. or lower. Therefore, as a first contrivance, in order to improve the mobility and ensure the response, it is preferable to form the first silicon thin film at a temperature of 600 ° C. or less by a low pressure CVD apparatus. FIG. 7 is a circuit diagram showing the O at 10 V of the transistor.
The FF leak current I _{C is changed} to the thickness t of the first silicon thin film.
_This is plotted with changing _si . The inventor has found through experiments that a film thickness of 3700 ° or less results in a leakage current of 500 PA or less, which is no problem in use. Next, as a second contrivance, it is conceivable to locally perform high-temperature annealing on the first silicon thin film so that the substrate is not affected by a laser or an electron beam. FIG. 6B shows the mobility of a transistor obtained by illuminating a silicon thin film formed in the same manner as in the above-described case A with a laser beam by a Q switch of 0.12 mJ per pulse. It can be seen that it is further improved. In addition, the mobility of the transistor by a low-temperature process obtained by depositing a high-melting glass at 500 ° C. to 540 ° C. and then performing laser annealing under the same conditions almost coincides with the curve of FIG. This indicates that local annealing using a laser beam, an electron beam, or the like is effective in both low-temperature and high-temperature processes. (Embodiment 2) FIG. 8 shows a configuration example of a cell according to a second embodiment of the present invention.
(A) is a plan view, and an address line 51 is a data line 50.
Are the source, the drive electrode and the electrode 52 of the capacitor are the drains, the gates of the channels 54 of the transistors. The GND line 53 is formed at the same time as the address line 51 and forms a capacitance between the GND line 53 and the electrode 52. FIG. 8B shows a cross section taken along the line AB in FIG. 8A. To explain an example of the manufacturing process, polysilicon is grown on a glass substrate 57 as a silicon thin film by about 3000 °. . However, in some cases, in order to improve adhesion, a thin SiO ₂ may be formed in advance. Further, after forming the gate 50 and the capacitor electrode 53 by photo-etching, about 15
A SiO ₂ film 55 of 00 ° is grown as a gate insulating film and a dielectric film of a capacitor. Thereafter, a second layer of polysilicon is applied, a pattern is formed by photo-etching, and P ions are implanted into the portions other than the channel portion 54 using a resist mask to form source / drain electrodes and data line wiring portions.
A liquid crystal drive electrode also serving as a capacitor electrode is formed. Since the transistor performance (threshold value, conductance) is insufficient in this state, laser is irradiated to the channel portion 54 locally or uniformly over the entire substrate to weld the polysilicon in a short time. The performance is improved by solidifying and growing the grains. Further, the activation of the impurities of the source / drain electrodes can be performed. This is what is called laser annealing. The feature of this structure is that, contrary to FIG. 4, the gate of the transistor uses the first-layer silicon thin film and the channel uses the second-layer silicon thin film. Arbitrarily high-density diffusion is possible, and a gate oxide film obtained by oxidizing the first silicon thin film or a gate insulating film on the first silicon film is
A dielectric film for forming a capacitor for holding electric charges can be used, and a process for forming an oxide film is sufficient in one process. Another feature is that the first silicon film becomes the address line and the GND line, and the second silicon film becomes the data line wiring even if no new wiring material is provided as shown in FIG. 4, the process of depositing the wiring material and performing the photoetching can be omitted, and the process is further simplified. In this method, a silicon film is used as a transparent driving electrode of the liquid crystal.
Below this, the effect is great because it is sufficiently transparent. Embodiment 3 FIG. 9 shows a cross section of a cell structure according to a third embodiment of the present invention by a low-temperature process in which a cell is formed on a normal glass substrate. A silicon film is formed on the glass substrate 70 by a low-temperature film formation method such as a sputtering method or a plasma CVD method, and P ions or B ions are implanted over the entire surface. Next, the gate 73 and the capacitor electrode 72 are formed by photoetching. Further, an insulating film 74 is formed. We are also still used SiO ₂ or the like by low-temperature growth. In addition, the source / drain of the transistor, the capacitor and the second electrode for double use as the drive electrode
The silicon film of the layer is also formed at a low temperature. This polysilicon is not doped at all, or is implanted with a sufficient amount of B ions to enhance the threshold value. Thereafter, annealing is performed by irradiating a laser beam locally or entirely. A part of the laser beam is absorbed by the first layer of silicon, but is transmitted through the glass substrate 70. Therefore 1
Activation of the ion-implanted impurities in the silicon of the layer, appropriate beam energy for the growth of the second polysilicon grains (particularly the channel portion 78), and appropriate time (pulse laser Interval, CW
When processing is performed with laser (depending on the scanning speed), annealing can be performed within a range that hardly affects the glass substrate. The features of this method are that laser annealing can greatly reduce the effect on the glass substrate compared to conventional thermal annealing, so that low-cost glass can be used. The feature is that the characteristics (particularly, mobility) of the transistor can be improved by growing the grains of the film. Thereafter, Al is applied and photoetched to form source / drain electrodes 76 and 77. Since it is difficult to make contact between Al and silicon as they are, a little heat treatment or a weak laser beam may be applied thereafter. FIG. 10 shows a simple cross section of a liquid crystal display device using the matrix substrate of the present invention. A liquid crystal 68 is sandwiched between a transparent substrate 65 on which a transparent driving electrode 67 is mounted and a glass 66 on which a common electrode 69 made of a Nesa film is mounted. Furthermore, after sandwiching with the polarizing plates 62 and 63, the reflecting plate 6
Add 4. In this way, the light incident from above almost passes through the electrode 67 and is reflected by the reflection plate 64 and is sensed by the human eye. The transistor constituted by the manufacturing method of the present invention comprises an external drive circuit for an active matrix,
That is, the shift register and the sample hold circuit can be formed on the same substrate. FIG. 11 shows an example of a gate line side driving circuit using a transistor formed by the manufacturing method of the present invention. The shift register cell 80 includes four transistors 81 to 84 and one bootstrap capacitor 85. The clock is a start pulse SP "1" potential by the input is a phase of φ ₁ and φ ₂ is slide into transferred in synchronization with the clock. Is input to the output D ₁ to D _m are gate lines of each shift register, as shown in Results Figure 12, slide into sequentially selects the gate lines. The input transfer gate transistor 81 is used for the shift register input, and T ₁
~ Once stored in TN, by bootstrap capacity,
D "1" is written to ₁ to D _m. If not used this transfer gate is short-circuited to the D ₁ and T ₂ and T ₃ ......, there is much to be larger than the bootstrapping slap capacitance of the gate line capacitance C _Gi, patterns increases,
Decreases yield. Also written in D _{1 to} D _m
To discharge 1 "to 0", the transistor 84 has T ₃
However, if this shift register operates at a low frequency, it will malfunction even with a slight leak, so a potential fixing transistor 83 is added to improve the yield and stabilize the operation. Then, it is refreshed to the “0” level every half cycle of the clock. FIG. 13 shows an example of a driving circuit on the data line side in a liquid crystal device using a transistor formed by the manufacturing method of the present invention. The shift register cell 86 includes a bootstrap capacitor 88 and a transistor 8 necessary for operation.
9 and 91 and a reset transistor 90 for selecting a shift register to be described later. A start pulse SP is applied to the first stage via an input gate 87. Each shift register output S _{1 to} S _m is a capacitance C _D1 that parasitics a sample-and-hold transistor H _{1 to} Hm signal) to a data line.
Let ~ C _Dm sample and hold. The data line side driving circuit is high speed because it performs all the processing within one scanning line, and it is not necessary to consider leakage current. However, on the contrary, it is necessary to secure high speed operation and to realize high speed operation. It is necessary to consider suppressing the increasing power consumption. This shift register is input when only one bit out of m bits is "1", and the video input V, S (video signal or data is not written, so that power consumption other than the clock is small in synchronization with the scanning signal. . the sample and hold transistor H ₁ ~Hm but is quite fast switching request, by the bootstrap operation to the gate input, because it is applied at nearly twice the amplitude of the clock signal as shown in FIG. 14, very 15 shows a case where these elements are actually arranged on an active matrix substrate, data-side shift registers 90 and 91, and a dummy cell for forming a feedback signal at the last stage. 94, 95 and sample-and-hold transistor H ₁ ~Hm are arranged is located vertically control. The gate-side shift registers 92 and 93 and the dummies 96 and 97 are arranged in left-right contrast.The peripheral circuits are not necessarily two-sided, and only one of them is required, but a plurality of shift register rows are prepared in consideration of the yield. Naturally, the number of rows may be four or eight, but an example of two rows is shown here: The following advantages are obtained by forming the drive circuit shown in FIG. First, since the clock frequency on the data line side is as high as several MHz, the parasitic capacitance of the clock line consumes more than the internal power consumption of the shift register, especially in bulk silicon, the connection between the wiring capacitance of the clock line and the substrate. Since the capacitance is more than 100 PF, the speed of the clock is reduced and the power consumption becomes 10 mA or more. The quantity is number P
F, the power consumption can be extremely reduced and the speed can be improved. Next, for bulk silicon, for example, FIG.
When the source potential of the transistor 82 increases, the threshold value increases due to the back gate effect. As a result, in order to obtain a necessary signal voltage, the gate T
_It is necessary to increase the voltage of ₁ and eventually increase the signal level of the clock or considerably increase the area of the bootstrap capacitor 85. However, in the structure of the present invention, the substrate of the transistor is floating, and there is no back gate effect. Therefore, the clock amplitude can be small, so that the power consumption can be reduced and the bootstrap capacitance can be small. The bootstrap capacitance in the peripheral driving circuit of the present invention is different from the charge holding capacitor, and basically uses an insulating film between a gate and a channel forming a transistor. This requires that the bootstrap capacitance has a variable inter-electrode capacitance depending on the gate voltage, which is the upper electrode. Therefore, the lower electrode of the capacitance is made of a low-concentration or non-doped silicon film. As described above, when the cell portion of the active matrix and the peripheral drive are simultaneously formed using the silicon thin film on the insulating substrate, the connection becomes easy, and the overall cost is reduced. Considering that the peripheral drive circuit is constituted by a non-inverting rain-shear shift register as shown in FIGS. 11 and 13 and that the parasitic capacitance is much lower, etc.
The overall power consumption can be reduced, and at the same time, the yield can be improved and the cost can be reduced. According to the present invention, the following excellent effects can be obtained. (A) It is possible to crystallize the silicon thin film by irradiating the silicon thin film to be a channel region with a laser beam or an electron beam. (B) After forming the silicon thin film to be one electrode of the channel region and the storage capacitor, the laser beam or the electron beam is applied to the silicon thin film to be the channel region and one electrode. Can grow. [0044]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a cell used in a conventional active matrix. FIG. 2 is a plan view of a conventional cell. FIG. 3 is a configuration diagram of a cell according to the first embodiment of the present invention. FIGS. 4A and 4B are a plan view and a sectional view, respectively. FIGS. 5A, 5B, and 5C are manufacturing process diagrams. FIG. 6 is a diagram showing characteristics of a silicon thin film. FIG. 7 is a diagram showing characteristics of a silicon thin film. FIGS. 8A and 8B are cell configuration diagrams of a second embodiment of the present invention. FIG. 9 is a diagram showing a cell configuration according to a third embodiment of the present invention. FIG. 10 is a cross-sectional view when assembled to the active matrix panel of the present invention. FIG. 11 is a diagram illustrating an example of a peripheral driver circuit used in the present invention. FIG. 12 is an operation waveform diagram of the peripheral drive circuit of the present invention. FIG. 13 is a diagram showing an example of a peripheral driver circuit used in the present invention. FIG. 14 is an operation waveform diagram of the peripheral drive circuit of the present invention. FIG. 15 is a diagram illustrating an example of a peripheral driver circuit used in the present invention. [Description of Signs] 7, 8, 9 ... Contact hole 10 ... Transistor 11 ... Upper electrode 13 of polysilicon of capacitor 3 ... Al ... Transparent low-resistance elements 26, 45, 50, 52, 75... Second-layer silicon thin films 28, 40, 51, 53, 72, 73. Channels 33, 57, 70... Substrates 36, 41, 55, 74... Gate insulating films 37, 46... Capacitive insulating films 62, 63 ... Polarizing plate 64 ... Reflecting plates 65, 66 ... Transparent substrate 67 ... Transparent driving electrode 68 ... ... Nesa films 76, 77 ... Al 85, 88 ... Boot strap Capacity 89 ............ active matrix 90, 91, 92, 93 ... shift register

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-55-162224 (JP, A)                 ITEJ Technical Report, Electronics               , Vol. 4, No. 23 (1980.10)               pp. 33-38                 Nikkei Electronics, No. 252,               November 24, 1980, pp. 66−73

Claims (1)

(57) [Claims] In a method for manufacturing a thin film transistor in which a gate electrode and a channel region of a thin film transistor are opposed to each other via a gate insulating film on a substrate, a step of forming a silicon thin film to be one electrode of the channel region and the storage capacitor; Irradiating a laser beam or an electron beam to a silicon thin film which is to be one electrode of a channel region and a storage capacitor to anneal the silicon thin film.