JP2853222B2 - Multiplication circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit suitable for application to a modulation / demodulation circuit, a frequency conversion circuit, a gain control circuit, a monolithic filter, and the like.

[Summary of the Invention]

According to the present invention, the first and second constant current sources having the same constant current Ix and one of the anode and the cathode are commonly connected to the first constant current source, and the ratio of the saturation current is N-
The first and second diodes set to 1: 1 (where N> 2) and one of the anode and the cathode are commonly connected to a second constant current source, and the ratio of the saturation current is reduced. , 1:
The third and fourth diodes set to N-1 and the respective bases were commonly connected to the other electrodes of the second and fourth diodes, and the ratio of the saturation current was set to N-1: 1. First and second transistors, and third and fourth transistors whose bases are commonly connected to the other electrodes of the first and third diodes, and whose ratio of the saturation current is set to 1: N-1. A third constant current source having a constant current of Iy, and a common current connected to each of the emitters of the first and third transistors; Has a fourth constant current source of Iy, and the difference between the sum of the currents flowing through the first and third diodes and the sum of the currents flowing through the second and fourth diodes is equal to the input current i. And the difference between the collector currents of the second and third transistors is obtained as Output current io Thus, the S / N can be improved without increasing the integration capacity.

[Conventional technology]

The analog multiplication circuit is widely used as a basic analog circuit in modulation / demodulation circuits, frequency conversion circuits, gain control circuits, monolithic filter circuits, and the like. Hereinafter, a conventional analog multiplication circuit (generally called a Gilbert multiplication circuit or multiplication cell) will be described with reference to FIGS. 6 and 7. FIG.

FIG. 6 shows a conventional analog multiplication circuit.
In D _1, D ₂ are diodes, each anode connected to each other, a constant current 2Ix is flowed to the anode connection point. Operating transistors Q ₁₆ and Q ₁₇ constitute a differential amplifying circuit (8), the base of which transistor Q ₁₆ and Q ₁₇ are connected to each of the cathodes of respective diodes D ₂ and D _1. The emitters of the transistors Q ₁₆ and Q ₁₇ are connected to each other, and the emitter connection point is connected to a constant current source (not shown) having a constant current of 2Iy.

Then, the currents flowing through the diodes D ₁ and D ₂ are Ix + i and Ix, respectively.
When (i-input current signal) x-i was set to be, the collector current of the transistor Q _16, Q ₁₇ are respectively Iy + io, Iy-
It is assumed that io (i is an output current signal) is achieved.

In this multiplying circuit, when the saturation current Is flows through the diodes D ₁ and D ₂ and the operating transistors Q ₁₆ and Q ₁₇ , the forward drop voltages of the diodes D ₁ and D ₂ are represented by V ₁ and V ₂ , respectively. _Assuming that the base-emitter voltages of the transistors ₁₆ and Q ₁₇ are V ₃ and V ₄ , respectively, the following equation is established.

V ₁ −V ₂ −V ₃ + V ₄ = 0 (1) By rewriting this equation (1), the following equation is obtained.

V _t in the above equation (2) is V _t = kT / q (k is Boltzmann's constant, T is absolute temperature, and q is electron charge), and its voltage is approximately 26 mV at room temperature. By modifying the above equation (2), the following equation (3) is obtained.

When the output current io is obtained from the above equation (3), the following equation (4) is obtained.

As is apparent from the above equation (4), the output current io is obtained by multiplying the input current signal i by the ratio (Iy / Ix) of the constant currents Iy and Ix. The output current signal io can be changed with respect to the current i.

Next, with reference to FIG. 7, offset and noise in the above-described multiplication circuit will be described. FIG. 7 is a diagram in which an offset voltage source and a noise voltage source are equivalently inserted into the multiplication circuit described with reference to FIG. Therefore, the sixth
The same reference numerals are given to the portions corresponding to those in the drawings, and the overlapping description will be omitted.

First, the offset will be described. _Assuming that the offset voltage of the entire multiplication circuit is _Voff2 , the DC voltage source is equivalently shown in the figure. This offset voltage V _off2 is
Inconsistent saturation current between diodes D ₁ and D _2, caused by the mismatch of the saturation current between the transistors Q ₁₆ and Q _12, the value is substantially 1～2MV. When husband between the collectors of the differential transistors Q ₁₆ and Q ₁₇ s flow output current (offset current) is denoted by i ₁ and i ₂ when the offset voltage V _off2 occurs, these output currents i ₁ and i ₂ Next It can be represented by the following equation.

As is apparent from the above equations (5) and (6), the ratio of the output current to Iy, that is, the ratio of the offset currents i ₁ and i ₂ is determined by the offset voltage V _off2 , respectively. Therefore, to reduce the values of the offset currents i ₁ and i ₂ , the offset voltage must be reduced.

Next, noise of the multiplication circuit will be described. The noise generated in each portion of the multiplier circuit, the transistors Q ₁₆ and Q ₁₇
Of the collector current, shot noise of the base current, thermal noise due to the resistance of the base, and excess noise (1 / f noise and burst noise). Also, the diode D ₁ and D _2, the same noise and shot noise of the collector current of the transistor Q ₁₆ and Q ₁₇ is generated.

The most inevitable transistor Q ₁₆ among the above-mentioned noises
In the figure, en ₁₃ and en ₁₄ are those obtained by converting the shot noise of the collector current of Q ₁₇ into voltage, and en ₁₁ and en ₁₂ are obtained by converting the shot noise of the current of the diodes D ₁ and D ₂ into voltage, respectively. Is equivalently shown as an AC voltage source, and this will be described below.

 The voltage of the noise at the unit frequency is given by the following equation.

If en _{11 to} en ₁₄ in equations (7) and (8) are set to en _o , the following equation (9) is obtained.

Next, i _n far To the following equation is obtained a noise current in the output currents i ₁ and i _2.

As is apparent from the above equations (9) and (10), the noise increases in proportion to the half power of the DC current Iy, and the maximum value of the output current increases in proportion to the DC current Iy. Therefore,
The dynamic range becomes wider in proportion to the half power of the current Iy.

In addition, PAUL R. GRAY (Paul Earl Gray) and ROB
Book "ANALY" by ERT G.MEYER
10.3 Analog Multi of "SIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS" (analysis and design of analog integrated circuits)
-Pliers Employing the Bipolar Transistor (analog multiplier using bipolar transistors) (561st to 5th)
75 page) describes a Gilbert multiplication circuit.

[Problems to be solved by the invention]

By the way, when the above-described conventional multiplying circuit is used for a gain control circuit and a filter circuit that require a wide dynamic range in an audio circuit, for example, the offset and noise may deteriorate the S / N of the audio circuit. There is. In particular, when the above-described multiplier circuit is used in a monolithic filter circuit in which a filter circuit is integrated, the monolithic filter circuit has a built-in integration capacitor, and a multiplication current Iy of the multiplier circuit is used in order to obtain a desired cutoff frequency with a small capacitor. Has a low S / N because it becomes a very small current.

Therefore in order to improve the S / N is a multiplication current Iy may be large and, while in thermal noise and diodes D ₁ and D ₂ of the thermal noise by the base of the resistance of the transistor Q ₁₆ and Q ₁₇ is large Become. In contrast, although the size of the transistors Q ₁₆ and Q ₁₇ and diode D ₁ and D ₂ can be reduced in large Tosureba thermal noise, it is IC form as a monolithic filter circuit described above It will be difficult.

In view of such a point, an object of the present invention is to propose a multiplying circuit capable of improving S / N without increasing the integration capacity.

[Means for solving the problem]

The present invention comprises a first and a second constant current source R ₁ , Q ₉ ; R ₂ , Q ₁₀ having a constant current Ix equal to each other, and one of the anode and the cathode having the first constant current source R x. are commonly connected to the _1, Q _9, the ratio of the saturation current, N-1: 1 (where, N> 2) and the first and second diodes Q _1, Q _2, which is set to the anode and cathode One of the electrodes is commonly connected to the second constant current sources R ₂ and Q ₁₀ , and the third and fourth diodes Q ₃ and Q ₄ whose saturation current ratios are set to 1: N−1. And each base is commonly connected to the other electrodes of the second and fourth diodes Q ₂ and Q ₄ ,
First and second transistors Q ₅ and Q ₆ whose saturation current ratios are set to N−1: 1, and bases commonly connected to the other electrodes of the first and third diodes Q ₁ and Q ₃ And the third and fourth transistors Q having a saturation current ratio set to 1: N-1.
₇ , Q8 and a third constant current source connected in common to the emitters of the first and third transistors Q ₅ , Q ₇ and having a constant current of Iy.
It has a fourth constant current source connected in common to the emitters of the second and fourth transistors Q ₆ and Q ₈ and having a constant current of Iy, and includes first and third diodes Q ₁ and Q ₃ . When the difference between the sum of the flowing currents and the sum of the currents flowing through the second and fourth diodes Q ₂ and Q ₄ is equal to the input current I, the second and third transistors Q ₂ and Q ₃ The output current io obtained as the difference between the collector currents of It is made to become.

[Action]

According to the present invention described above, the first and third diodes
The sum of the currents flowing through Q ₁ and Q ₃ and the second and fourth diodes Q
_When the difference between the sum of the currents flowing through Q ₂ and Q ₄ is made equal to the input current i, the output current io obtained as the difference between the collector currents of the second and third transistors Q ₂ and Q ₃ becomes It becomes.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. (3) a current mirror circuit composed of the transistors Q ₉ and Q ₁₀ of PNP type, the emitter of the transistor Q ₉ and Q ₁₀ are connected to each other through respective resistors R _1, R _2,
A constant current 2Ix flows into the connection point, and the respective bases are connected to each other. The collector and base of the transistor Q ₉ is connected directly, there is a diode configuration.

Q ₁ and Q ₂ are NPN type transistors whose emitter area ratios, that is, their saturation current ratios are N−1: 1 (where N> 2). Each collector and base are directly connected, and each diode is connected. Make up.

Q ₃ and Q ₄ are NPN-type transistors whose emitter area ratio, that is, their saturation current ratio is 1: N−1, and their respective collectors and bases are directly connected to each other to form diodes.

The respective collectors of the transistors Q ₁ and Q ₂ are connected to the respective collectors of the transistor Q ₉ of the current mirror circuit (3),
The collectors of the transistors Q _3, Q ₄ is connected to the collector of the transistor Q _10. The emitters of the transistors Q ₁ and Q ₃ are connected to each other, and the emitters of the transistors Q ₂ and Q ₄ are connected to each other.

(1) is a differential amplifier circuit including NPN-type differential transistors Q ₅ and Q ₇ , and (2) is a differential amplifier circuit including NPN-type differential transistors Q ₆ and Q ₈ . The ratio between the emitter areas of the transistors Q ₅ and Q ₆ , that is, the ratio between the saturation currents is set to N−1: 1, and each base thereof is commonly connected to each emitter of the transistors Q ₂ and Q ₄ . The ratio of the emitter area of the transistors Q ₇ and Q ₈ , that is, the ratio of the saturation current is set to 1: N−1,
The respective bases are commonly connected to the respective emitters of the transistors Q ₁ and Q ₃ . The emitters of the transistors Q ₅ and Q ₇ are commonly connected to a constant current source (not shown) having a constant current of Iy. The emitters of the transistors Q ₆ and Q ₈ have a constant current source of a constant current of Iy (see FIG. (Not shown).

The respective collector currents I ₆ and I ₇ of the transistors Q ₆ and Q ₇ are subtracted by a subtraction circuit (4). Output to output terminal OUT.

 Next, the operation of the circuit of FIG. 1 will be described.

Transistor Q ₉ constituting current mirror circuit (3)
And current flowing through the emitter of Q ₁₀ are respectively both Ix.
The currents flowing through the emitters of the diode-connected transistors Q ₁ and Q ₃ are I ₁ and I _{3, respectively,} and the sum of these currents is Ix +
i. Also, diode-connected transistors Q ₂ and Q ₄
The current flowing through the emitter and respectively I ₂ and I _4, to sum Ix-i of those currents. Here, i is an input current signal.

Further, a differential amplifier circuit (1) is configured. Transistor Q ₅
And the current flowing through the emitter of Q ₇ and respectively I ₅ and I _7, to equalize the sum of the current in the constant current Iy of the above. Further, the differential transistors Q ₆ and Q ₈ constituting the differential amplifier circuit (2)
The current flowing through the emitter and respectively I ₆ and I _8, to equalize the sum of the current in the constant current Iy of the above.

Then, the saturation current of the transistors Q ₂ , Q ₃ , Q ₆ , Q ₇ is Is,
Therefore, the saturation current of the transistors Q ₁ , Q ₄ , Q ₅ , and Q ₈ is (N−
1) Let it be Is.

The difference in the base-emitter voltage of the transistor Q ₁ and Q ₂ are, the transistors Q ₅ and equal to the difference between the base-emitter voltages of Q _7, the difference is the transistor base-emitter voltage of the transistor Q ₄ and Q ₃ Q equal to the difference between the base-emitter voltage of ₈ and Q _6. Further, the sum of the currents I ₁ and I ₂ flowing through the emitters of transistors Q ₁ and Q ₂ is equal to the constant current Ix, the sum of the currents I ₅ and I ₇ flows emitter of the transistor Q ₅ and Q ₇ is a constant current Iy be equivalent to. Therefore, the following equation is obtained.

I ₁ + I ₂ = Ix ‥‥ (11) I ₅ + I ₇ = Iy ‥‥ (12) From the above, the following equation is established.

By rearranging the above equations (11) to (13), the following equations are obtained.

I ₅ = I ₁ · Iy / Ix ‥‥ (14) I ₇ = I ₂ · Iy / Ix ‥‥ (15) Also, for the transistors Q ₃ , Q ₄ and Q ₆ , Q ₈ , the same equation is obtained. .

I ₃ + I ₄ = Ix ‥‥ (16) I ₆ + I ₈ = Iy ‥‥ (17) By rearranging the above equations (16) to (18), the following equations are obtained.

I ₆ = I ₃ · Iy / Ix ‥‥ (19) I ₈ = I ₄ · Iy / Ix ‥‥ (20) By the way, each of the currents I _{1 to} I ₈ is a steady value having no change and an input current signal i. And the change due to Ino for steady state
(N = 1,2,3,4,5,6,7,8), and the change is Δin (n = 1,
2,3,4,5,6,7,8). First, I _{1 to} I ₄ will be described below.

From the above equations (21) to (24), the following equations are obtained.

Δi ₁ −Δi ₂ = Δi ₃ −Δi ₄ = 0 (25) Δi ₁ + Δi ₃ = Δi ₂ + Δi ₄ = i (26) From the above equations (25) and (26), the following equations are obtained. .

Δi ₂ = Δi ₁ , Δi ₄ = Δi ₃ 27 (27) Therefore, it is sufficient to consider the change between Δi ₁ and Δi ₂ .

For I ₆ and I ₇ are then the following equation is obtained from equation (19) and (15).

The output current i ₀ is the difference current. Therefore, the following equation is obtained.

As is apparent from the above equation (30), it can be seen that the multiplying circuit according to the present invention has the same multiplying function as that of the conventional example shown in FIG.

Next, an explanation will be given with reference to FIG. 3 showing an equivalent circuit in which an offset voltage source and a noise voltage source are inserted in the multiplication circuit described with reference to FIG.

V _off1 is the sum of the offset voltages of the multiplication circuit.

First, the offset will be described. Transistor Q ₅ ~
Assuming that the transfer conductance of Q ₈ is Gm (= ∂i _out / ∂V _off ), the transfer conductance Gm is represented by the following equation.

Here, _assuming that the offset current is i _off1 , the offset current i _off1 can be expressed by the following equation.

FIG. 2 shows the improvement rate of the offset with respect to N based on the above equation (32). As is clear from FIG. 12, the improvement rate increases as the value of N increases. That is, misalignment of the saturation current between the transistors Q ₁ and Q ₃ between the transistors Q ₂ and mismatch and differential saturation current between Q ₄ transistors Q ₅ and Q ₇ between the differential transistors Q ₆ and Q ₈ is Since the averaging is performed, the offset voltage V _off1 is reduced, and the improvement rate is increased.

Next, noise will be described. In the figure, en ₁ ~en ₈ shows the shot noise of the collector currents of the transistors Q ₁ to Q ₈ of the multiplying circuit as a voltage, as en _d is a summary of the noise voltage en ₁ ~en _4, en _t noise voltage summarizes the en ₅ ~en _8. The noise voltage per unit frequency is given by the following equation.

Here, the en _d with en _t, becomes a following formula.

Further, en _d and en _t are collectively referred to as en _x , and the equation is as follows. It becomes. When the noise current is set to in and the noise current in is calculated based on the above equations (39) and (31), the following equation is obtained.

Therefore, the equation showing the noise current of the multiplication circuit described with reference to FIG. It can be seen that the noise current in is smaller than that of FIG.

FIG. 4 shows the noise improvement [dB] with respect to N based on the above equation (40). As is apparent from FIG. 4, the improvement [dB] increases as the value of N increases.

Next, another embodiment according to the present invention will be described with reference to FIG. 5, but portions corresponding to those of the multiplying circuit of FIG.

In the embodiment of FIG. 1, a diode-connected transistor
Current mirror circuit was on the collector side of the Q ₁ ~Q ₄ (3)
Instead, in the embodiment of FIG. 5, the emitter of the transistor Q ₁ to Q _4, is provided with a current mirror circuit (7). The Karetomira circuit (7) consists of the transistors Q ₁₁ and the transistor Q ₁₂ of the diode-connected transistor Q _11, the collector of Q ₁₂ are each transistors Q _1, Q _3; Q
₂ and Q ₄ are connected to the emitter connection point, and transistors Q ₁₁ and Q
Each of the ₁₂ emitters is connected to a negative power supply -B through resistors R ₃ and R _{4 respectively.}
Connected to.

The collectors (bases) of the diode-connected transistors Q ₁ and Q ₂ are connected to the respective bases of the transistors Q ₇ and Q ₈ , and a current Ix−i flows through the connection point, and the diode-connected transistors Q ₃ and Q ₃ the collectors of Q ₄ (base) is connected to the bases of the transistors Q _5, Q _6, it flows a current Ix + i to the connection point.

(5) is a current mirror circuit, which is a diode-connected PN
Comprising a P-type transistor Q ₉ and the transistor Q _10, the respective collectors are respectively connected to the collectors of the respective transistors Q _6, Q _7, the respective emitter is connected to the positive power source + B via respective resistors R _1, R ₂ , And constitute the load of the transistors Q ₉ and Q ₁₀ , respectively. Note that the output terminal OUT from the collector of the transistor Q ₇ is outputted.

(6) in the current mirror circuit is composed of transistors Q ₁₅ and the transistor Q _13, Q ₁₄ of the diode connection,
The emitters of the transistors Q ₁₅ , Q ₁₃ , Q ₁₄ are respectively connected to resistors R ₇ ,
It is connected to a negative power source -B through R _5, R _6. And
Constant current Iy is flowed in the transistor Q _15, the constant current Iy is the collectors of the transistors Q _13, Q ₁₄ flowing to the collector connected to the emitters of the respective transistors Q _5, Q ₇ and Q _6, Q _8.

The multiplying circuit described with reference to FIG. ₁ obtains outputs from the emitters of the diode-connected transistors Q ₁ , Q ₃ and Q ₂ , Q ₄ , respectively. ₁ , Q ₂ and Q ₃ , Q _{4, respectively} , the output is obtained from the collector, and the direction of the current source of Ix ± i is opposite,
The basic operation of the multiplication circuit is the same as that of the circuit shown in FIG.

The first feature of the above-described embodiment is that a nonlinear element (first to fourth diodes Q ₁ , Q ₂ ) having an inverse function to the nonlinear transfer conductance of the common emitter differential transistor pair (1), (2) is used. , Q ₃ , Q ₄ ) are provided before the common-emitter differential transistor pair (1), (2), and the input current i is distorted in advance, so that the relationship between the input / output currents i, i _o as a whole is It is a linear point.

The second feature of the above-described embodiment is that the output is taken out from the transistors Q ₆ and Q _{7 having} a small emitter area of the common emitter differential transistor pair (1) and (2) to reduce the steady current. , The area ratio of the emitters is used, whereby noise and offset can be improved.

〔The invention's effect〕

According to the present invention described above, the first constant current Ix equal to the first
And one of the anode and the cathode is commonly connected to the first constant current source, and the ratio of the saturation current is set to N−1: 1 (where N> 2). The first and second diodes, and one of the anode and the cathode are commonly connected to a second constant current source, and the third and the third have a saturation current ratio set to 1: N-1. A fourth diode, first and second transistors each having a base commonly connected to the other electrode of the second and fourth diodes, and having a saturation current ratio set to N−1: 1; A base is commonly connected to the other electrodes of the first and third diodes, and the third and fourth transistors have a saturation current ratio set to 1: N−1, and the first and third transistors have the same ratio. A third constant current source connected in common to each emitter and having a constant current of Iy, and second and fourth transistors A fourth constant current source connected to each emitter in common and having a constant current of Iy, the sum of the currents flowing through the first and third diodes and the sum of the currents flowing through the second and fourth diodes; Is equal to the input current i, the output current io obtained as the difference between the collector currents of the second and third transistors is As a result, S / N (noise and offset characteristics) can be improved without increasing the integration capacity.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a graph showing an improvement rate of offset, FIG. 3 is a circuit diagram for explaining offset and noise in the embodiment, and FIG. FIG. 5 is a circuit diagram showing another embodiment, FIG. 6 is a circuit diagram showing a conventional example, and FIG. 7 is a circuit diagram for explaining offset and noise in the conventional example. . (1) and (2) are differential amplifier circuits, (3) is a current mirror circuit, (4) is a subtraction circuit, Q ₁ , Q ₂ , and ΔQ ₁₀ are transistors, and R ₁ and R ₂ are resistors. is there.

Claims (1)

(57) [Claims] A first and a second constant current source having a constant current Ix equal to each other, and one of an anode and a cathode is commonly connected to the first constant current source, and a ratio of a saturation current The first and second diodes are set to N−1: 1 (where N> 2), and one of an anode and a cathode is commonly connected to the second constant current source, Third and fourth diodes having a saturation current ratio set to 1: N−1, each base is commonly connected to the other electrode of the second and fourth diodes, and the saturation current ratio is The first and second transistors set to N−1: 1, each base is commonly connected to the other electrode of the first and third diodes, and the ratio of the saturation current is 1: N−1. Common to the set third and fourth transistors and the emitters of the first and third transistors A third constant current source having a constant current of Iy, and a fourth constant current source having a constant current of Iy and commonly connected to the emitters of the second and fourth transistors. When the difference between the sum of the currents flowing through the first and third diodes and the sum of the currents flowing through the second and fourth diodes is made equal to the input current i, the second
And the output current io obtained as the difference between the collector currents of the third transistor and A multiplication circuit characterized by the following.