JP2853445B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to an output circuit having an electrostatic protection function.

[0002]

2. Description of the Related Art Generally, an input protection circuit in a MOS integrated circuit clamps a voltage applied to an internal circuit by breakdown of a diode or a field transistor and causes a voltage drop by a protection resistor. As an output protection circuit, an output transistor having a relatively large transistor length is connected without intentionally providing a protection circuit, and this serves as a clamp element. When an electrostatic discharge stress is applied to this protection circuit, the most susceptible to breakdown is the gate insulating film, which reduces the voltage per unit area by using a transistor with a larger gate width to prevent this breakdown. By increasing the distance between the contact portion and the gate electrode by the connection portion between the drain region and the wiring, a voltage drop due to resistance is caused. In such a conventional output circuit having an electrostatic protection function, the correlation between the distance between the gate and the contact and the electrostatic withstand voltage (ESD withstand voltage) is based on the curve A- in FIG.
1, B-1. Curve A-1 shows the result of examining the presence or absence of abnormality by discharging the charge charged in the 100 pF capacitor to the output terminal through a 1.5 kΩ resistor. Curve B-1 shows the charge charged in the 200 pF capacitor. Is directly discharged to the output terminal. FIG. 2 (a),
As shown in FIG. 2B, the MOS transistor inserted between the output signal wiring 12 connected to the output terminal and, for example, the ground wiring 13 has a gate oxide film 4 having a thickness of 18 nm and a width of 1.
It has a gate electrode 6 of 3 μm and a channel width of 450 μm
It is.

In order to obtain good electrostatic withstand voltage for the reasons described above, it is common to use a huge MOS transistor having a channel width of 400 μm or more and a gate-contact distance of 3.5 μm or more in an output circuit. .

[0004]

With the increasing integration of semiconductor devices, it is very important to form many transistors in a smaller area. Terminals that cannot use a large protection resistor, such as output terminals, have an electrostatic protection function by forming an output circuit using transistors with a large channel width and a large gate-contact distance. With the integration,
When the gate insulating film becomes thinner, a larger gate width and a larger gate-contact distance are required to form an output circuit having a sufficient withstand voltage. There was a problem that it had to be upset.

[0005]

A semiconductor integrated circuit according to the present invention has a source region and a drain region selectively formed on a surface portion of a semiconductor substrate, and is sandwiched between the source region and the drain region of the semiconductor substrate. A source electrode and a drain made of a metal silicide film contacting the source region and the drain region via a contact hole provided in the first interlayer insulating film, and a gate electrode attached to the region via the gate insulating film; An electrode, and a source electrode wiring and a drain electrode wiring that are in contact with the source electrode and the drain electrode through through holes provided in the second interlayer insulating film, respectively. virtual line connecting the said contact hole on the drain region are provided interlink the gate electrode and oblique, and the con Lower transfected hole of the through hole
An output circuit including a MOS transistor arranged at a position separated from the position is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing an embodiment of the present invention.
FIG. 2B is a sectional view taken along line YY in FIG.

A transistor formation region 3 is defined by a field oxide film 2 selectively formed on the surface of a P-type silicon substrate 1. The transistor forming region 3 has a thickness of 1
An 8-nm gate oxide film 5 is formed, and a plurality of comb-shaped gate electrodes 6 are formed on the surface thereof. The width of the gate electrode is 1.3 μm. Source region 4s and drain region 4d are formed in self-alignment with gate electrode 6.
Source electrode 9 contacting source region 4s and drain region 4d through contact hole 8a (0.8 μm × 0.8 μm) provided in interlayer insulating film 7 having a thickness of 0.85 μm.
s and a drain electrode 9d are provided. The source electrode 9s and the drain electrode 9d is a thickness of 1.0 .mu.m, a width of 2 [mu] m WSi _x film _(x = 2.5~2.7). The interval between the contact holes 8a is 4.1 μm. Thickness 0.4
Through hole 11 provided in 8 μm interlayer insulating film 10
It is provided with a source electrode wiring 14s, and the drain electrode wiring 12l contact with the WSi _x film through. The source electrode wiring 13s and the drain electrode wiring 12d are made of an aluminum alloy film having a thickness of 1.0 μm, and are respectively connected to the ground wiring 13a and the output signal wiring 12a (connected to a bonding pad (not shown)).

No contact hole 8a is provided below the through hole 11, and the contact hole 8a (also the through hole 11 ) on the source (or drain) region and the drain (or source) region with the gate electrode 6 interposed therebetween. through holes 1 1 (or contact hole 8a) are arranged. Note that the channel width is 450 μm.

The relationship between the ESD withstand voltage and the distance between the contact hole and the gate electrode in this embodiment is shown by curves A-2 and B-2 in FIG. The test conditions are the same as the conditions when the curves A-1 and B-1 were obtained. This shows that the distance between the contact hole and the gate electrode can be reduced by about 2.7 μm.

An actual output circuit has a channel width of 90.
A MOS transistor of approximately the same structure of 0 μm is inserted between a power supply line (not shown) and the output signal line 12a.

Output signal wiring and source (or drain)
There is WSi _x film between the region, the distance between the contact portion of the contact portion and the drain region in the source region, can be increased, provided protection resistance is distributed between an output signal line and an output circuit It will be. Therefore, E
Although the SD withstand voltage is improved, the resistance between the output terminal and the source or the drain is parallel connection in proportion to the number of contacts, so that the resistance is low, and the operation speed and other characteristics are hardly affected. That is, the withstand voltage against breakdown of the insulating film generated between the drain and the gate can be improved without changing the characteristics and without increasing the mask area.

[0012]

As described above, according to the present invention, a large voltage relaxing effect can be locally obtained with a small resistance between the output signal wiring connected to the output terminal and the source or drain portion. This can prevent the voltage applied to the insulating film between the source or drain and the gate electrode from rising to some extent, and as a result, the gate electrode of the transistor and the contact which is the connection portion between the source or drain region and the metal wiring can be prevented. It is possible to obtain the same effect as increasing the distance between the parts. That is, by using this structure, there is an effect that the electrostatic withstand voltage can be improved without increasing the layout area of the output circuit having the electrostatic protection function.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention (FIG. 1A).
And a sectional view (FIG. 1B).

FIG. 2 is a plan view (FIG. 2A) and a cross-sectional view (FIG. 2B) showing a conventional example.

FIG. 3 is a graph showing a relationship between an ESD withstand voltage and a distance between a contact hole and a gate electrode.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 Field oxide film 4 d Drain region (N-type diffusion layer) 4 s Source region (N-type diffusion layer) 5 Gate insulating film 6 Gate electrode 7 Interlayer insulating film 8, 8a Contact hole 9 d Drain electrode 9 s Source electrode 10 Interlayer insulating film 11 Through hole 12, 12a Output signal wiring 12d Drain electrode wiring 13, 13a Ground wiring 13s Source electrode wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 21/8234 H01L 27/06 H01L 27/088 H01L 29/78

Claims (2)

(57) [Claims] 1. A semiconductor device comprising: a source region and a drain region selectively formed on a surface portion of a semiconductor substrate; and a region interposed between the source region and the drain region of the semiconductor substrate, the gate region being attached via a gate insulating film. A gate electrode, a source electrode and a drain electrode made of a metal silicide film that are in contact with the source region and the drain region through contact holes provided in the first interlayer insulating film, respectively,
A source electrode wiring and a drain electrode wiring that are respectively in contact with the source electrode and the drain electrode through through holes provided in the interlayer insulating film, and the contact hole on the source region and the drain electrode on the drain region. An imaginary line connecting the contact hole is provided obliquely to the gate electrode , and the contact hole is
A semiconductor integrated circuit comprising an output circuit including a MOS transistor disposed at a position separated from a lower portion of the device. 2. The semiconductor integrated circuit according to claim 1, wherein the metal silicide film is a tungsten silicide film.