JP2854772B2 - Analog switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog switching circuit, and more particularly to an analog switching circuit used for an A / D converter or a D / A converter built in a one-chip microcomputer or the like.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit diagram of a conventional analog switching circuit (hereinafter referred to as "switching circuit"). A conventional switching circuit is an N-channel MOSF
An ET (hereinafter abbreviated as “NTr”) 20 and a P-channel MOSFET (hereinafter abbreviated as “PTr”) 21 are connected in parallel to form an input / output unit, and a substrate electrode of the NTr 20 is connected to a ground voltage. to V _SS, the substrate electrode of PTr21 is connected to the power supply voltage V _DD. Further, a signal (hereinafter, referred to as a “CTL signal”) for controlling ON / OFF of the switching circuit is input to the gate electrode of PTr 21, and NTr 2.
The inverted CTL signal is input to the 0 gate electrode via the inverter 24 including the NTr 22 and the PTr 23.

Incidentally, the PT constituting the inverter unit 24
The source electrode of r23 is connected to the power supply voltage V _DD ,
Since the source electrode of the NTr 22 is connected to the ground voltage V _SS , the CTL signal is at the power supply voltage V _DD level in the “H” state and is at the ground voltage V _SS level in the “L” state.

[0004] The above switching circuit is a CMO
Since the S process can be configured relatively easily and has good performance, it is generally widely used in A / D converters and D / A converters.

[0005]

However, the conventional switching circuit shown in FIG. 4 has the following problem. As shown in the ON resistance characteristic diagram (V _DD ≦ 3 V) of the conventional switching circuit shown in FIG.
When the power supply voltage becomes about 3 V or less, the on-resistance (R _ON (Ω)) in the switching circuit rapidly increases when the analog input voltage is near the intermediate level (1/2 V _DD ) of the power supply voltage. is there.

Using the switching circuit as described above, A
When a / D converter is configured, at a power supply voltage of 3 V or less,
Due to the influence of the on-resistance in the switching circuit, a large error (5% or more of the analog input voltage) occurs near the analog input voltage of 1/2 _VDD . This is because a transient phenomenon occurs between a capacitor used in a comparator unit (not shown) provided in an output unit and an on-resistance in a switching circuit, and an analog voltage is sufficiently supplied during a sampling period in A / D conversion. This is because conversion is performed without charging the capacitor.

The on-resistance of the switching circuit increases when the power supply voltage is lower than about 3 V. The reason is that the on-resistance increases as the input voltage approaches the ground voltage _Vss level. V _DD
As the N-channel MOSFET increases in on-resistance as it approaches the level, it is connected in parallel. Therefore, as shown in FIG. 5, the input voltage becomes an intermediate level (1/2) of the power supply voltage.
Around V _DD ), the on-resistances of the N-channel MOSFET and the P-channel MOSFET both increase,
This is because the on-resistance in the switching circuit, which is a combined resistance of the two on-resistances, rapidly increases.

The above phenomenon greatly depends on the threshold voltage of the MOSFET. The higher the threshold voltage, the higher the on-resistance, and the lower the threshold voltage, the lower the on-resistance. Further, the point at which the combined resistance has the maximum value is determined by the ratio between the threshold voltages of the N-channel MOSFET and the P-channel MOSFET.

As a technique for lowering the value of the combined resistance, firstly, it is considered to lower the threshold voltage. However, it is not preferable in view of the variation in the threshold value in production and the influence on other circuits.

Also, two switching circuits are connected in series to form an N-channel M which constitutes one switching circuit.
OSFET and P-channel MOSFET substrate electrode and analog input electrode, and N-channel MOSFET and P-channel M constituting another switching circuit
A method of connecting the substrate electrode of the OSFET and the analog output electrode to reduce the on-resistance is disclosed in JP-A-4-2737.
Are disclosed in 16 JP, in the above method, P ^- forming a well, further, the N ^{- -} N on the substrate on the well P ^-
Wells must be formed, which is not possible with a low-cost CMOS process.

According to the present invention, the potential of the gate electrode of the N-channel MOSFET and the P-channel
It is an object to provide an analog switching circuit in which the on-resistance at a low voltage is reduced by using a CMOS process by boosting the potential of a substrate electrode of an OSFET when an input / output unit is in an on state.

[0012]

An analog switching circuit according to the present invention is an analog switching circuit having an input / output unit in which an N-channel first transistor and a P-channel second transistor are connected in parallel. The semiconductor device further includes a means for increasing the potential of the gate electrode of the transistor and the potential of the substrate electrode of the second transistor at least during a period in which the input / output portion is in a conductive state.

[0013]

With the above configuration, the gate electrode potential of the first transistor and the substrate electrode potential of the second transistor are boosted at least during the switch-on period, and the on-resistance characteristic of the switching circuit of the embodiment of the present invention shown in FIG. Figure (V _DD
As shown in (3V), the on-resistance of the switching circuit can be kept low even when the power supply voltage is 3 V or more by using a normal CMOS process.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment. FIG. 1 is a circuit diagram of an analog switching circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the analog switching circuit.

In FIG. 1, an N-channel MOSFET
(Hereinafter abbreviated as "NTr") 1 and P-channel MOS
An FET (hereinafter abbreviated as “PTr”) 2 is connected in parallel to form an input / output unit, an inverter unit 11 is composed of NTr3 and PTr4, an inverter unit 12 is composed of NTr5 and PTr6, and an inverter unit is composed of NTr7 and PTr8. 13 constitutes a first electrode 10 _a of the capacitor 10 is connected to the output of the inverter section 12, a second electrode 10 _b and the PTr4 and PTr8 source electrode of the capacitor 10, P
The drain electrode of Tr9 and the substrate electrode of PTr2 are connected to have the same potential.

The output of the inverter 11 is NTr
1, the substrate electrode of NTr1 is grounded, and the source electrode of PTr9 is connected to the power supply voltage _VDD .

Further, during the sampling period, a CTL signal which becomes "L" level is input to the inverter unit 11 and the gate electrode of PTr2.
The “L” level PWL signal is input to the inverter units 12 and 13. In this embodiment,
During the same period, both the CTL signal and the PWL signal are “L”.
Although it is at the level, the CTL signal may be at the “L” level within the “L” level period of the PWL signal.

Note that NTr 3, 5, 7 and PTr 4, 6,
8, the source electrode and the substrate electrode are connected, and the drain electrode of the PTr 9 and the substrate electrode are connected.

Next, the operation of the analog switching circuit according to one embodiment of the present invention will be described with reference to FIGS.
First, when the PWL signal is at “H” level, the outputs of the inverter unit 12 and the inverter unit 13 are at “L” level. Therefore, the voltage of the first electrode 10 _a of the capacitor 10 0 (V) becomes also,, PTr9 is turned on, P
Since the potential of the drain electrode of the Tr9 is the power supply voltage V _DD (V), the potential V of the second electrode 10 _b of capacitor 10
_DD (V).

Next, when the PWL signal is changed from "H" level to "L" level, the inverter sections 12 and 1
The output of No. 3 becomes "H" level. Accordingly, the PTr 9 is turned off, and the potential of the first electrode 10 _a of the capacitor 10 becomes V _DD (V).
The potential of _b is approximately 2V _DD (V).

By the above operation, P
The potential of the source electrode of Tr4 becomes approximately 2V _DD , and the potentials of the gate electrode of NTr1 and the substrate electrode of PTr2 in the input / output section become approximately 2V _DD . Therefore, when the CTL signal is set to the “L” level when the PWL signal is the “L” level and the input / output unit is turned on, the gate voltage of the NTr1 and the substrate voltage of the PTr2 are increased to about twice the power supply voltage. . Therefore, even in a low-voltage power supply having a power supply voltage of 3 V or less, an increase in the on-resistance of the switching circuit can be suppressed.

In the above embodiment, the PWL signal and C
Although the TL signal and the TL signal are used as different signals, a configuration using a CTL signal as the PWL signal may be adopted.

[0023]

As described in detail above, by using the present invention, an analog switching circuit having a small on-resistance can be formed even when the power supply voltage V _DD is 3 V or less.
When used for A / D converter and D / A converter,
The problem that the accuracy is degraded by the on-resistance of the switching circuit even when the power supply voltage V _DD is 3 V or less is eliminated, and the same accuracy as when the power supply voltage V _DD is about 3 V or more can be secured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an analog switching circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the analog switching circuit.

FIG. 3 is an ON resistance characteristic diagram of the analog switching circuit.

FIG. 4 is a circuit diagram of a conventional analog switching circuit.

FIG. 5 is an on-resistance characteristic diagram of a conventional analog switching circuit.

[Explanation of symbols]

 1.3.5.7 N-channel MOSFET 2.4.8.6. 9 P-channel MOSFET 10 Capacitor 11, 12, 13 Inverter section

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/687 H03K 17/06

Claims (1)

(57) [Claims] 1. An analog switching circuit having an input / output unit in which an N-channel first transistor and a P-channel second transistor are connected in parallel, wherein the potential of the gate electrode of the first transistor and the potential of the second transistor are
An analog switching circuit including means for increasing a potential of a substrate electrode of a transistor at least during a period in which the input / output portion is in a conductive state.