JP2856376B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate in which thin film transistors and the like are formed in a matrix as switching elements.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device, a counter substrate is disposed opposite to an active matrix substrate on which thin film transistors (hereinafter referred to as "TFT") and the like are formed in a matrix. It has a structure in which is sandwiched.

The structure of a conventional active matrix substrate will be described. FIG. 7 is a plan view of a picture element which is one unit constituting a conventional active matrix substrate, and FIG. 8 is a sectional view taken along line AA of FIG.

As shown in FIG. 7, in an active matrix substrate, a gate wiring 102 made of tantalum (Ta) and a source wiring 103 made of titanium (Ti) are arranged on a glass substrate 101. Two TFTs connected to the source wiring 103 are formed for each picture element. It is not necessary to form two TFTs for each picture element, and some TFTs are formed one by one.

Referring to FIG. 8, the structure of the TFT will be described in detail.

In the illustrated TFT, a first gate insulating film 104 made of tantalum oxide (Ta ₂ O ₅ ) is formed so as to cover a gate wiring 102 provided on a glass substrate 101. A second gate insulating film 10 made of silicon nitride (SiN _x ) covering the entire surface of the film 104;
5 are formed. A semiconductor layer 106 made of intrinsic amorphous silicon (hereinafter, referred to as “a-Si (i)”) is formed on the second gate insulating film 105 so as to partially overlap with a position where the gate wiring 102 is formed. Semiconductor layer 10
6, an etching stopper layer 107 made of SiN _x is formed on the central portion. On both sides of the etching stopper layer 107 of the semiconductor layer 106, a contact layer 108 made of n ⁺ type amorphous silicon (hereinafter referred to as “a-Si (n ⁺ )”) is formed on the etching stopper layer 1.
07 is formed. Contact layer 10
A source wiring 103 is formed so as to cover one (the left side in the drawing) of the wiring layer 8, and a drain wiring 109 made of Ti is formed to cover the other (the right side in the drawing) of the contact layer 108. A pixel electrode 110 made of indium tin oxide (ITO) is formed so as to partially overlap with the drain wiring 109.

A method for manufacturing a conventional active matrix substrate having the above structure will be described.

First, Ta is deposited and patterned on a glass substrate 101 to form a gate wiring 102, and the surface of the gate wiring 102 is anodized to form a first gate insulating film 104.

Next, S which becomes the second gate insulating film 105
The iN _x layer, the a-Si (i) layer serving as the semiconductor layer 106, and the SiN _x layer serving as the etching stopper layer 107 are successively deposited in this order, and the etching stopper layer 107 is patterned.

On the substrate 1 in such a state, a-Si (n ⁺ ) to be the contact layer 108 is deposited,
The semiconductor layer 106 and the contact layer 108 are formed by patterning together with the i (i) layer.

Next, after Ti is deposited on the entire surface of the substrate 101 by a sputtering method, a source wiring 103 and a drain wiring 109 are formed in a predetermined pattern by photolithography and etched. This etching method includes wet etching and dry etching.
There are types. In the wet etching method, etching is performed using an etchant such as hydrofluoric-nitric acid. In the dry etching method, etching is performed using a gas such as CF ₄ or SF ₆ as an etching gas. The dry etching method improves the pattern accuracy from the anisotropic etching characteristics of the dry etching as compared with the wet etching method.

Finally, ITO is deposited on the entire surface of the substrate 101 in such a state, and is patterned to form a pixel electrode 110.
To form

[0013]

In the conventional active matrix substrate as described above, as shown in FIG.
Then, on the insulating substrate 121 made of glass,
Only the stripe-shaped wiring 122 is formed.
there were. Since ITO has high resistance, it can
In a board, the resistance of the wiring 122 which is a bus line increases.
There is a problem. In response to this problem, distribution of ITO
It is conceivable to form a metal auxiliary wiring on the line.
Since TO has weak metal adhesion, metal supplementation on ITO film
Auxiliary wiring could not be formed.

[0014]

[0015]

[0016]

[0017]

[0018]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and a signal wiring and a scanning wiring are required.
It is an object of the present invention to provide an active matrix substrate which has low resistance and can obtain good display quality when used in a liquid crystal display device.

[0020]

According to the active matrix substrate of the present invention, a signal wiring and a scanning wiring are formed on a substrate by a grid.
In the shape of a circle and surrounded by the signal wiring and the scanning wiring
Pixel electrodes are arranged in a matrix,
Electrically connected to the electrode, the signal wiring, and the scanning wiring
Matrix substrate with switching element
In, the signal wiring and the scanning wiring, from the substrate side,
Wiring layer made of ITO, conductive layer made of tantalum nitride and
A metal auxiliary wiring layer made of tungsten and tantalum is formed in this order.
The three-layer structure described above achieves the above object.

[0021]

[0022]

[0023]

[0024]

According to the above arrangement, the signal wiring and the scanning wiring are
Strong adhesion to ITO on the wiring layer made of ITO
A conductive layer made of tantalum nitride is formed, and tantalum
Three-layer structure with metal auxiliary wiring layer made of metal
Low resistance on the active matrix substrate
Wiring can be realized. In particular, the wiring material and
Since tantalum is used as the material, a thin film of tantalum is generally
Becomes β-Ta having a square lattice structure and has high resistance.
On the other hand, when tantalum is deposited on nitride,
It becomes α-Ta having a cubic lattice structure and has low resistance. Obedience
Therefore, the above metal auxiliary wiring has lower resistance than a general tantalum film.
Become anti.

[0025]

[0026]

[0027]

[0028]

Embodiments of the present invention will be described below.

<First Embodiment> The structure of the active matrix substrate of this embodiment will be described with reference to FIG. FIG. 1 shows a TFT constituting an active matrix substrate of the present embodiment.
FIG.

The illustrated TFT covers a gate wiring 2 provided on a glass substrate 1 and is made of tantalum oxide (Ta).
_A first gate insulating film 4 made of ₂ O ₅ ) is formed.
A second gate insulating film 5 made of SiN _x is formed to cover the entire surface of the gate insulating film 4. A semiconductor layer 6 made of a-Si (i) is formed on the second gate insulating film 5 so as to partially overlap the position where the gate wiring 2 is formed.
An etching stopper layer 7 made of SiN _x is formed on the center of the semiconductor layer 6. On both sides of the etching stopper layer 7 of the semiconductor layer 6, a contact layer 8 made of a-Si (n ⁺ ) is formed on the etching stopper layer 7 so as to be divided. A source wiring composed of a lower source wiring 3a and an upper source wiring 3b is formed so as to cover one (left side in the drawing) of the contact layer 8, and to cover the other (right side in the drawing) of the contact layer 8 and to be integrated with the pixel electrode. A drain wiring composed of a pixel electrode / lower drain wiring 9a and an upper drain wiring 9b is formed. The drain wiring 9 of the picture element electrode and the lower drain wiring 9a
The portion that does not overlap with the element functions as a pixel electrode.

A method of manufacturing a conventional active matrix substrate having the above structure will be described with reference to FIGS.

First, as shown in FIG. 2, a Ta film having a thickness of 500 to 5,000 angstroms is deposited on a transparent insulating glass substrate 1 by a sputtering method, patterned by photolithography, and etched. The gate wiring 2 is formed. For etching the Ta film, C
There are a method of performing dry etching by converting a mixed gas of F ₄ and O ₂ into plasma, and a method of performing wet etching using a mixed solution of hydrofluoric acid and nitric acid as an etchant. In the case of performing wet etching, a Ta film having a thickness of 1000 to 10000 Å is formed between the glass substrate 1 and the Ta film.
₂ O ₅ is formed in advance so that the glass substrate 1 is not etched.

Next, as shown in FIG. 3, the upper surface of the gate wiring 2 is anodized to form Ta ₂ O ₅ having a thickness of 500 to 5000 Å.

Next, as shown in FIG.
The thickness of the gate insulating film 5 to be 500 to 6000
An Angstrom SiN _x film, an a-Si (i) film having a thickness of 50 to 1000 Å to become the semiconductor layer 6 and a 300 to 50 Å thickness to become the etching stopper layer 7.
A 00 Å SiN _x film is deposited sequentially in this order. Thereafter, patterning is performed by photolithography, and the uppermost layer of SiN _x is etched with a BHF solution (hydrofluoric acid + ammonium fluoride) to form only the etching stopper layer 7.

As shown in FIG. 5, an a-Si (n ⁺ ) film having a thickness of 200 to 2000 angstroms to be the contact layer 8 is deposited by a plasma CVD method, and then the a-Si film is formed by photolithography and etching. (N ⁺ )
The film and the a-Si (i) film are simultaneously patterned into an island shape to obtain a contact layer 8 and a semiconductor layer 6.

Next, as shown in FIG.
₂ , a single layer of any one of InO ₃ or a multilayer film of two or more materials is deposited by a sputtering method so as to have a thickness of 300 to 3000 Å, thereby forming a transparent conductive film. . On the transparent conductive film, T
a single layer of any one of i, Ta, TaN, Mo, and Al, or a multilayer film of two or more materials having a thickness of 5
A metal thin film is formed by sputtering so as to have a thickness of 00 to 5000 Å. After patterning the metal thin film by photolithography, the source wiring 3 and the drain wiring 9 are formed by etching.

There are two types of etching methods for the source wiring 3 and the drain wiring 9, a dry etching method and a wet etching method.

In the dry etching method, a parallel plate type dry etching apparatus in which electrodes are arranged to face each other is used to perform C etching.
The metal thin film is etched by converting a fluorine-based mixed gas such as F ₄ and O ₂ gas or a chlorine-based mixed gas such as CCl ₄ and O ₂ gas into plasma. In this process, since the etching rate selectivity between the transparent conductive film and the metal thin film can be sufficiently obtained, the underlying second gate insulating film 5 made of SiN _x is used.
Is not etched.

In the wet etching method, HF, HNO
Etching of the metal thin film is performed with a hydrofluoric / nitric acid-based mixed etchant such as ₃ . Also in this process, since the etching rate selectivity between the transparent conductive film and the metal thin film is sufficiently obtained, the underlying second gate insulating film 5 made of SiN _x is not etched.

Finally, as shown in FIG. 1, the transparent conductive film is patterned by photolithography and etched to form the source wiring 3, the drain wiring 9 and the picture element electrode 10. This etching includes HC
ferric chloride-based etchant, which is a mixed solution of l and FeCl ₃ , hydrogen bromide-based etchant of HBr, HCl and Zn
Only the transparent conductive film is etched by using an etching solution which is a mixed solution of the transparent conductive film and the like. These etchants do not etch SiN _x , which is the material of the second gate insulating film 5.

As described above, when the source wiring 3 and the drain wiring 9 are etched, the second gate insulating film 5
Does not hurt. As a result, the insulating properties between the source wiring 3 and the gate wiring 2 and between the drain wiring 9 and the gate wiring 2 can be improved.

The source line 3 is a lower source line 3a.
And the upper layer source wiring 3b, it has a laminated structure of at least two layers. Therefore, even if the redundancy of the source wiring increases, it is difficult to disconnect.

The active matrix substrate of this embodiment has
A liquid crystal display device formed by arranging a counter substrate having a counter electrode formed on the surface thereof and enclosing liquid crystal between the two substrates provides a point defect caused by the second gate insulating film 5 and a source wiring 2. Can reduce the probability of occurrence of linear defects due to the redundancy. As a result, the display quality is greatly improved.

<Second Embodiment> FIG. 9 is a sectional view of a main part of a metal wiring board according to the present embodiment. The illustrated metal wiring substrate is also used, for example, as an active matrix substrate. Specifically, a lower electrode wire 12 made of Ta is formed on an insulating substrate 11 made of glass, and a TaN _x layer 13 having a nitrogen content of 40 to 50 atomic% is formed on the upper surface of the lower electrode wire 12. Have been. Further, an ITO electrode wiring 14 is formed on the substrate 11 so as to partially overlap the TaN _x layer 13.

As a material for the insulating substrate 11, besides glass, quartz, silicon wafer, ceramic or the like can be used. The lower electrode wiring 12 also includes a portion functioning as an electrode.
aN _x , Ti, Al, W, Mo and the like can be used.

A method for manufacturing a metal wiring board having the above structure will be described.

First, Ta is deposited to a thickness of, for example, 3000 Å on the insulating substrate 11 by a sputtering method, and the lower electrode wiring 12 having a desired shape is obtained by photolithography.

Next, by a reactive sputtering method using nitrogen gas, the nitrogen content of Ta is adjusted to 40 to 50 atomic%.
N _x is deposited to a thickness of, for example, 700 angstroms, and a TaN _x layer 13 having a desired shape is formed by photolithography. Note that TaN _x may be formed by an ion shower doping method instead of the reactive sputtering method.

Further, ITO is deposited to a thickness of, for example, 2000 Å on the substrate 11 including the portion where the TaN _x layer 13 is formed, and an ITO electrode wiring 14 having a desired shape is formed by photolithography.

In the above metal wiring board, TaN _x
Due to the presence of the layer 13, the electrical connection resistance between the lower electrode wiring 12 and the ITO electrode wiring 14 can be made small and stable.

On the other hand, in the conventional metal wiring board, as shown in FIG. 10, a lower electrode wiring 112 made of Ta is formed on an insulating substrate 111 made of glass.
In this configuration, an ITO electrode wiring 114 is formed on the substrate 111 so as to partially overlap with the lower electrode 112. The manufacturing method is as follows. First, Ta is deposited to a thickness of 3000 Å on the insulating substrate 111 by a sputtering method, and a lower-layer electrode wiring 112 having a desired shape is obtained by photolithography. Further, the lower electrode wiring 11
ITO is deposited to a thickness of 2000 angstroms on the substrate 111 including the formation portion 2, and an ITO electrode wiring 114 having a desired shape is formed by photolithography.

Therefore, in the conventional metal wiring substrate, when Ta is used as the material of the lower-layer electrode wiring 112 as described above, the film is formed at the time of ITO film formation and at the time of heating in a later step performed at the time of mounting an electric circuit. Then, oxygen diffuses into the surface layer of the lower electrode wiring 112, and an oxide film is formed on the surface of the lower electrode wiring 112. The electrical resistance of this oxide film is large, and the specific resistance is 10 ¹⁴ Ω.
・ Cm or more. Further, the contact resistance between the oxide film and the ITO electrode wiring 114 also increases. As a result, the connection resistance between the lower electrode wiring 12 made of Ta and the ITO electrode wiring 14 becomes several tens mΩ · mm ² to several tens Ω · mm ² , and has a problem that it is unstable and has a large value.

In order to solve such a problem, the present embodiment, as described above, uses the lower electrode wiring 12 and the ITO electrode wiring 14 as described above.
And a TaN _x layer 13 is formed between them. Therefore, Ta
Nitrogen contained in the N _x layer 13 prevents diffusion of oxygen, and the specific resistance of the TaN _x layer 13 is 10 ⁻³ Ω · cm.
About small. As a result, the electrical connection resistance between the lower-layer electrode wiring 12 and the ITO electrode wiring 14 is 4 to 7 mΩ as a measured value.
・ It is small and stable as mm ² . The metal wiring substrate thus formed can be provided with a transistor or the like as necessary, and can be used as a matrix substrate for a liquid crystal display device.

<Third Embodiment> FIG. 11 is a plan view of the matrix substrate of this embodiment, and FIG. 12 is a cross-sectional view of the matrix substrate shown in FIG. 11 taken along line BB. In this matrix substrate, bus lines 25 are formed in stripes on an insulating substrate 21 made of glass. The bus line 25 has a three-layer structure as can be seen from FIG. 12, and a wiring 22 made of ITO, a conductive layer 23 made of tantalum nitride, and a metal auxiliary wiring 24 made of tantalum are formed in this order from the substrate side. I have.

As a material of the wiring 22, besides Ta,
Metals such as Ti, Nb, Al, Cu, W, and Mo and alloys containing these metals as main components can be used. For example, in the case of an alloy containing Al as a main component, Ta, Si, Cu, Zn, Ni, or the like is used as a metal other than Al.
As the material of the conductive layer 23, besides tantalum nitride, a metal nitride that can be used as the material of the wiring 22 can be used. Here, the material of the conductive layer 23 is the wiring 2
It need not be a metal nitride of the second material.

A method for manufacturing a matrix substrate having the above structure will be described.

First, an ITO film is formed on the insulating substrate 21 by sputtering or the like to a thickness of, for example, 1000 angstroms, and is patterned in a stripe shape by photolithography to form the wiring 22.

Next, for example, tantalum nitride having a thickness of 500 angstroms and tantalum having a thickness of 5000 angstroms are deposited in this order on the substrate 21 on which the wirings 22 are formed by sputtering.

Finally, the bus line 25 is formed by simultaneously patterning the tantalum nitride film for the conductive layer 23 and the tantalum film for the metal auxiliary wiring 24 into a predetermined shape by photolithography.

In the step of forming the tantalum nitride film and the tantalum film, a sputtering apparatus schematically shown in FIG. 13 is used. This sputtering apparatus is composed of three spaces separated by two gate valves 201, and a space for a loader 202, a sputtering chamber 203, and an unloader 204 is provided from one end (right side in the figure). The loader 202, the sputtering chamber 203, and the unloader 204 can be evacuated by a pump 205 provided in each of them. The sputtering chamber 203 includes at least two electrodes. A tantalum nitride target 206 having a nitrogen molar concentration of 15% produced by hot pressing is mounted on the electrode on the loader 202 side, and the electrode on the unloader 204 side is mounted on the electrode on the unloader 204 side. A tantalum target 207 is mounted. Argon and nitrogen can be appropriately introduced into the sputtering chamber 203 as a sputtering gas.

A description will be given of the contents of the tantalum nitride film and the tantalum film formed by the sputtering apparatus having the above configuration.

First, the substrate 21 is set on the loader 202, and the inside of the loader 202 is evacuated by the pump 205 to make it vacuum. Open the gate valve 201 and remove the substrate 21
The wafer is transported into the unloader 204 through the sputtering chamber 203 which has already been evacuated. While the substrate 21 is transported in the sputtering chamber 203, argon and nitrogen are introduced into the sputtering chamber 203 so that the flow ratio thereof becomes 1: 1. While the substrate 21 is transported on the tantalum nitride target 206, tantalum nitride having a nitrogen concentration of 45 to 50 atomic% is deposited on the substrate 21. At this time, the sputtering power and the transport speed of the substrate 21 are set so that the tantalum nitride having a thickness of 500 angstroms is deposited on the substrate 21 above the tantalum nitride target 206.

After moving the substrate 21 into the unloader 204, the substrate 21 is subsequently moved to the sputtering chamber 20.
3 to the loader 202. While the substrate 21 is transported in the sputtering chamber 203, only argon is introduced into the sputtering chamber 203. While the substrate 21 is transported over the tantalum target 207, tantalum is deposited on the substrate 21. At this time, the sputtering power and the transport speed of the substrate 21 are set so that tantalum having a thickness of 5000 angstroms is deposited on the substrate 21 above the tantalum target 207.

In the matrix substrate manufactured as described above, since the metal auxiliary wiring 24 is formed on the wiring 22 made of ITO, the bus line has low resistance.

On the other hand, in the conventional matrix substrate, as shown in FIG. 14, only stripe-shaped wirings 122 made of ITO are formed on an insulating substrate 121 made of glass. Since ITO has a high resistance, the resistance of the wiring 122 which is a bus line in a conventional matrix substrate increases. However, conventionally, as in this embodiment,
Metal auxiliary wiring could not be formed on the ITO film. This is because ITO has weak metal adhesion.

In this embodiment, the wiring 2 made of ITO is used.
1 with strong adhesion to ITO and nitrogen concentration of 45-5
Since the conductive layer 23 made of 0 atomic% tantalum nitride is formed, the metal auxiliary wiring 24 can be provided.

Here, the nitrogen concentration of tantalum nitride is set to 45 to 45.
The reason for setting the atomic concentration to 50 atomic% is that no tantalum nitride has a nitriding concentration exceeding 50% and the nitriding concentration is 4 atomic%.
If it is less than 5%, it cannot be used because of low adhesion to ITO.

When tantalum is used as the material of the wiring 22, there is an effect different from the case where another material is used. Tantalum has two types of crystal structures, one is a square lattice and the other is a body-centered three-dimensional lattice. Ta having a square lattice structure is called β-Ta, and the thin film has a specific resistance of 170 to 200 μΩcm. On the other hand, Ta having a body-centered cubic lattice structure is called α-Ta, and the thin film has a specific resistance of 13 to 15 μΩcm. Generally, most of the thin film of tantalum becomes β-Ta and has high resistance. But,
When tantalum is formed on a nitride, it becomes α-Ta and has low resistance. Therefore, the metal auxiliary wiring 24 of this embodiment has lower resistance than a general tantalum film.

As is clear from the above description, according to the matrix substrate of this embodiment, the wiring
Since metal auxiliary wiring is formed via nitride between them,
Low-resistance wiring can be realized.

[0070]

As is apparent from the above description, according to the active matrix substrate of the present invention, the signal wiring and the scanning
The inspection wiring is attached to the ITO wiring layer
A conductive layer made of strong tantalum nitride is formed and
Layer with a metal auxiliary wiring layer made of tantalum on top
Because it has a structure,
Thus, low-resistance wiring can be realized. Especially for wiring
Since tantalum is used as the material, tantalum is generally thin.
Most of the film becomes β-Ta having a square lattice structure,
Deposits tantalum on nitride while providing resistance
And α-Ta having a body-centered cubic lattice structure and low resistance
Therefore, the above metal auxiliary wiring is
Low resistance can be achieved. Also, this active mat
Good display quality can be obtained when the liquid crystal substrate is used for a liquid crystal display device.

[0071]

[0072]

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT constituting an active matrix substrate of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the TFT shown in FIG.

FIG. 3 is a sectional view illustrating another manufacturing process of the TFT shown in FIG.

FIG. 4 is a cross-sectional view showing another manufacturing process of the TFT shown in FIG.

FIG. 5 is a cross-sectional view illustrating another manufacturing process of the TFT shown in FIG.

FIG. 6 is a sectional view illustrating another manufacturing process of the TFT shown in FIG.

FIG. 7 shows a configuration 1 of a conventional active matrix substrate.
It is a top view of a picture element.

FIG. 8 is a sectional view taken along line AA of FIG. 7;

FIG. 9 is a cross-sectional view of a metal wiring board according to a second embodiment.

FIG. 10 is a sectional view of a conventional metal wiring board.

FIG. 11 is a plan view of a matrix substrate according to a third embodiment.

12 is a cross-sectional view of the matrix substrate shown in FIG. 11, taken along line BB.

FIG. 13 is a schematic view showing a configuration of a sputtering apparatus used for manufacturing the matrix substrate shown in FIG.

FIG. 14 is a cross-sectional view of a conventional matrix substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate wiring 3a Lower source wiring 3b Upper source wiring 4 First gate insulating film 5 Second gate insulating film 6 Semiconductor layer 7 Etching stopper layer 8 Contact layer 9a Pixel electrode and lower drain wiring 9b Upper drain wiring

Continued on the front page (72) Inventor Mikio Katayama 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Masaya Okamoto 22-22 Nagaikecho, Abeno-ku, Osaka-shi Osaka Prefecture Inside Sharp Corporation (72 Inventor Yukiya Nishioka 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Japan Inside Sharp Corporation (72) Inventor Manabu Takahama 22-22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Katsuhiro Kawai Osaka 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Sharp Corporation (72) Inventor Kisuke Shimada 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72) Inventor Hidenori Nekoto Abeno, Osaka, Osaka 22-22 Nagaike-cho, Ward Inside Sharp Corporation (72) Inventor Makoto Miyago 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Prefecture Inside Sharp Corporation (72) Masahiro Date Date 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Prefecture (72) Kondo, the inventor of Sharp Corporation Naofumi, 22-22 Nagaike-cho, Abeno-ku, Osaka, Japan Inside Sharp Corporation (72) Inventor Atsushi Atsushi 22-22, Nagaike-cho, Abeno-ku, Osaka City, Osaka Inside Sharp Corporation (72) Mitsui Hirata Osaka, Osaka 22-22, Nagaike-cho, Abeno-ku Sharp Corporation (56) References JP-A-4-276723 (JP, A) JP-A-2-170135 (JP, A) JP-A-2-234125 (JP, A) Kaihei 2-234132 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G02F 1/1343 G02F 1/136 500

Claims (1)

(57) [Claims] 1. A signal wiring and a scanning wiring are formed in a grid on a substrate.
In the area surrounded by the signal wiring and the scanning wiring.
The pixel electrodes are arranged in a matrix and
Pole, the signal wiring, and the scanning wiring
On an active matrix substrate with switching elements
Then, the signal wiring and the scanning wiring are separated from the substrate side by ITO.
Wiring layer, conductive layer made of tantalum nitride and tantalum
Three-layer structure in which metal auxiliary wiring layers made of
Active matrix substrate.