JP2856433B2 - Video signal encoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture signal encoding apparatus using a band compression technique.

[Conventional technology]

As a coding method of a moving picture signal coding apparatus using a conventional band compression technique, for example, the materials of the Institute of Electronics and Communication Department of Imaging Engineering, document number IE87-70, from page 13 to page 18 `` 32kbps ~ 1.5Mbps Also known as "color video codec". FIG. 7 briefly shows this encoding method. In encoding, encoding is performed for all significant blocks in the frame. Then, the encoded data is temporarily stored in the buffer memory, and when the encoding of the frame is completed, the frame frames are dropped until the amount of data accumulated in the transmission-side buffer decreases below a predetermined threshold. Is used.

[Problems to be solved by the invention]

In the conventional assimilation image signal encoding apparatus described above, the encoded signal is temporarily stored in a large-capacity buffer memory, and then gradually read out by the clock of the transmission line, so that the encoded signal passes through the buffer memory. In bi-directional video communications such as videophones, this response is transmitted to the other party, and the other party's response is transmitted to the other party in order to transmit the encoded signal to the buffer memory. , Twice, and the delay time is doubled. As a result, the response of the other party is delayed, which is very unnatural.

[Means for solving the problem]

A moving picture signal encoding apparatus according to the present invention comprises: a first or second storage unit for storing an image frame of an input moving picture signal for each frame; From the first storage means (or the second storage means), which is storing the newest input video signal, encodes the image frame of the newest input video signal over a plurality of frame times, and terminates the encoding of the frame. At the same time, encoding means for encoding the most recently stored image frame of the input moving image signal from the second storage means (or the first storage means) over a plurality of frame times and outputting as encoded data, The encoded data from the encoding means is temporarily stored and then output to a transmission path, and further, the code instructing encoding of the input video signal in accordance with the amount of the encoded data stored. A line memory for outputting a run signal, and having a.

[Action]

In low bit rate video coding, highly efficient coding is performed to compress information of several hundred to one thousandth of an input video signal. However, reducing the amount of encoded information per screen to several kilobits or less is very severe.
In order to further reduce the amount of information per screen, a very coarse coding parameter is used, and as a result, the image quality of the coded image is significantly deteriorated, and the image becomes very difficult to see. Therefore, in the current low bit rate video coding, instead of coding all the frames of the input video signal, the coding is performed by thinning out the frames to such an extent that they do not seem visually unnatural. By doing so, the amount of information per frame is ensured so that image quality degradation is minimized.

The moving picture signal encoding method of the present invention effectively utilizes the time obtained by the above-described frame thinning, and gradually encodes every n lines. As shown in FIG. 1, the encoding device of the present invention has a frame memory for two screens in an input portion, and is composed of a control unit, an encoder, a variable length encoder, and a line memory. The encoding method of the present invention will be described with reference to FIGS. For example, the input moving image signal of the F1 frame shown in FIG. 2 is written into the frame memory 1a shown in FIG.
As for the encoding speed at this time, the encoding is executed at a period longer than the frame period of the input moving image signal by utilizing the fact that advanced information compression is performed by frame thinning or the like as described above. Since the encoding speed is lower than the speed of the input moving image signal, the read address of the frame memory 1a does not pass the write address. Then, the writing to the frame memory 1a stops when the F1 frame of the input moving image signal ends. If the input video signal is F2
At the same time as switching to the frame, writing of the input moving image signal to the frame memory 2a is started. The reading of the frame memory at this time is continued until all the F1 frames stored in the frame memory 1a are read. Therefore, as shown in FIG. 2, if the encoding of the F1 frame takes up to the first half of the F3 frame, the reading of the frame memory 1a is continued to the first half of the F3 frame. Therefore, when the F2 frame ends and the F3 frame starts, the frame memory 2a discards the moving image signal stored at the time of the F2 frame and starts writing the moving image signal of the F3 frame. F3
When the encoding of the F1 frame is completed, the reading from the frame memory 1a is performed in the frame memory.
F3 being switched to 2a and being stored in frame memory 2a
Start encoding the frame. This frame memory 1
The control of writing and reading of a and 2a is performed according to an instruction of the control unit 3a. The control unit 3a performs the above-described write / read control. Regarding read control, when the encoding execution signal given from the line memory 9a indicates that encoding is to be executed, the frame memory 1a or the frame memory 1a is controlled. A read instruction is given to 2a. The encoding execution signal is also supplied to the encoder 8a, and the execution of the encoding is stopped. Therefore, the reading control of the frame memory and the encoding operation of the encoder 8a are performed in synchronization. Therefore, the encoding is performed when reading out the frame memory, and the encoding is also stopped when reading out the frame memory is stopped. In this way, the coding is gradually advanced. The variable-length encoder 8b further reduces the redundancy of the encoded data by using an efficient code such as a Huffman code. Then, the variable-length encoded data is temporarily stored in the line memory 9a, read out by the transmission line clock, and supplied to the transmission line. Only when the amount of data stored in the line memory 9a at this time is smaller than a predetermined threshold, an encoding execution signal indicating the execution of encoding is given to the control unit and the encoder. As described above, the frame memories 1a and 2a for two screens are placed in front of the encoder 8a, and the input moving image signal is written into any one of the frame memories for each frame. In accordance with the amount of encoded data stored in the output line memory 9a, the moving image signal of the latest frame stored in When the encoding of the frame is completed, the reading of the frame memory is switched to the other, and the moving image signal of the latest frame stored in the switched frame memory at that time is encoded. If the encoding speed and the transmission line speed are matched by the small-capacity line memory 9a, the time required for the encoded data to pass through the buffer memory is reduced, and the delay of the encoded image is reduced. be able to. Also, since encoding is performed asynchronously with the timing of the frame of the input signal, encoding of the next frame can be started immediately after encoding of one frame is completed. There is no need to output a signal. Therefore, the coding efficiency is also improved.

〔Example〕

Next, the present invention will be described with reference to the drawings. An embodiment of the present invention will be described with reference to FIG. 3, FIG. 4, FIG. 5, and FIG.

In FIG. 3, an input video signal is supplied to the frame memories 1 and 2 and the encoding control circuit 3 via a line 100. The frame memory 1 has a line from the encoding control circuit 3.
When the write control signal supplied via the line 311 is 1, the input video signal supplied via the line 100 is stored at the address indicated by the address signal supplied via the 310. Similarly to the frame memory 1, when the write control signal supplied via the line 320 is at the address indicated by the address signal supplied via the line 310 from the encoding control circuit 3, The input video signal supplied via the line 100 is stored. Frame memory 1
Is read when the read control signal supplied from the encoding control circuit 3 via the line 312 is "1". The moving image signal read from the frame memory 1 is supplied to the subtractor 4 via a line 140.
The input moving image signal stored in the frame memory 2 is read when the read control signal supplied from the encoding control circuit 3 via the line 321 is 1. Frame memory 2
Is executed after the reading of the frame memory 1 is completed. The moving image signal read from the frame memory 2 is supplied to the subtractor 4 via a line 140.

Next, the encoding control circuit 3 will be described with reference to FIG. An input video signal is supplied to the sync separator 30 via a line 100. The synchronization separator 30 separates synchronization from the input moving image signal, and generates a frame pulse, a clock pulse, and a switching signal twice as fast as the clock pulse based on the separated synchronization. The clock pulse generated by the sync separator 30 is supplied to a write counter and a read counter via a line 3031. The frame pulse generated by the sync separator 30 is supplied to the write counter 31 via a line 3034.
Is supplied to the write / read controller 34. Further, the switching signal generated by the sync separator 30 is supplied to the switch 33. The write counter 31 resets the counter value at the beginning of the frame pulse supplied from the sync separator 30 and counts up according to the clock supplied from the sync separator 30. The write address signal generated by the write counter 31 is supplied to the switch 33. Read counter 32
Counts up in accordance with the clock supplied from the sync separator 30 only when the encoding execution signal supplied via the line 93 indicates the execution of encoding. Further, the read counter 32 resets the value of the counter by a reset signal supplied from the write / read control unit 34 via the line 3432. The read address signal generated by the read counter 32 is supplied to the switch 33 and the write / read controller 34. The switch 33 converts the address signals supplied from the write counter 31 and the read counter 32 into a synchronous separator.
The switching of the address signal is performed according to the switching signal supplied from 30. The multiplexed signal of the write / read address of the output of the switch 33 is sent to the frame memory via a line 310.
Supplied to 1,2.

Next, the write / read control unit 34 will be described with reference to FIGS. A read address signal is supplied to the determiner 340 via a line 3234 in FIG. Judge 340
Assuming that the number of encoded pixels in one screen is N, the value of N is detected and a reset pulse is generated. For example, it is assumed that the encoding of each screen is completed at the respective times t1, t2, t3, and t4 of 3432 in FIG. Then, the reset pulse of the output of the determiner 340 becomes the time t1, t2, t3, t4
Occurs at each time. The reset pulse output from the decision unit 340 is connected to the D-type flip-flop 341 and the line 3432
Is supplied to the read counter 32 via the. The D-type flip-flop 341 has a Q output and an output. By connecting the output to the D input, the output of the D-type flip-flop is inverted every time a reset signal is supplied from the decision unit 340. That is, each time the reading of the frame memory is completed, the output of the D-type flip-flop is inverted, as shown by 312 and 321 in FIG. Therefore, reading of the frame memories 1 and 2 can be controlled by the output of the D-type flip-flop. The signal of the Q output of the D-type flip-flop 341 is supplied to the frame memory 1 via a line 312 as a read control signal. The signal at the output of the D-type flip-flop 341 is supplied to the frame memory 2 via the D input of the D-type flip-flop 342 and the line 321 as a read control signal. The D-type flip-flop 342 shapes the signal supplied from the D-type flip-flop 341 by a frame pulse supplied via a line 3034, and outputs the signals 311 and 320 in FIG.
become that way. The output of the D-type flip-flop 342 is supplied via a line 311 as a write control signal for the frame memory 1. The signal at the output of the D-type flip-flop 342 is supplied via a line 320 as a write control signal for the frame memory 2. The encoding control circuit 3 generates various control signals as described above. Third
Return to the figure. The subtractor 4 subtracts the input moving image signal supplied via the line 140 from the prediction signal supplied from the frame memory 7 to obtain an inter-frame prediction error signal. The prediction error signal output from the subtractor 4 is supplied to the quantizer 5. The quantizer 5 quantizes the prediction error signal supplied from the subtractor 4, and supplies the quantized prediction error signal to the variable length encoder 8 and the adder 6.
The adder 6 adds the quantized prediction error signal supplied from the quantizer 5 and the prediction signal supplied from the frame memory 7 to obtain a local decoded signal. The local decoded signal output from the adder 6 is supplied to a frame memory 7. The frame memory 7 writes the local decoded signal supplied from the adder 6 only when the encoding execution signal supplied via the line 93 indicates that encoding is performed. Then, the written local decoded signal is delayed by one frame to obtain an inter-frame prediction signal. The inter-frame prediction signal output from the frame memory 7 is supplied to the subtractor 4 and the adder 6. The variable-length encoder 8 performs variable-length encoding on the quantized prediction error signal supplied from the quantizer 5 using an efficient code such as a Huffman code, and supplies the encoded signal to the line memory 9. The line memory 9 temporarily stores the code supplied from the variable length encoder 8, reads out the code according to the transmission line clock supplied via the line 91, and matches the speed with the transmission line speed. When the amount of the stored code is smaller than the predetermined amount, the line memory 9 outputs a signal indicating the execution of the coding, and the code generated by the coding is stored in the line memory 9 and the amount is stored. When a predetermined amount is exceeded, the signal indicating the execution of encoding is stopped. The output signal of the line memory 9 is
It is supplied to the transmission line via line 90.

[Effects of the Invention] As described above, in the present invention, a frame memory for two screens is placed in front of an encoder, an input moving image signal is written into one of the frame memories for each frame, and at the start of encoding, Performs and stops encoding the moving image signal of the latest frame stored in the frame memory in small increments according to the amount of encoded data stored in the output line memory. When the encoding of the frame is completed, the reading of the frame memory is switched to the other at the same time, and the moving picture signal of the latest frame stored in the switched frame memory at that time is encoded. If the speed of the encoding and the speed of the transmission line are matched by a small-capacity line memory,
The time required for the encoded data to pass through the buffer memory is reduced, and the delay of the encoded image can be reduced. In addition, since encoding is performed asynchronously with the timing of the frame of the input signal, encoding of the next frame can be started immediately after encoding of one frame is completed, and a dummy for preventing underflow in the buffer memory is provided. There is no need to output a signal, and coding efficiency can be improved.

[Brief description of the drawings]

FIGS. 1 and 2 are block diagrams and timing diagrams for explaining the operation of the present invention, and FIGS. 3, 4, 5 and 6 are diagrams for explaining an embodiment of the present invention. FIG. 7 is a block diagram and a timing diagram, and FIG. 7 is a block diagram showing an example of a conventional moving picture signal encoding apparatus. 1, 2, 7 ... frame memory, 3 ... encoding control circuit, 4 ...
Subtracter, 5 quantizer, 6 adder, 8 variable length encoder, 9 line memory, 30 sync separator, 31 write counter, 32 read counter, 33 switch, 34 write Read control unit, 340 ... determiner, 341, 342 ... D type flip-flop.

Claims (1)

(57) [Claims] 1. A first or second storage means for storing an image frame of an input video signal for each frame, and the first storage means storing a newest input video signal when an encoding execution signal is given. Storage means (or second
From the storage means), the most recently stored image frame of the input moving image signal is encoded over a plurality of frame times, and simultaneously with the end of the encoding of the frame, the second storage means (or the first storage means) ), Encoding means for encoding the image frame of the newest input video signal that is being stored over a plurality of frame times and outputting it as encoded data, after temporarily storing the encoded data from the encoding means. A line memory that outputs to the transmission path, and further outputs the encoding execution signal that instructs the encoding of the input moving image signal in accordance with the amount of the encoded data that has been stored. Image signal encoding device.