JP2857590B2 - Circuit for enhancing noise characteristics of semiconductor devices. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise characteristic enhancement circuit applied to a semiconductor device for removing a noise signal supplied to the semiconductor device and preventing a malfunction of the semiconductor device.
In particular, the present invention relates to a noise characteristic enhancement circuit for a semiconductor device capable of removing a noise signal, compensating for an effective input signal having a small pulse width, and operating the semiconductor device accurately.

[0002]

2. Description of the Related Art The semiconductor device includes a bootstrap circuit for boosting a voltage of an input signal and a precharge circuit for precharging a bit line. The bootstrap circuit and the precharge circuit must compensate for operation feedback for a certain period of time or more in order to generate a normal output. For this reason, the input signal supplied to the semiconductor device must include a pulse for maintaining a specific logic state for a predetermined time or more.

The noise characteristic enhancement circuit applied to the semiconductor device removes a noise signal included in the input signal as one filter circuit. However, although the noise characteristic enhancement circuit of the conventional semiconductor device can accurately remove the noise component included in the input signal, it is not preferable because the pulse width of the input signal is reduced or the input signal is removed. Due to the decrease in the pulse width of the input signal and the loss of the input signal, the bootstrap circuit and the precharge circuit cannot operate normally and generate an error-containing output. As a result, the conventional noise characteristic enhancement circuit of the semiconductor device has a problem that the width of the input signal is reduced or the input signal is removed to cause a malfunction of the semiconductor device. The above-mentioned problems of the conventional noise characteristic enhancement circuit of a semiconductor device will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing an example of a conventional noise characteristic enhancement circuit of a semiconductor device. In FIG. 1, the noise characteristic enhancement circuit includes a delay line including four inverters (10) to (16) connected in series to an input line (11), an input signal delayed by the delay line, and the input line. A NAND gate (18) for performing a NAND operation on an input signal from the line (11).

The delay line delays an input signal by a fixed time corresponding to the sum of the propagation delay times of the four inverters (12) to (16). Actually, the delay line delays an input signal supplied to the input line 11 as shown in FIGS.
B and the delayed input signal as shown in FIG.
Supply to the gate (18).

When a pulse as shown in FIG. 2A having a pulse width smaller than the delay time of the delay line is supplied to the input line 11, the NAND gate 18 removes the pulse shown in FIG. 2C. Such an output signal is generated on the output line (13). Conversely, when an input signal as shown in FIG. 3A having a pulse width larger than the delay time of the delay line is input, the NAND gate (1
8) The pulse width of the input signal is removed by the delay time of the delay line to generate a low logic pulse signal as shown in FIG. 3C. The width of the pulse signal shown in FIG. 3C corresponds to the remaining period of the pulse width of the input signal that is removed by the delay time of the delay line.

FIG. 4 is a diagram showing a different example of the noise characteristic enhancement circuit of the conventional semiconductor device. Referring to FIG. 4, a conventional noise characteristic enhancement circuit includes four inverters (2) connected in series between an input line (21) and an output line (23).
0, 22, 24, 26). The first and third inverters (20, 24) include a P-MOS transistor (not shown) having a large channel width and an N-MOS transistor (not shown) having a small channel width. The pulse width of the input signal is removed by the entire delay time of the MOS transistor. In addition, the second and fourth inverters (22, 26) also include a P-MOS transistor (not shown) having a small channel width and an N-MOS transistor (not shown) having a large channel width. The pulse width of the input signal is removed by the propagation delay time of the MOS transistor.

For this reason, when a pulse signal as shown in FIG. 5A having a width smaller than the propagation delay time of the four inverters is input, the conventional noise characteristic enhancement circuit removes the pulse signal as shown in FIG. 5B. And an appropriate output signal is generated on the output line (23). Conversely, when a pulse signal as shown in FIG. 6A having a width greater than the delay time of the four inverters is input to the input line (21), the conventional noise characteristic enhancement circuit uses the input pulse signal. The pulse width is removed by the propagation delay time of the four inverters to generate a pulse signal as shown in FIG. 6B on the output line (23).

[0009]

As described above, the conventional noise characteristic enhancement circuit of a semiconductor device can remove a noise signal having a small pulse width, but can reduce the effective input signal pulse width or reduce the effective pulse width. There is a problem that removing the unnecessary input signal causes the semiconductor device to malfunction.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device noise characteristic enhancement circuit capable of removing a noise signal, compensating for the width of an effective input signal having a small width, and operating the semiconductor device accurately. is there.

[0011]

In order to achieve the above object, a noise characteristic enhancement circuit of a semiconductor device according to the present invention comprises a semiconductor device having an input line for externally inputting an input signal having a first logic pulse. In the device, the first and second
A supply voltage source and a C-
A MOS inverter; and latch means connected to an output terminal of the C-MOS inverter for latching an output signal of the C-MOS inverter. Buffer means for filtering and buffering an input signal having a pulse width smaller than the sum of the propagation delay times, and a delay line connected to an output terminal of the buffer means for delaying an output signal of the buffer means for a predetermined time; And when the input signal changes from the first logic to the second logic, until the signal buffered by the first logic by the C-MOS inverter of the buffer means is output from the delay line, the C-MOS In order to prevent the logic of the output signal of the inverter from changing, it is connected between the output terminal of the delay line and the buffer means. In semiconductors noise characteristics enhanced circuit having a feedback loop means.

[0012]

With the above arrangement, the noise characteristic enhancement circuit of the semiconductor device according to the present invention comprises the C-MOS inverter and the latch means, and performs the filtering and buffering function even if the pulse width of the output signal of the buffer means changes. By using the delay line and the feedback loop means, it is possible to compensate such that the pulse width of the input signal having a small width distinguished from the noise component is equal to or larger than a predetermined width. Further, the noise characteristic enhancement circuit of the semiconductor device of the present invention has an advantage that the semiconductor device can be operated accurately and the reliability of the semiconductor device can be improved.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 7 shows an input line (30).
The first P-MO that inputs an input signal to its own gate side from
4 illustrates a circuit for enhancing noise characteristics of a semiconductor device according to a first embodiment of the present invention, including an S transistor (M1) and a first N-MOS transistor (M2). The drains of the first P-MOS and N-MOS transistors (M1, M2) are commonly connected to a first node (31), and one C-
Forming a MOS inverter; The first P-MOS transistor M1 is turned on when a low logic input signal is applied from the input line 30. Further, the first P-MOS transistor (M1) receives a first supply voltage (Vcc) applied to its own source side via a second N-MOS transistor (M3), which is a second control switch means, to the first P-MOS transistor (M1). The signal is transmitted to the node (31) to invert the low logic input signal so as to become a high logic input signal. On the other hand, the first N-MOS transistor M2 is turned on when an input signal having a high logic pulse is applied from the input line 30. Then, the first N-MOS transistor (M
2) transmitting the second supply voltage (Vss) applied from the second supply voltage source (Vss) to its own source side to the first node (31), and transmitting the high logic pulse to the low logic; Invert so that it becomes a pulse. Further, the C-MOS
The inverter is the first P-MOS transistor (M1)
And a low logic noise component having a width smaller than the propagation delay time of the first N-MOS transistor (M2).

Further, the noise characteristic enhancement circuit of the semiconductor device comprises a second node (32) and the first node (31).
And a second supply voltage (Vs) from a second supply voltage source (Vss) to the first node (31) according to an output signal of the inverter (G1).
s), and a second N-MOS transistor (M4) for supplying s). The second N-MOS transistor (M4) is turned on when the output signal of the inverter (G1) has a high logic, and the second supply voltage source (Vs) is turned on.
s) to supply the second supply voltage (Vss) to the first node (31). Due to the second supply voltage (Vss) supplied by the second N-MOS transistor (M4), a pulse generated from the first node (31) is turned on when the first N-MOS transistor (M2) is turned on. The logic low is maintained until the first and second P-MOS transistors M1 and M3 are all turned on. As a result, the second N-MOS transistor (M4) and the inverter (G1) function as a latch circuit. Further, the inverter (G
1) removes a noise component having a width smaller than its own propagation delay time from the output signal of the C-MOS inverter. The second N-MOS transistor (M4) performs a first control to generate a high-logic logic signal at the first node (31) when all of the first and second P-MOS transistors (M1, M3) are turned on. And has an extremely small channel width as compared with the first and second P-MOS transistors (M1, M3).

The noise characteristic enhancement circuit of the semiconductor device includes three inverters (G2 to G4) connected in series between the output line (33) and the second node (32). The three inverters (G2 to G4) are connected to the inverter (G) supplied from the second node (32).
It functions as a delay line that delays the output signal of 1) for a period corresponding to the sum of its own propagation delay time. The signal delayed by the delay line is applied to the output line (3
It is sent through 3). Further, the delayed signal output from the delay line is a signal corresponding to a sum of the propagation delay time of the delay line, the propagation delay time of the inverter (G1), and the propagation delay time of the C-MOS inverter. The signal has a delayed and inverted waveform, or the signal has a propagation delay time of the delay line, a propagation delay time of the inverter (G1) and a propagation delay time of the C-MOS inverter. The input signal has a delayed and compensated inverted waveform.

The first P-MOS transistor (M1)
Is turned on by a low logic input signal, the second P-MOS transistor (M3) operates until the delayed signal from the delay line changes to low logic. The width of the input signal is compensated based on blocking the first supply voltage (Vcc) supplied to the input signal.

If the input signal supplied to the input line (30) has a high logic pulse having a width smaller than the delay time of the delay line as shown in FIG. The generated signal has a waveform similar to that of FIG. 8B, and the delayed signal on the output line (33) has a waveform as shown in FIG. 8C. Alternatively, when the input signal supplied to the input line (30) has a high logic pulse having a width greater than the delay time of the delay line as shown in FIG. 9A, the first node (3
The signal generated in 1) has the same waveform as in FIG. 9B, and the delayed signal on the output line (33) has the waveform as in FIG. 9C.

FIG. 10 shows a first P-MOS transistor (M1) and a first N-MOS transistor (M) for inputting an input signal from the input line (30) to its own gate.
2 shows a circuit for enhancing the noise characteristics of a semiconductor device according to a second embodiment of the present invention, which includes 2). The drains of the first P-MOS transistor and the first N-MOS transistor (M1, M2) are commonly connected to a first node (31) to form one C-MOS inverter. The first P-MOS
When an input signal having a low logic pulse is applied from the input line (30) to the transistor (M1),
Turned on. Also, the first P-MOS transistor (M1) transmits the first supply voltage (Vcc) from the first supply voltage source (Vcc) to the first node (31) side to change the low logic pulse to a high logic. Invert so that the pulse becomes On the other hand, the first N-MOS transistor M2 is turned on when an input signal having a high logic pulse is applied from the input line 30. And the first N-MOS transistor (M2)
Converts the second supply voltage (Vss) applied from the second supply voltage source (Vss) to its own source side via the second N-MOS transistor (M5) as the second control switch means into the first node ( 31) to invert the high logic input signal to low logic. The C-MOS inverter may include a low logic noise component having a width smaller than a propagation delay time of the first P-MOS transistor M1 and the first N-MOS transistor M1.
The noise component of high logic having a width smaller than the propagation delay time of 2) is removed.

As shown in FIG. 10, the noise characteristic enhancement circuit of the semiconductor device includes an inverter (G) connected between a second node (32) and the first node (31).
1) and a second P-MOS transistor (M6) for supplying a first supply voltage (Vcc) from a first supply voltage source (Vcc) to the first node (31) according to an output signal of the inverter (G1). Prepare additionally. The second P-MO
The S-transistor (M6) is turned on when the output signal of the inverter (G1) has low logic, and supplies a first supply voltage from a first supply voltage source (Vcc) to the first node (31). The pulse generated at the first node (31) by the first supply voltage supplied by the second P-MOS transistor (M6) is the first P-M
When the OS transistor (M1) is turned off, the first and second N-MOS transistors (M2, M5)
Maintain high logic until all are turned on. As a result, the second P-MOS transistor (M6) and the inverter (G1) function as a latch circuit. Further, the inverter (G1) can remove a noise component having a width smaller than its own propagation delay time from the output signal of the C-MOS inverter. The second
The P-MOS transistor (M6) includes the first and second transistors.
When the N-MOS transistors (M2, M5) are all turned on, the first and second N-MOS transistors function as first control switch means for generating a low logic signal at the first node (31). Transistor (M
2, M5) has a very small channel width.

The noise characteristic enhancement circuit of the semiconductor device according to the present invention includes an output line (33) and the second node (3).
2) three inverters (G2 to G4) connected in series.

The three inverters (G2 to G4) delay the output signal of the inverter (G1) supplied from the second node (32) for a period corresponding to the sum of their own propagation delay times. Performs the function of a delay line. The signal delayed by the delay line is applied to the output line (3
It is sent through 3). Further, the delayed signal output from the delay line is used for a period corresponding to the sum of the propagation delay time of the delay line, the propagation delay time of the inverter (G1), and the propagation delay time of the C-MOS inverter. The input signal has a delayed and inverted waveform, or a period corresponding to the sum of the propagation delay time of the delay line, the propagation delay time of the inverter (G1), and the propagation delay time of the C-MOS inverter. The input signal has a waveform inverted by delay and width compensation. When the first N-MOS transistor M2 is turned on by a high logic input signal, the second N-MOS transistor M2 is turned on.
The S-transistor (M5) switches the first N-th until the delayed signal from the delay line changes to high logic.
The width of the input signal is compensated based on blocking the second supply voltage (Vss) supplied to the MOS transistor (M2).

In fact, when the input signal supplied to the input line (30) has a low logic pulse having a width smaller than the delay time of the delay line as shown in FIG. The generated signal has a waveform similar to that of FIG. 11B, and the delayed signal on the output line (33) has a waveform as shown in FIG. 11C. Alternatively, when the input signal supplied to the input line (30) has a low logic pulse having a width greater than the delay time of the delay line as shown in FIG. 12A, the signal is generated at the first node (31). 12B, and the delayed signal on the output line (33) has a waveform as in FIG. 12C.

FIG. 13 shows a noise characteristic enhancement circuit of a semiconductor device according to a third embodiment of the present invention. The noise characteristic enhancement circuit shown in FIG. 13 is the second of the circuits shown in FIG.
An inverter (G5) connected between the first and second nodes (31, 32) is provided instead of the N-MOS transistor (M4).
And a third N-MOS transistor (M7) connected between the source of (2) and the second supply voltage source (Vss). The noise characteristic enhancement circuit shown in FIG. 13 compensates for a small pulse width of an input signal having a low logic pulse and a high logic pulse, and removes noise to reduce the noise. It is a technology that merges.

The circuit shown in FIG. 13 will be briefly described. The first P-MOS transistor (M1) and the first
The N-MOS transistor (M2) forms a C-MOS inverter to invert and buffer the input signal from the input line (30), and to remove a noise component smaller than its own propagation delay time included in the input signal. be able to.

The first and second nodes (31), (3)
Two inverters (G1 and G5) connected to form a circulating circuit between 2) provide the first and second PMs with the logic of the input signal inverted by the C-MOS inverter.
The latch function is performed until the OS transistors M1 and M3 are all turned on or the first and third N-MOS transistors M2 and M7 are all turned on.

Three inverters (G2) connected in series between the second node (32) and the output line (33)
G4) delays the output signal of the latch circuit by its own propagation delay time to compensate for the pulse width of the input signal having a small width.

The second P-MOS transistor (M3), which is a first control switch, is connected to the first P-MOS transistor when a low logic delayed signal is applied from the output line (33). First on (M1) side
A first supply voltage (Vcc) from a supply voltage source (Vcc) is transmitted to change the output signal of the latch circuit to a high logic.

Separately, the third N-MOS transistor (M7), which is the second control switch means, receives the first N-MOS transistor when a high logic delayed signal is applied from the output line (33). MOS transistor (M2)
The second supply voltage (Vs) from the second supply voltage source (Vss)
ss) to change the output signal of the latch circuit to low logic.

[0029]

As described above, the noise characteristic enhancement circuit of the semiconductor device according to the present invention comprises the C-MOS inverter and the latch means and performs the filtering and buffering functions. Even so, there is an advantage that it is possible to compensate using the delay line and the feedback loop means so that the pulse width of the input signal having a small width distinguished from the noise component is equal to or larger than a certain width. For this reason, the noise characteristic enhancement circuit of the semiconductor device of the present invention has a great industrial advantage that the semiconductor device can be operated accurately and the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining one example of a conventional noise characteristic enhancement circuit of a semiconductor device.

FIGS. 2A to 2C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 1 when a narrow-width pulse signal is input;

3A to 3C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 1 when a pulse signal having a large width is input.

FIG. 4 is a circuit diagram for explaining a different example of the noise characteristic enhancement circuit of the conventional semiconductor device.

FIGS. 5A and 5B are input and output waveform diagrams of the circuit shown in FIG. 4 when a narrow width pulse signal is input;

6A and 6B are input and output waveform diagrams of the circuit shown in FIG. 4 when a pulse signal having a large width is input.

FIG. 7 is a circuit diagram showing a noise characteristic enhancement circuit of the semiconductor device according to the first embodiment of the present invention.

8A to 8C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 7 when a pulse signal having a narrow width is applied.

9A to 9C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 7 when a pulse signal having a large width is input.

FIG. 10 is a circuit diagram for explaining a noise characteristic enhancement circuit of a semiconductor device according to a second embodiment of the present invention.

11A to 11C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 10 when a pulse signal having a narrow width is applied.

12A to 12C are operation waveform diagrams corresponding to respective portions of the circuit shown in FIG. 10 when a pulse signal having a large width is input.

FIG. 13 is a circuit diagram illustrating a noise characteristic enhancement circuit of a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

10, 12, 14, 16 inverter 11 input lines 13 output lines 18 NAND circuit 20, 22, 24, 26 inverter 21 input line 23 the output line 30 input lines 31, 32 node 33 output lines _{M 1, M 3, M 6} P -MOS transistor _{M 2, M 4, M 5} , M 7 N-MOS transistors _{G 1, G 2, G 3} , G 4, G 5 inverter Vcc first supply voltage Vss second supply voltage

Claims (11)

(57) [Claims] 1. A semiconductor device having an input line for inputting an input signal having a first logic pulse from outside, comprising: a first and a second supply voltage source; and a C-terminal connected between the input lines. A MOS inverter; and latch means connected to an output terminal of the C-MOS inverter for latching an output signal of the C-MOS inverter. Buffer means for filtering and buffering an input signal having a pulse width smaller than the sum of the propagation delay times; and a delay line connected to an output terminal of the buffer means for delaying an output signal of the buffer means for a predetermined time. When the input signal changes from the first logic to the second logic, the C-MOS inverter of the buffering means changes the first logic to the first logic. A feedback loop connected between the output terminal of the delay line and the buffer means so that the logic of the output signal of the C-MOS inverter does not change until the buffered signal is output from the delay line. Means for enhancing noise characteristics. 2. The latch circuit according to claim 1, wherein said latch means comprises two inverters to form a circulating circuit between said C-MOS inverter and said delay line.
The described noise characteristic enhancement circuit. 3. The first control switch means for selectively connecting the C-MOS inverter to a first supply voltage source according to an output signal of the delay line, and the feedback loop means according to an output signal of the delay line. And a second control switch, which is driven complementarily to the first control switch and selectively connects the C-MOS inverter to a second supply voltage source. 2. The noise characteristic enhancement circuit according to 2. 4. A C-MOS inverter comprising: a first P-MOS transistor connected between said input line, said first control switch means and said latch means; and said input line and said second control switch. 4. The noise characteristic enhancing circuit according to claim 3, further comprising a first N-MOS transistor connected between the first and second latch means. 5. The first control switch means includes a second P-MOS transistor for connecting the first P-MOS transistor to the first supply voltage source when an output signal of the delay line has low logic. The second control switch means connects the first N-MOS transistor to the second supply voltage source when an output signal of the delay line has high logic.
5. The device according to claim 4, further comprising a MOS transistor.
The described noise characteristic enhancement circuit. 6. The latch means selects a logic signal having a second logic at an input terminal of the inverter according to an inverter connected between the C-MOS inverter and the delay line, and an output signal of the inverter. 2. The noise characteristic enhancing circuit according to claim 1, further comprising first control switch means for supplying the noise characteristic. 7. The feedback loop means controls the C-MOS inverter according to an output signal of the delay line.
A second control switch means selectively connected to a supply voltage source or an output signal of the delay line, the C-MOS
7. The noise characteristic enhancement circuit according to claim 6, further comprising a second control switch for selectively connecting an inverter to the second supply voltage source. 8. The noise characteristic enhancement circuit according to claim 7, wherein the first logic has a low state, and the second logic has a high state. 9. The circuit according to claim 8, wherein said first supply voltage source generates a first supply voltage (Vcc). 10. The noise characteristic enhancement circuit according to claim 7, wherein the first logic has a high state, and the second logic has a low state. 11. The circuit according to claim 10, wherein the second supply voltage source generates a second supply voltage (Vss).