Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP2859155B2 - Evaluation equipment for semiconductor devices - Google Patents
[go: Go Back, main page]

JP2859155B2 - Evaluation equipment for semiconductor devices - Google Patents

Evaluation equipment for semiconductor devices

Info

Publication number
JP2859155B2
JP2859155B2 JP7032230A JP3223095A JP2859155B2 JP 2859155 B2 JP2859155 B2 JP 2859155B2 JP 7032230 A JP7032230 A JP 7032230A JP 3223095 A JP3223095 A JP 3223095A JP 2859155 B2 JP2859155 B2 JP 2859155B2
Authority
JP
Japan
Prior art keywords
laser beam
semiconductor device
laser
dimensional
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7032230A
Other languages
Japanese (ja)
Other versions
JPH08227922A (en
Inventor
和久 永屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP7032230A priority Critical patent/JP2859155B2/en
Publication of JPH08227922A publication Critical patent/JPH08227922A/en
Application granted granted Critical
Publication of JP2859155B2 publication Critical patent/JP2859155B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Length Measuring Devices By Optical Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Lasers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の評価装置に
関し、特にレーザ光を用い非破壊的に評価対象の半導体
装置の断面形状を評価する半導体装置の評価装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device evaluation apparatus, and more particularly to a semiconductor device evaluation apparatus for non-destructively evaluating a cross-sectional shape of a semiconductor device to be evaluated using a laser beam.

【0002】[0002]

【従来の技術】半導体装置においては、MOSトランジ
スタ等半導体素子を構成するゲートやソースなどの電極
やこれら電極のリード線あるいは半導体素子間配線の断
面形状の正確さは、性能および信頼性を左右する重要な
必要条件である。例えば、矩形であるべきMOSトラン
ジスタのゲート電極の断面形状が台形に形成されていた
り、その逆に逆台形に形成されると、性能の劣化やばら
つきを生ずる。また、配線が逆台形に形成されると、ス
トレスマイグレーションやエレクトロマイグレーョンを
生じ易くなるという信頼性上の問題に発展する。
2. Description of the Related Art In a semiconductor device, the accuracy of the cross-sectional shape of electrodes such as gates and sources constituting semiconductor elements such as MOS transistors, the lead wires of these electrodes, or the wirings between semiconductor elements influences the performance and reliability. This is an important requirement. For example, if the gate electrode of a MOS transistor, which should be rectangular, is formed in a trapezoidal cross section, or conversely, if the gate electrode is formed in an inverted trapezoidal shape, performance degradation or variation occurs. In addition, if the wiring is formed in an inverted trapezoidal shape, it causes a problem of reliability that stress migration and electromigration are likely to occur.

【0003】従来、上述したような電極や配線等の断面
形状の評価方法としては、評価対象半導体装置の対象部
分を所定の寸法に切断して評価試料として抽出し、この
評価試料を第1の評価装置である走査型電子顕微鏡を用
いて直接的に観察評価する第1の評価方法が主流であ
る。
Conventionally, as a method for evaluating the cross-sectional shape of an electrode, a wiring, or the like as described above, a target portion of a semiconductor device to be evaluated is cut into a predetermined size, extracted as an evaluation sample, and the evaluation sample is subjected to a first method. A first evaluation method for directly observing and evaluating using a scanning electron microscope as an evaluation device is mainstream.

【0004】従来の第1の評価方法を工程順に示す図3
を参照して説明すると、まず、(A)に示すSiウェハ
等の半導体基板上に形成されたLSIなどの半導体装置
を、(B)に示すように半導体基板ごと切断し切断面を
研磨し、(C)に示すように走査型電子顕微鏡の試料室
に収容可能な寸法の試料に加工形成する。次に、この評
価試料を走査型電子顕微鏡の試料室内に収容し、上述の
研磨面を(D)に示す電子顕微鏡画像として直接的に観
察評価する。評価対象断面を電子顕微鏡画像としてとら
えるため、電子が帯電しやすいようにこの断面に金をス
パッタすることもしばしば必要である。
FIG. 3 shows a first conventional evaluation method in the order of steps.
First, a semiconductor device such as an LSI formed on a semiconductor substrate such as a Si wafer shown in (A) is cut together with the semiconductor substrate as shown in (B) and the cut surface is polished as shown in FIG. As shown in (C), the sample is formed into a sample having a size that can be accommodated in the sample chamber of the scanning electron microscope. Next, this evaluation sample is accommodated in a sample room of a scanning electron microscope, and the above-mentioned polished surface is directly observed and evaluated as an electron microscope image shown in (D). In order to capture a cross section for evaluation as an electron microscope image, it is often necessary to sputter gold on this cross section so that electrons are easily charged.

【0005】この従来の第1の評価装置では、観察評価
するため、評価対象の半導体ウェハ等から所望の寸法の
評価試料を加工形成する必要があり、多大な工数と時
間、典型的には約3時間を要する。
In this conventional first evaluation apparatus, it is necessary to process and form an evaluation sample of a desired size from a semiconductor wafer or the like to be evaluated in order to perform observation and evaluation. It takes 3 hours.

【0006】この欠点を解決する特開平4−17614
3号公報記載のウェハパターン形状検査装置である従来
の第2の評価装置は、レーザ光源と、レーザビーム径を
ウェハの外形をカバーするよう拡大するビームエキスパ
ンダと、評価対象ウェハに拡大レーザビームを導く光学
系と、上記評価対象ウェハに生じた正反射光とこのウェ
ハ上の半導体装置のパターンによる回折光を集光する集
光レンズと、この集光した反射・回折レーザビームパタ
ーン(集光パターン)を受光する2次元受光素子と、基
準半導体の集光パターン(基準パターン)を記憶する記
憶装置と、上記集光パターンと基準パターンとを比較し
てこの集光パターン対応の半導体装置がどの基準半導体
に対応するかを判定する判定装置とを備え、上記反射光
・回折光が半導体装置固有の立体パターンに依存するこ
とを利用して非破壊的にウェハ全体の立体パターンを含
む形状評価を行うというものである。
[0006] Japanese Patent Laid-Open No. 4-17614 for solving this drawback
The second conventional evaluation device, which is a wafer pattern shape inspection device described in Japanese Patent Publication No. 3 (1993) -279, includes a laser light source, a beam expander for expanding a laser beam diameter to cover the outer shape of the wafer, and an expanded laser beam for a wafer to be evaluated. , A condenser lens for collecting the specularly reflected light generated on the wafer to be evaluated and the diffracted light by the pattern of the semiconductor device on the wafer, and a condensed reflected / diffracted laser beam pattern (condensed light beam). Pattern), a storage device for storing the condensing pattern (reference pattern) of the reference semiconductor, and comparing the condensing pattern with the reference pattern to determine which of the semiconductor devices corresponding to the condensing pattern A judgment device for judging whether or not the reflected light / diffraction light corresponds to a reference semiconductor; Manner is that performs shape evaluation including the whole of the three-dimensional pattern wafer.

【0007】[0007]

【発明が解決しようとする課題】上述した従来の第1の
半導体装置の評価装置は、電子顕微鏡画像として直接的
に観察評価するため、評価対象の半導体ウェハ等を破壊
して所望の寸法の評価試料を加工形成する必要があり、
多大な工数と時間を要するとともに、半導体装置生産ラ
インの歩留を低下させるという欠点があった。
Since the above-mentioned first conventional semiconductor device evaluation apparatus directly observes and evaluates as an electron microscope image, it destroys a semiconductor wafer or the like to be evaluated and evaluates a desired dimension. It is necessary to process the sample,
It requires a lot of man-hours and time, and also has the disadvantage of lowering the yield of the semiconductor device production line.

【0008】この欠点を解決する従来の第2の半導体装
置の評価装置は、ウェハ全体の半導体装置パターンにつ
いての形状評価は可能であるものの、基準半導体の種類
に限界があるため、ウェハの特定領域における半導体装
置単体の実際の断面形状の特定までは困難であるという
欠点があった。
The second conventional semiconductor device evaluation apparatus which solves this drawback can evaluate the shape of the semiconductor device pattern of the entire wafer, but has a limit in the type of the reference semiconductor. However, it is difficult to specify the actual cross-sectional shape of the semiconductor device alone.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置の評
価装置は、3次元形状を有する半導体装置を形成した半
導体基板の一主面に対し予め定めた角度でレーザビーム
を照射するレーザ光源を有しこのレーザビームの反射光
を検出し信号処理して前記半導体装置の断面方向の形状
を測定する半導体装置の評価装置において、 前記一主面
に投影した前記レーザビームの照射方向に対し垂直方向
に走査するレーザ走査手段と、2次元に配列した光電変
換素子から成り前記レーザ光源と予め定めた位置関係で
機械的に固定され前記一主面からの反射光を受光する2
次元光センサと、記2次元光センサに入射した前記反
射光のうちの最大の信号レベルに対応する一次反射光を
受光した前記光電変換素子の電荷量対応の画素信号を抽
出する信号処理手段と、前記画素信号を記憶する記憶回
路と、前記記憶回路から読出した前記画素信号と前記レ
ーザビームの走査情報とからこの画素信号を画像に変換
する画像出力手段とを備えて構成されている。
According to the present invention, there is provided an apparatus for evaluating a semiconductor device, comprising: a laser light source for irradiating a laser beam at a predetermined angle to one principal surface of a semiconductor substrate on which a semiconductor device having a three-dimensional shape is formed. Reflected light of this laser beam
And process the signals to process the shape of the semiconductor device in the cross-sectional direction.
In the evaluation apparatus of a semiconductor device to be measured, said one main surface
Perpendicular to the irradiation direction of the laser beam projected on
A laser scanning means for scanning the laser light source, and two-dimensionally arranged photoelectric conversion elements, and in a predetermined positional relationship with the laser light source.
2 that is mechanically fixed and receives light reflected from the one main surface
Signal processing means for extracting the dimension light sensor, the maximum charge amount corresponding pixel signals of the photoelectric conversion element receives the primary reflected light corresponding to the signal level of one of the reflected light incident on the front SL two-dimensional photosensor And a storage circuit for storing the pixel signal, and image output means for converting the pixel signal into an image based on the pixel signal read from the storage circuit and the scanning information of the laser beam.

【0010】[0010]

【実施例】次に、本発明の実施例を一部をブロックで示
す図1を参照すると、この図に示す本実施例の半導体装
置の評価装置は、ウェハ9にレーザビームBを照射する
He−Neレーザなどのレーザ光源1と、レーザ光源1
と一体化して配置されウェハ9からの反射光Rを受光す
る2次元CCDセンサ2と、レーザビームBを入射方向
に対し垂直の方向に移動(走査)可能なレーザ走査部3
と、CCDセンサ2の出力信号Cを処理し反射光データ
Dを出力する信号処理部4と、反射光データDを記憶す
る記憶部5と、記憶部5の読出データEを画像に形成し
てディスプレイに表示する画像出力部6とを備える。
FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a semiconductor device evaluation apparatus according to this embodiment shown in FIG. A laser light source 1 such as a Ne laser, and a laser light source 1
A two-dimensional CCD sensor 2 which is arranged integrally with the laser beam receiving means 9 for receiving reflected light R from the wafer 9 and a laser scanning unit 3 which can move (scan) a laser beam B in a direction perpendicular to the incident direction.
A signal processing unit 4 for processing an output signal C of the CCD sensor 2 and outputting reflected light data D; a storage unit 5 for storing the reflected light data D; and reading data E from the storage unit 5 to form an image. And an image output unit 6 for displaying on a display.

【0011】次に、図1を参照して本実施例の動作につ
いて説明すると、まず、レーザ光源1は、ビーム径0.
1μm程度のビームBをウェハ9の表面側斜め上方から
照射する。ウェハ9の細部とビームB,反射光Rとの関
係を示す図2(A)を併せて参照すると、ウェハ9に入
射したビームBは、半導体装置の素子10の側面で反射
して反射光Rとなり、2次元CCDセンサ2に入射し、
対応の信号電荷を発生させる。一般的なこの種の2次元
CCDセンサの1つの光電素子すなわち1画素の寸法が
3μm角程度であるから、ビーム径0.1μmの入射光
は1画素分の情報として認識される。ただし、反射光R
には、ウェハ表面で反射される一次反射光と半導体装置
表面下層部分における絶縁膜等の境界面などで反射され
るn次反射光(nは2,3,4…)が含まれる。一次反
射光とn次反射光とを区別する物理的特徴点はエネルギ
ーであり、一次反射光が最も大きい。したがって、2次
元CCDセンサ2へ入射する反射光Rの中で最もエネル
ギーの大きいもの、すなわち2次元CCDセンサ2の各
光電素子のうち最も信号電荷量の大きいものを一次反射
光Rの受光素子と見なすことができる。前述のように2
次元CCDセンサ2は、レーザ光源1と機械的に一体化
して配置されており、一次反射光Rが、どの光電素子
(以下画素)に戻ってくるかによって、ウェハ9の表面
の素子10の断面形状を推定できる。すなわち図2
(A),(B)に示すように、素子10に入射したビー
ムBは素子10の断面形状によって反射角度が変わる。
例えば、(A)に示すように素子10の断面11が正確
な矩形すなわちウェハ9の表面に対し垂直である場合は
入射ビームBに対し角度(以下反射角度)0度で反射
し、(B)に示すように断面11が台形である場合は入
射ビームBに対し対応の角度θ度で反射する。2次元C
CDセンサ2のこの反射光Rの入射画素位置からその反
射角度、つまり素子10の断面形状を推定できるという
原理である。
Next, the operation of the present embodiment will be described with reference to FIG.
A beam B of about 1 μm is irradiated from obliquely above the surface of the wafer 9. Referring also to FIG. 2A showing the relationship between the details of the wafer 9 and the beam B and the reflected light R, the beam B incident on the wafer 9 is reflected by the side surface of the element 10 of the semiconductor device and reflected light R And enters the two-dimensional CCD sensor 2,
A corresponding signal charge is generated. Since the size of one photoelectric element, that is, one pixel of a general two-dimensional CCD sensor of this type is about 3 μm square, incident light having a beam diameter of 0.1 μm is recognized as information for one pixel. However, the reflected light R
Include primary reflected light reflected on the wafer surface and n-order reflected light (n is 2, 3, 4,...) Reflected on a boundary surface such as an insulating film in the lower part of the semiconductor device surface. The physical feature that distinguishes the primary reflected light from the n-order reflected light is energy, and the primary reflected light is the largest. Therefore, of the reflected light R incident on the two-dimensional CCD sensor 2, the one having the largest energy, that is, the one having the largest signal charge amount among the photoelectric elements of the two-dimensional CCD sensor 2 is regarded as the light receiving element of the primary reflected light R. Can be considered. 2 as described above
The two-dimensional CCD sensor 2 is mechanically integrated with the laser light source 1, and depends on which photoelectric element (hereinafter, pixel) the primary reflected light R returns to the cross section of the element 10 on the surface of the wafer 9. Shape can be estimated. That is, FIG.
As shown in (A) and (B), the reflection angle of the beam B incident on the element 10 changes depending on the cross-sectional shape of the element 10.
For example, as shown in (A), when the cross section 11 of the element 10 is an accurate rectangle, that is, perpendicular to the surface of the wafer 9, the element 10 reflects the incident beam B at an angle (hereinafter referred to as a reflection angle) of 0 degree, When the cross section 11 has a trapezoidal shape as shown in FIG. 2D C
The principle is that the reflection angle, that is, the cross-sectional shape of the element 10 can be estimated from the position of the incident pixel of the reflected light R of the CD sensor 2.

【0012】レーザ光源1は、レーザ走査部3によりビ
ームBに対し垂直方向に移動することにより走査可能な
構造である。評価時には、例えば、0.1μmのピッチ
で移動しながら反射角度を測定し、その反射角度データ
を記憶装置5に記憶し、それらの記憶された反射角度デ
ータを1つの画像データとして合成することで素子10
の立体的な構造が推定でき、画像出力部6により画像イ
メージとして表示することで、素子10の形状を認識で
きる。
The laser light source 1 has a structure that can be scanned by moving in a direction perpendicular to the beam B by the laser scanning unit 3. At the time of evaluation, for example, the reflection angle is measured while moving at a pitch of 0.1 μm, the reflection angle data is stored in the storage device 5, and the stored reflection angle data is synthesized as one image data. Element 10
Can be estimated, and the image output unit 6 displays the image as an image, whereby the shape of the element 10 can be recognized.

【0013】画像出力制御部6の具体的な出力画像の一
例を示す図2(C)を参照すると、図2(B)に示す評
価対象の素子10の断面11の区間Xの範囲がディスプ
レイ表示画面13の画像12のように表示される。これ
らの評価所要時間は約10分で十分である。
Referring to FIG. 2C, which shows an example of a specific output image of the image output control unit 6, the range of the section X of the cross section 11 of the element 10 to be evaluated shown in FIG. It is displayed as an image 12 on the screen 13. A time required for these evaluations of about 10 minutes is sufficient.

【0014】このように、本実施例では、素子10の片
側部分の形状のみを評価のため表示するが、一般に半導
体装置における種々の素子形状は左右対象であるので、
上述のように片側部分のみの表示で充分である。勿論、
素子の両側の形状を正確に表示評価することも可能であ
り、その場合、片側部分の表示の終了後にビームの入射
方向をもう片側の斜め上方に変更して再度実行すればよ
い。
As described above, in the present embodiment, only the shape of one side of the element 10 is displayed for evaluation. However, since various element shapes in a semiconductor device are generally symmetrical,
As described above, it is sufficient to display only one side portion. Of course,
It is also possible to accurately evaluate the display of the shape on both sides of the element. In this case, after the display on one side is completed, the incident direction of the beam may be changed to the obliquely upper side on the other side, and the processing may be executed again.

【0015】[0015]

【発明の効果】以上説明したように、本発明の半導体装
置の評価装置は、ウエハ表面に投影したレーザビームの
照射方向に対し垂直方向に走査するレーザ走査手段と、
上記レーザ光源と予め定めた位置関係で機械的に固定さ
上記表面からの反射光を受光する2次元光センサと
素信号を抽出する信号処理手段と、この画素信号を記
憶する記憶回路と、この記憶回路から読出した上記画素
信号と走査情報とからこの画素信号を画像に変換する画
像出力手段とを備え、ウェハに形成した半導体装置の素
子の断面形状を極めて簡単に評価できるため、従来約3
時間の時間と手間を要していたものが約10分と大幅に
短縮できるという効果がある。
As described above, the apparatus for evaluating a semiconductor device according to the present invention uses the laser beam projected onto the wafer surface.
Laser scanning means for scanning in a direction perpendicular to the irradiation direction,
Mechanically fixed in a predetermined positional relationship with the laser light source
And two-dimensional optical sensor for receiving the reflected light from the surface Re,
Comprising a signal processing means for extracting a picture element signal, a memory circuit for storing the pixel signals, and an image output means for converting from from the storage circuit and read out the pixel signal and the scanning information the pixel signal to the image, Conventionally, since the cross-sectional shape of the element of the semiconductor device formed on the wafer can be evaluated very easily.
There is an effect that the time and labor required can be greatly reduced to about 10 minutes.

【0016】しかも、半導体装置そのものの評価は非破
壊で可能であるので、歩留低下要因が除去できるという
効果がある。
In addition, since the evaluation of the semiconductor device itself can be performed in a non-destructive manner, there is an effect that the factor of lowering the yield can be eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の評価装置の一実施例を示
すブロック図である。
FIG. 1 is a block diagram showing one embodiment of a semiconductor device evaluation apparatus of the present invention.

【図2】本実施例の半導体装置の評価装置における評価
対象のウェハの細部とレーザビームおよび反射光との関
係および表示画像の一例をそれぞれ示す説明図である。
FIG. 2 is an explanatory diagram illustrating a relationship between details of a wafer to be evaluated, a laser beam, and reflected light, and an example of a display image in the semiconductor device evaluation apparatus of the present embodiment.

【図3】従来の半導体装置の評価装置の評価方法の工程
の一例を示す工程図である。
FIG. 3 is a process chart showing an example of a process of an evaluation method of a conventional semiconductor device evaluation device.

【符号の説明】[Explanation of symbols]

1 レーザ光源 2 2次元CCDセンサ 3 レーザ走査部 4 信号処理部 5 記憶部 6 画像出力部 9 ウェハ 10 素子 11 断面 12 画像 13 表示画面 Reference Signs List 1 laser light source 2 two-dimensional CCD sensor 3 laser scanning unit 4 signal processing unit 5 storage unit 6 image output unit 9 wafer 10 element 11 cross section 12 image 13 display screen

フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/66 G01B 11/24 H01S 3/00Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/66 G01B 11/24 H01S 3/00

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 3次元形状を有する半導体装置を形成し
た半導体基板の一主面に対し予め定めた角度でレーザビ
ームを照射するレーザ光源を有しこのレーザビームの反
射光を検出し信号処理して前記半導体装置の断面方向の
形状を測定する半導体装置の評価装置において、 前記一主面に投影した前記レーザビームの照射方向に対
し垂直方向に走査するレーザ走査手段と、 2次元に配列した光電変換素子から成り前記レーザ光源
と予め定めた位置関係で機械的に固定され前記一主面か
らの反射光を受光する2次元光センサと、 記2次元光センサに入射した前記反射光のうちの最大
の信号レベルに対応する一次反射光を受光した前記光電
変換素子の電荷量対応の画素信号を抽出する信号処理手
段と、 前記画素信号を記憶する記憶回路と、 前記記憶回路から読出した前記画素信号と前記レーザビ
ームの走査情報とからこの画素信号を画像に変換する画
像出力手段とを備えることを特徴とする半導体装置の評
価装置。
1. A laser light source for irradiating a laser beam at a predetermined angle to one principal surface of a semiconductor substrate on which a semiconductor device having a three-dimensional shape is formed, and having a laser beam reflected therefrom.
Detects the emitted light, processes the signal, and detects
In a semiconductor device evaluation device for measuring a shape, a laser beam projected onto the one main surface may be irradiated in a direction in which the laser beam is projected.
Laser scanning means for scanning in the vertical direction; and two-dimensional light, which is composed of two-dimensionally arranged photoelectric conversion elements and is mechanically fixed to the laser light source in a predetermined positional relationship and receives light reflected from the one main surface. signal processing means for extracting sensor and the maximum charge amount corresponding pixel signals of the photoelectric conversion element receives the primary reflected light corresponding to the signal level of one of the reflected light incident on the front SL two-dimensional photosensor, A semiconductor circuit, comprising: a storage circuit that stores the pixel signal; and an image output unit that converts the pixel signal into an image based on the pixel signal read from the storage circuit and scanning information of the laser beam. Evaluation device.
【請求項2】 前記2次元光センサが2次元CCDセ
ンサであることを特徴とする請求項1記載の半導体装置
の評価装置。
2. The semiconductor device evaluation device according to claim 1 , wherein said two-dimensional optical sensor is a two-dimensional CCD sensor.
JP7032230A 1995-02-21 1995-02-21 Evaluation equipment for semiconductor devices Expired - Fee Related JP2859155B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7032230A JP2859155B2 (en) 1995-02-21 1995-02-21 Evaluation equipment for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7032230A JP2859155B2 (en) 1995-02-21 1995-02-21 Evaluation equipment for semiconductor devices

Publications (2)

Publication Number Publication Date
JPH08227922A JPH08227922A (en) 1996-09-03
JP2859155B2 true JP2859155B2 (en) 1999-02-17

Family

ID=12353177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7032230A Expired - Fee Related JP2859155B2 (en) 1995-02-21 1995-02-21 Evaluation equipment for semiconductor devices

Country Status (1)

Country Link
JP (1) JP2859155B2 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6244610A (en) * 1985-08-22 1987-02-26 Sumitomo Metal Ind Ltd Measuring method for cross sectional size of shape steel
JPH0212002A (en) * 1988-06-30 1990-01-17 Fujitsu Ltd Method and device for inspecting pattern
JPH04268404A (en) * 1991-02-22 1992-09-24 Tokai Rika Co Ltd Measuring apparatus for displacement and measuring apparatus for geometry
JP2992154B2 (en) * 1992-01-10 1999-12-20 富士電機株式会社 Appearance inspection device
JPH05187841A (en) * 1992-01-14 1993-07-27 I N R Kenkyusho:Kk Method for measuring two-or three-dimensional shape

Also Published As

Publication number Publication date
JPH08227922A (en) 1996-09-03

Similar Documents

Publication Publication Date Title
JP4351522B2 (en) Pattern defect inspection apparatus and pattern defect inspection method
KR100775437B1 (en) Pattern inspection device and method
US6411377B1 (en) Optical apparatus for defect and particle size inspection
US7881558B2 (en) Scanning microscope
JPH11108864A (en) Pattern defect inspection method and inspection device
KR20190049890A (en) Defect marking for semiconductor wafer inspection
JPH0671038B2 (en) Crystal defect recognition processing method
US5850467A (en) Image data inspecting method and apparatus providing for equal sizing of first and second image data to be compared
US6566671B1 (en) Microscopic defect inspection apparatus and method thereof, as well as positional shift calculation circuit therefor
US4659936A (en) Line width measuring device and method
US20070071308A1 (en) Workpiece inspection apparatus, workpiece inspection method and computer-readable recording medium storing program
US11703465B2 (en) Apparatus for inspecting semiconductor device and method for inspecting semiconductor device
JP2859155B2 (en) Evaluation equipment for semiconductor devices
CN114223017B (en) Design-assisted verification for DRAM and 3D NAND devices
JP4206393B2 (en) Pattern inspection method
JPH10300450A (en) Hole inspection method using charged particle beam
EP0989399A1 (en) Apparatus and method for measuring crystal lattice strain
JPH0658215B2 (en) Method and apparatus for inspecting a pattern to be inspected on a semiconductor wafer
JP4074624B2 (en) Pattern inspection method
JP3348168B2 (en) Crystal defect detection method and apparatus
US20080151259A1 (en) Synchronized wafer mapping
JP2002195955A (en) Semiconductor defect inspection method and semiconductor defect inspection device
JPH0621179A (en) Erasing method for eliminated area of ic chip
JP3366067B2 (en) Crystal defect detection method
JP2001074423A (en) Method for detecting height of minute projection, height detecting device, and defect detecting device

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19981104

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees