JP2859604B2 - Sliding correlator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization acquisition technique for establishing synchronization between a received signal spread by a spread code and a spread code generated on the receiving side in a receiver for spread spectrum communication or the like. is there.

[0002]

2. Description of the Related Art In North America, CDMA (Code Division)
Multiple Access) type cellular telephone system (TIA)
IS95) has been standardized. In this CDMA system, a sliding correlator is generally used to acquire synchronization between a received signal spread by a spreading code and a spreading code generated on the receiving side. The advantages of the sliding correlator are that the circuit scale can be reduced and the power consumption can be reduced.

FIG. 15 shows the configuration of such a conventional sliding correlator. However, in FIG. 15, a PN (Pseudo Noise) code is used as the spreading code. In FIG. 15, a PN code of the same spread code as that of the transmitting side is generated by a PN generator 103 for a received spread spectrum signal spread by a PN code, and the received spread spectrum signal and a PN code from the PN generator 103 are output. Is multiplied by the multiplier 101. Then, the multiplied signal output from the multiplier 101 is
Integrate at 2. This process is called despreading.

In this despreading, a PN code subjected to spectrum spreading and a PN code generated by a PN generator 103 are used.
If the phase with the code is synchronized, the output from the integrator 102 obtained by integrating the multiplication signal output from the multiplier 101 for a certain time exceeds a predetermined threshold value. When the control unit 104 detects that the predetermined threshold value is exceeded, the control unit 104 determines that the received spread spectrum signal is synchronized with the PN code generated by the PN generator 103.
Judge. Conversely, if the output from the integrator 102 does not exceed the predetermined threshold, the control unit 104 determines that synchronization has not been achieved, and sets the P output from the PN generator 103 to P.
The phase of the N code is shifted, and despreading is performed again.

[0005] Here, the length of the spread code composed of the PN code is N (the number of chips N), the time integrated by the integrator 102 is the time of L chips, and the received received spread spectrum signal has noise. Is not added and the phase of the PN code is random, the average synchronization acquisition time is a time corresponding to the number of NL / 2 chips. In this case, the PN generated by the PN generator 103 is used.
This is a case where the phase of the code is shifted by one chip.

[0006]

By the way, from the viewpoint of the code length of the spread code in the CDMA system, the above-mentioned average synchronization supplementary time is a long time that cannot be ignored with respect to the data communication speed. Since the received spread spectrum signal cannot be demodulated unless the synchronization capture is completed, there is a possibility that the first data portion of the received spread spectrum signal cannot be demodulated unless the synchronization acquisition time is reduced. There was a problem. Therefore, an object of the present invention is to reduce the synchronization acquisition time of a sliding correlator.

[0007]

SUMMARY OF THE INVENTION To achieve the above object, a sliding correlator according to the present invention generates a divided spreading code of M frames by dividing a spreading code having a code length of an integer power of 2 by M. A code generating means for generating a multi-level spreading code by adding all the divided spreading codes of the M frame; the multi-level spreading code or the divided spreading code generated by the code generating means; Despreading means for multiplying the received signal which has been frequency-spread by: an integrating means for integrating a multiplied output output from the despreading means in units of a frame length of the divided spreading code; and an output from the code generating means. And a control means for controlling the code to be output and determining the output level of the integration means, wherein the control means comprises a multi-level spreading code output from the code generation means. By determining the output level of the integrating means each time the phase is slid, the phase of the received signal frequency-spread by the spreading code and the phase of the multi-level spreading code are acquired. Output the divided spread code of any one of the M frames from the code generation means, and each time the relative phase with respect to the received signal slides in units of the frame length, the integration means By judging the output level, the reception signal frequency-spread by the spreading code is synchronized with any one of the M frames.

In the above-mentioned sliding correlator, the integrating means is controlled by the control means to calculate integrated values for all phases of the multi-level spreading code, and the integrated value outputted from the integrating means is calculated. By selecting the phase having the maximum value, the control means may acquire the phase of the received signal frequency-spread by the spreading code and the phase of the multi-level spreading code. Further, in the sliding correlator, when the integrated value output from the integrating means exceeds a preset threshold value for the integrated value output from the integrating means, the control means The multi-level spreading code may be determined to be phase-synchronized with the received signal frequency-spread by the spreading code.

Still further, in the above-mentioned sliding correlator, when the integrated value output from the integrating means exceeds a threshold value, the control unit does not slide the phase of the multi-level spreading code and slides the integrated signal. The integrated value output from the means is calculated again, and when the calculated value again exceeds the threshold value continuously, the phase of the multi-level spread code is added to the received signal frequency-spread by the spread code. It may be determined that synchronization has been achieved.

Still further, in the above-mentioned sliding correlator, when the received signal is divided into M frames and the output level of the integrating means is determined while sliding the phase of the received signal in units of the frame length, When the integration value output from the integration means exceeds a preset threshold value, the control means sets the divided spread code and the reception signal of any one of the M frames. It may be determined that the synchronization acquisition of the frame has been completed. In this case, when the output level of the integration means is determined while sliding the phase of the reception signal divided into the M frames in units of the frame length, the reception signal may be slid by M frames. If the integrated value output from the integration means does not exceed the preset threshold value, the control means may perform the synchronization acquisition processing again with the synchronization acquisition processing as an initial state.

According to the present invention, in order to synchronize the spread code, the spread code is divided into M and the divided spread codes are added to each other, so that the code length is 1 / M.
Is generated, and a phase synchronization acquisition is performed using the multi-level spreading code. Thereafter, since the synchronization of the frame with respect to the M-divided code is detected, high-speed synchronization acquisition can be performed. Also, when performing frame synchronization acquisition, a frame synchronization process is performed for a certain frame, so that only one frame of spread code need be stored in a memory for storing generated codes. Thus, the size of the circuit can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first configuration example of a sliding correlator according to an embodiment of the present invention. Hereinafter, a sliding correlator according to the present invention will be described in detail with reference to FIG. In FIG. 1, for example, PN
The received spread-spectrum signal spread by the code is supplied to the multiplier 1, and is multiplied by the multi-level spreading code read from the memory 3 and supplied to the multiplier 1. The multiplied signal of the received spread spectrum signal and the multi-level spread code output from the multiplier 1 is supplied to the integrator 2 and integrated. The integrated value in the integrator 2 is sent to the control unit 4, and the control unit 4 detects the phase synchronization from the integrated value output from the integrator 2 as described later. The control unit 4 controls the phase of the multi-level spreading code read from the memory 3 and controls the integrator 2
Is controlling the operation of

FIG. 2 schematically shows how to generate a multi-level spreading code read from the memory 3. In FIG. 2, a spreading code P (n) is a spreading code that is the same as the spreading code used for spectrum spreading on the transmitting side and has a chip number N of an integer power of 2 which is the same spreading code. n)
Is divided into M. The code length of each of the M-divided divided spreading codes is K chips, and each of the M-divided spreading codes is divided spreading code PN (k, 1) and divided spreading code PN (k,
2),..., Are represented as divided spreading codes PN (k, M). Here, each divided spreading code is represented by PN (k, m).
, And the divided spreading codes PN (k, m) arranged in time series are each referred to as a frame.
Here, k represents the phase of the divided spreading code, and m represents the frame number of the divided spreading code. Therefore, PN (k, m) = P {k + (m-1) .K} (1)

Therefore, as shown in FIG.
In (n), the divided spreading code PN (k, 1) is set as the first frame, and the divided spreading code PN (k, M) is set as the last frame. As shown in FIG. 2, the divided spreading codes PN (k, 1) to PN (k, M) of the M frame are supplied to the multi-value adder 41, respectively, as shown in FIG. To be added. Therefore,
The multi-value adder 41 outputs a generated code F (k) obtained by adding the M frames and multi-valued. in this case,
The code length of the generated code F (k) is K chips equal to one frame length, and the number K of chips of the generated code F (k) is K = N /
M is represented. Here, N is the code length of the spreading code P (n), and M is the number of divisions of the spreading code P (n).

The multi-valued generation code F (k) is generated in advance in the control unit 4 or externally and stored in the memory 3.
Is stored in The memory 3 stores at least one of the divided spreading codes PN (k, 1) to PN (k, M) of M frames. And
The control unit 4 in the present invention executes the synchronization acquisition process of the flowchart shown in FIG. 3 to generate the generated code F (k).
And a received spectrum spread signal. In the flowchart shown in FIG. 3, when the synchronization acquisition process starts, first, in step S1, the phase k is detected using the generated code F (k). Next, in step S2, the divided spreading code of one specific frame, here, the divided spreading code PN (k, 1)
Is used to detect the frame number m. As a result, synchronous acquisition is performed at high speed.

FIG. 4 shows the configuration of the phase k detection processing performed in step S1. The timing of the received spread spectrum signal P (n ') and the generated code F (k) in FIG. 5 is shown in FIG. 5, and the detection process of the phase k executed in step S1 will be described in detail with reference to FIGS. However, the received spread spectrum signal P (n ′) is divided into M frames and each frame is divided into M frames, and each of the divided M frames is divided into the received divided spread signals PN (k ′, 1), PN (k ′, 2), ..., P
It is represented by N (k ', M). First, the received spread spectrum signal P at the timing shown in FIG.
It is assumed that (n ′) is supplied to the multiplier 1 and the generated code F (k) is read from the memory 3 and supplied to the multiplier 1 at the timing shown in FIG.

For example, the received spread spectrum signal P
(N ′) and the generated code F (k) of the phase k are multiplied by the multiplier 1 for a time corresponding to two frames (represented by L = 2) from timing t0 to timing t1 as shown in FIG. Suppose. In this case, the generated code F of the phase k
(K) is repeatedly read out from the memory 3 twice and multiplied by the reception division spread signal PN (k ′, 1) and the reception division spread signal PN (k ′, 2), respectively. Then, during a period corresponding to two frames, the multiplied output output from the multiplier 1 is integrated by the integrator 2. The integrated waveform of the integrated value output from the integrator 2 is shown in FIG.
Is shown in In this example, the integration value is S (1) at the timing t1.

Next, the received spread spectrum signal P
The generated code F (k + 1) of the phase (k + 1) whose phase is advanced by one chip from the previous time with respect to (n ′) is read out from the memory 3, and as shown in FIG. During a period corresponding to a frame (represented by L = 2), the received spread spectrum signal P
(N '). In this case, the generated code F (k + 1) of the phase (k + 1) is repeatedly read twice from the memory 3, and the received divided spread signals PN (k ′, 3),
This is multiplied by the reception division spread signal PN (k ′, 4). Then, during the period corresponding to these two frames, the multiplied output output from the multiplier 1 is integrated in the integrator 2. FIG. 5C shows an integrated waveform of the integrated value output from the integrator 2. In this example, the integrated value is S (2) at the timing t2.

The integrated value shown in FIG.
The phase varies depending on whether or not the phase k of (k) and the phase of the received spread spectrum signal P (n ′) are synchronized. That is, if the phases are synchronized, the generated code F (k) and the received spread spectrum signal P (n ′) can be correlated, so that the multiplied signal output from the multiplier 2 is integrated by the integrator 2. As a result, a large-level correlation signal is output from the integrator 2 like the integrated value S (2) output at the timing t2 shown in FIG. 5C. When the phase of the generated code F (k) and the received received spread spectrum signal P (n ′) are not synchronized, the generated code F (k) and the received spread spectrum signal P (n ′) are not synchronized. Since the correlation cannot be obtained, the multiplier 1
Is integrated in the integrator 2, a small-level correlation signal is output from the integrator 2 as an integrated value S (1) output at the timing t1 shown in FIG. 5C. Become so. At the integration end timing, as shown in FIG.
Is reset to the initial value.

Therefore, every time the phase k of the generated code F (k) is shifted by a time corresponding to one chip, the level of the correlation signal output from the integrator 2 is detected by the control unit 4 so that the generated code F (k) is detected. It becomes possible to determine whether or not the phase of the received spread spectrum signal P (n ′) is synchronized with that of the received spread spectrum signal P (n ′). For example, in the case shown in FIG. 5, it is determined from the level of the integrated value S (2) output at the timing t2 that the synchronization has been acquired at the phase (k + 1). In the example shown in FIG. 5, the integration time is set to a time corresponding to two frames (L = 2). However, the present invention is not limited to this, and integration is performed during a period corresponding to more frames. It may be. The integration time at this time is a time corresponding to the KL code. Where K
Is the number of chips of the generated code F (k), and L is the number of integration section frames.

The above processing is executed in step S1,
Next, the process of step S2 described below is performed. In step S2, after the acquisition of the phase is completed, by detecting the frame number, the acquisition of the synchronization between one specific divided spread code PN (k, m) and the received spread spectrum signal P (n ') is performed. Will be FIG. 6 shows the configuration at the time of this frame number detection process. The received spread spectrum signal P (n ′) and the divided spread codes (k,
FIG. 12 shows an example of the timing m) and the output waveform of the integrator 2, and the frame number detection processing will be described in detail with reference to FIGS. However, the received spread spectrum signal P (n ′) is divided into M, and each frame is divided into the received divided spread signals PN (k ′, 1), PN (k ′, 2),
, PN (k ', M), and shows an example in which the divided spreading code PN (k, 1) of frame number 1 is used as the divided spreading code read from the memory 3.

As described above, a specific frame used for detecting the frame number is the split spreading code PN of the frame number 1.
(K, 1), and the divided spreading code PN (k, 1) is read from the memory 3 and supplied to the multiplier 1. The multiplier 1 multiplies one frame time starting from the timing t20 at this time by the multiplier 1 shown in FIGS.
In this example, as shown in FIG.
(K ′, M) and the divided spreading code PN (k, 1).
At this time, the received spread spectrum signal P (n ′)
Since the synchronous acquisition of the phase k between the received signal and the generated code F (k) has been completed, the frame number of the received spread signal PN (k ′, M) supplied to the multiplier 1 and the data read from the memory 3 are read. Divided spread code PN output and supplied to multiplier 1
If the frame number matches (k, 1), it means that the frame has been captured.

However, the frame number of the received divided spread signal supplied to the multiplier 1 at the timing t20 is M, and the frame number of the divided spread code is 1, so that the frames are not synchronized. Therefore, a low-level correlation signal is output as an integrated value obtained by time-integrating the multiplied signal output from the multiplier 1 corresponding to one frame length, such as the integrated value at the timing t21 in FIG. Become. Next, at timing t2
In 1, the divided spreading code PN (k, 1) read out from the memory 3 again is multiplied by the received divided spread signal PN (k ′, 1) one frame later than the previous time. At this time, the frame number 1 of the reception division spread signal PN (k ′, 1) and the multiplier 1 read from the memory 3
Since the frame number 1 of the divided spreading code PN (k, 1) supplied to the frame number coincides, the frame is synchronously acquired.

Therefore, by integrating the multiplied signal output from the multiplier 1 in the integrator 2 in units of time corresponding to one frame length, the integrator is integrated as in the integrated value at the timing t22 in FIG. 2 outputs a high-level correlation signal exceeding a predetermined threshold value. When the control unit 4 detects that this high-level start-up signal is output from the integral description 2, it is determined that frame synchronization has been completed. And the control unit 4
Outputs a synchronization detection signal and stops reading the divided spread code from the memory 3.

As described above, every time one frame length elapses, the divided spreading code PN of the same frame is repeatedly read from the memory 3.
By reading out (k, m) and supplying it to the multiplier 1, the multiplier 1 multiplies the received divided spread signal and the divided spread code by being relatively shifted by one frame. Then, the control unit 4 detects the level of the correlation signal output from the integrator 2 at each end timing of the frame, so that the divided spreading code PN (k, m) is detected.
It is determined whether or not the received frame is synchronized with the received spread spectrum signal P (n ′). This determination is made, for example, when the frame number of the divided spread code (k, m) matches the frame number of the received spread spectrum signal P (n ′) when the integrated output output from the integrator 2 exceeds a predetermined level. It can be determined that synchronization has been acquired.

The control unit 4 also sets the address of the memory 3 and controls the timing of the integrator 2. In the configuration shown in FIG. 1, the case where the address setting for reading out the generated code F (k) is set in FIG. And the divided spreading code P
FIG. 6 shows a case where the address is set to read N (k, 1). 4 and 6
Shows the same configuration as the configuration shown in FIG.
Only the manner in which the manner of operation is different is shown. As described above, in the sliding correlator according to the present invention, the phase synchronization acquisition is performed by the multi-level spreading code having a length of 1 / M by multi-value adding the spreading code divided into M frames by M frames. Next, since frame synchronization is performed by using a specific one-frame divided spreading code, high-speed synchronization can be performed.

Next, FIG. 7 shows a configuration of a first modified example when performing phase synchronization acquisition. In this first modification,
The timing control section 5 sets the address of the memory 3 and controls the timing of the integrator 2. And
The phase k of the generated code F (k) is determined by the timing control unit 5.
Is slid one chip at a time, and the integrator 2 performs integration for the KL code for all the phases k. When the integration for all the phases k is completed, the maximum integration value of the integration values output from the integrator 2 is detected by the maximum value detection unit 6. Next, the synchronization detection determination unit 7 determines the phase k based on the detection timing of the maximum value in the maximum value detection unit 6. Thereby, phase synchronization acquisition can be performed. In the first modification, the control unit 4 includes a timing control unit 5, a maximum value detection unit 6, and a synchronization detection determination unit 7.

FIG. 8 shows a second modified example in which the phase synchronization acquisition is performed. This second modified example is different from the first modified example in that a threshold value judging unit 8 for setting a threshold value in advance for an output value from the integrator 2 is provided. In the second modified example, the timing control section 5 sets the address of the memory 3 and controls the timing of the integrator 2. Then, each time the phase k of the generated code F (k) is slid one chip at a time, the timing controller 5 performs integration of the KL code in the integrator 2. Next, the threshold value judging section 8 detects whether or not the integrated value output from the integrator 2 at the end timing of this integration exceeds a preset threshold value. Then, the synchronization detection judging section 7 is provided with the threshold judging section 8
, The phase k is determined based on the timing at which the threshold value is exceeded. Thereby, phase synchronization acquisition can be performed.

Further, a third method for performing phase synchronization acquisition is as follows.
9 is shown in FIG. This third modified example is an integrator 2
When the output value from exceeds the preset threshold,
This is different from the second modification in that the integration is performed again at the same phase and the phase k is determined based on whether or not the integrated value exceeds the threshold value again. In the third modified example, the timing control section 5 sets the address of the memory 3 and controls the timing of the integrator 2. Each time the phase k of the generated code F (k) is slid by one chip,
The integration for L codes is performed in the integrator 2. At the end timing of this integration, threshold value judging section 9 detects whether or not the integrated value output from integrator 2 exceeds a preset threshold value. Then, when the threshold value judging unit 9 detects that the threshold value has been exceeded, a flag is set in the register 10.

When the flag is set in the register 10, the synchronization detection judging unit 7 instructs the timing control unit 5 to read out the generated code F (k) having the same phase k from the memory 3 again. Then, the timing controller 5 performs the second integration of the KL code with respect to the generated code F (k) having the same phase,
It is performed again in the integrator 2. At the end timing of this integration, the threshold value judging unit 9 detects whether or not the integrated value output from the integrator 2 exceeds the preset threshold value again. Then, when the threshold value is again detected by the threshold value judging unit 9, the phase k is determined by the synchronization detection judging unit 7 based on this detection. Thereby, the reliability of the phase synchronization acquisition can be improved.

FIG. 10 shows an example of the timing of the received spread spectrum signal P (n '), the generated code F (k), and the output waveform of the integrator 2 in the third modification. In FIG. 10, the reception division spread signal PN
(K ′, 1), the multiplied signal of the reception division spread signal PN (k ′, 2) and the generated code F (k) of the phase k read from the memory 3 during the period from timing t10 to timing t11, 2 is integrated. The integration value S (1) at the integration period end timing t11 is as shown in FIG.
As shown in (c), the threshold value is not exceeded. Therefore, the generated code F read from the memory 3
The phase of (k) is changed from the phase k to the phase (k + 1), and the generated code F (k + 1) is read from the memory 3. Then, from timing t11 to timing t
In a period of 12, the integrator 2 integrates a multiplication signal of the generated code F (k + 1), the reception division spread signal PN (k ′, 3), and the reception division spread signal PN (k ′, 4).

The generated code F (k +) of this phase (k + 1)
Assuming that the integration value S (2) exceeds the threshold value indicated by the broken line at the integration end timing t12 at the time of 1) as shown in FIG. 10C, the generation code F () of the phase (k + 1) is again obtained. k + 1) is read from the memory 3. Then, in the generated code (k + 1), the integrated value with the received divided spreading code is calculated again, and at this integration end timing t13, the integrated value S (3) continues as shown in FIG. 10 (c). If the threshold value is exceeded, the phase is determined to be phase (k + 1). As described above, in the generated code having the same phase, the phase is determined when it is detected that the integrated value exceeds the threshold value again, so that the reliability of phase synchronization acquisition can be improved.

The configuration shown in FIG. 11 is a diagram showing a modified example when the frame is synchronously acquired. FIG. 12 is a diagram showing the reception spread spectrum signal P in the configuration shown in FIG.
FIG. 9 is a diagram showing an example of (n ′), the timing of the divided spreading code PN (k, m), and an output waveform of the integrator 2. FIG.
In the modified example shown in FIG.
And the timing control of the integrator 2 is performed. Then, the divided spread code PN (k, 1) is repeatedly read out by the timing control unit 5, and the integration of one frame for all the frames of the received divided spread code is sequentially performed in the integrator 2. The threshold value judging unit 11 detects whether or not the integrated value output from the integrator 2 at each end timing of the integration for one frame exceeds a preset threshold value. For example, as shown in FIG. 12C, at timing t22, when the threshold value judging unit 11 detects that the output integrated value exceeds the threshold value, the threshold value judging unit 11 outputs the detection output. Then, in response to this, the synchronization detection determination unit 7 determines the frame number based on the timing when it is detected that the threshold value has been exceeded. This makes it possible to capture frames synchronously.

FIG. 13 is a flowchart showing a modification of the sliding correlator according to the present invention. In this flowchart, when the phase acquisition process is started, first, in step S11, the phase k is detected by the generated code F (k). Next, in step 12, the frame number m is detected by using the divided spreading code of one specific frame, here, the divided spreading code PN (k, 1). If the output of the integrator 2 does not exceed the threshold value K times in a row at this time, step S1
Returning to step 1, the sliding correlator is initialized so that the phase synchronization acquisition process is performed again and then the frame number detection process is performed again. This makes it possible to reliably perform synchronization acquisition in the sliding correlator.

Next, FIG. 14 shows a computer simulation result of the detection characteristic of the phase k by the generated code F (k) in the first modified example shown in FIG. Where the spreading code P
The number of spreading taps of the PN code constituting (n) is 15, the number of divisions M of the spreading code P (n) is 128, and the number of phases K is
Is 256. The integration section at the phase k is set to L · K chips. Also, all phases k (k
= 1, 2, ..., K), and the evaluation is made based on the probability (frame detection error rate) that the phase k at which the correlation value becomes maximum becomes an incorrect phase. SN shown in FIG.
Referring to the simulation result of the frame detection error rate with respect to the ratio, when the SN ratio is 5 dB and the number of frames L in the integration section is 16, a good value of 2% or less is obtained as the frame detection error rate.

In the conventional sliding correlator, the number of spreading taps of the PN code is 15, and the integration interval is 1
If the correlation detection is always performed when 28 chips are used, the average synchronization acquisition time is a time corresponding to 2 21 (15 + 7-1) chips. Further, according to the sliding correlator of the present invention, when the number of integration section frames L is 16 and the calculation is performed for all phases k,
The average synchronization acquisition time of the phase is 2 ^ 20 chips (KK
L), and the frame acquisition time is 2 14 chips (M · K / 2). Therefore,
If the average synchronization acquisition time in the sliding correlator of the present invention is approximately 2 @ 20 chips, the synchronization acquisition time can be reduced to about 1/2 as compared with the conventional sliding correlator, and the synchronization acquisition time can be reduced. It can be performed at high speed.

[0037]

As described above, according to the sliding correlator of the present invention, in order to perform synchronization acquisition of a spread code, the spread code is divided by M, and the divided spread codes are added to each other. A new multi-level spreading code having a length of 1 / M is generated, and phase synchronization is acquired using the multi-level spreading code. Thereafter, since the synchronization of the frame with respect to the M-divided code is detected, high-speed synchronization acquisition can be performed. Also, when performing frame synchronization acquisition, a frame synchronization process is performed for a certain frame, so that only one frame of spread code need be stored in a memory for storing generated codes. Thus, the size of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first configuration example of an embodiment of a sliding correlator according to the present invention.

FIG. 2 is a diagram for explaining a generated code generated in the sliding correlator of the present invention.

FIG. 3 is a flowchart showing a correlation process of a sliding correlator according to the present invention.

FIG. 4 is a block diagram showing a configuration of synchronous acquisition of a phase in the sliding correlator of the present invention.

FIG. 5 is a diagram showing signs and integral waveforms of respective units of the configuration shown in FIG.

FIG. 6 is a block diagram showing a configuration of frame synchronization acquisition in the sliding correlator of the present invention.

FIG. 7 is a diagram showing a block diagram of a first modification of synchronous acquisition of phase in the sliding correlator of the present invention.

FIG. 8 is a diagram showing a block diagram of a second modification of synchronous acquisition of phase in the sliding correlator of the present invention.

FIG. 9 is a diagram showing a block diagram of a third modification of synchronous acquisition of phase in the sliding correlator of the present invention.

10 is a diagram showing signs and integral waveforms of each part of the configuration shown in FIG.

FIG. 11 is a block diagram showing a modification of the configuration of synchronous acquisition of a frame in the sliding correlator of the present invention.

12 is a diagram showing a sign and an integral waveform of each part of the configuration shown in FIG. 11;

FIG. 13 is a flowchart showing a modified example of the sliding correlator of the present invention.

FIG. 14 is a diagram showing a characteristic of an SN ratio versus a frame detection error rate in the first modified example shown in FIG. 7;

FIG. 15 is a diagram showing a configuration of a conventional sliding correlator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Integrator 3 Memory 4 Control part 5 Timing control part 6 Maximum value detection part 7 Synchronization detection judgment part 8, 9, 11 Threshold judgment part 10 Register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 1/707 H04L 7/00

Claims (6)

(57) [Claims] 1. A multi-level spreading code is generated by dividing a spreading code having a code length of an integer power of 2 by M to generate a divided spreading code of M frames and adding all the divided spreading codes of the M frame. Code generating means, a despreading means for multiplying the multi-level spreading code or the divided spreading code generated by the code generating means and a received signal frequency-spread by the spreading code, Integrating means for integrating the multiplied output to be output in units of a frame length of the divided spreading code; and control means for controlling a code output from the code generating means and determining an output level of the integrating means. The control means determines the output level of the integration means every time the phase of the multi-level spread code output from the code generation means is slid. The phase synchronization between the received signal frequency-spread by the code and the multi-level spreading code is performed, and then the control unit changes the divided spreading code of any one of the M frames into the code. Each time the relative phase with respect to the received signal is slid in units of the frame length, the received signal is frequency-spread by the spreading code.
A sliding correlator for performing synchronization acquisition with any one of the M frames. 2. The integration means is controlled by the control means to calculate integrated values for all phases of the multi-level spreading code, and the phase at which the integrated value output from the integrating means is maximized. By selecting, the control means, the received signal frequency-spread by the spreading code,
2. The sliding correlator according to claim 1, wherein synchronization acquisition of a phase with the multi-level spreading code is performed. 3. When the integrated value output from the integration means exceeds a preset threshold value for the integrated value output from the integration means, the control means controls the spread code by using the spread code. 2. The sliding correlator according to claim 1, wherein it is determined that the multi-level spreading code is phase-locked to the frequency-spread received signal. 4. The controller according to claim 1, wherein the controller outputs the integrated value output from the integrating means without sliding the phase of the multi-level spreading code when the integrated value output from the integrating means exceeds a threshold value. Is calculated again, and when the recalculated integral value also continuously exceeds the threshold value, it is determined that the multi-level spreading code is phase-synchronized with the received signal frequency-spread by the spreading code. The sliding correlator according to claim 3, wherein 5. When the output level of the integrating means is determined while dividing the received signal into M frames and sliding the phase of the received signal in units of the frame length,
When the integration value output from the integration means exceeds a preset threshold value, the control means sets the divided spread code and the reception signal of any one of the M frames. 2. The sliding correlator according to claim 1, wherein it is determined that synchronization acquisition of the frame is completed. 6. Each time the phase of the received signal divided into the M frames is slid in units of the frame length, when the output level of the integrating means is determined, the received signal may be slid by M frames. When the integrated value output from the integration means does not exceed the preset threshold value, the control means performs the synchronization acquisition processing again with the synchronization acquisition processing as an initial state. The sliding correlator according to claim 5, wherein