JP2859613B2 - Diagnostic device for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] An integrated circuit diagnostic apparatus, comprising: a power supply means for detecting an integrated circuit from a power supply means in parallel with a determination based on a test result pattern corresponding to a test pattern input to the integrated circuit from a test pattern generating means; By performing the determination based on the output current value in parallel, the time required for the diagnosis can be reduced and the reliability of the diagnosis can be increased. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic device for an integrated circuit, and more particularly, to an integrated circuit configured to diagnose a short-circuit fault while performing a stack fault diagnosis of a large-scale integrated circuit (LSI). The present invention relates to a circuit diagnostic device. 2. Description of the Related Art An integrated circuit such as an LSI is hermetically sealed in a manufacturing process, and only a power supply terminal and an input / output terminal are exposed outside. Therefore, a stack failure diagnosis is generally performed to check whether the internal state is normal. In the stack fault diagnosis, a test pattern that can diagnose the H / L stack fault of each terminal in the LSI is input from the input terminal of the LSI to check whether there is any abnormality in the logic logic inside the LSI. To determine the result pattern obtained from the output terminal. This determination is continuously performed for many patterns that are assumed to be abnormal. The short fault diagnosis is to check whether a circuit inside the LSI is physically short-circuited. The location where a short circuit is assumed increases according to the gate size, so that diagnosing all points results in a long pattern. For this reason, by actually using a stack failure diagnosis pattern or the like and applying this to the LSI and checking the power supply current value at that time, an excessive current due to a short circuit is detected, and an abnormality is determined. The method is used. [Problems to be Solved by the Invention] By the way, in the above-mentioned conventional method, a short-circuit fault diagnosis is performed by using the pattern at the same time as the stack fault diagnosis. Thereafter, the operation of applying the same pattern to the LSI, stopping at a certain pattern, and measuring the power supply current value will be repeated. The diagnosis rate increases as the number of measurement points increases. However, when the current tester is used, the measurement time increases, so that the number of measurement points must be reduced. In addition, the number of diagnostic patterns increases as the size of the LSI increases, so that there is a problem that the time spent for diagnosis increases. Further, as described above, the method of stopping the pattern halfway for the short fault diagnosis has a problem that the diagnosis takes a long time. The present invention has been made in view of the above circumstances, and has as its object to provide an integrated circuit diagnostic apparatus that reduces the time required for diagnosis and increases the reliability of diagnosis. . [Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of an integrated circuit diagnostic apparatus according to the present invention. In the figure, a test pattern generator 121 inputs a test pattern for diagnosis to the integrated circuit 199. The power supply unit 131 supplies a voltage to the integrated circuit 199, and outputs a current value at that time to the current determination unit 171. The current table storage unit 161 stores a non-defective power supply current value corresponding to the test pattern for each test pattern. The current determining unit 171 determines that a certain test pattern is
Output current value of the power supply means 131 when input to the
The power supply current value of the non-defective product corresponding to the test pattern stored in the current table storage unit 161 is compared to determine whether the output current value of the power supply means is normal. Therefore, the overall configuration is such that the determination of the test result pattern and the determination of the current value are performed in parallel. [Operation] The test pattern generation means 121 inputs a test pattern for diagnosis to the integrated circuit 199. For each test pattern,
A non-defective power supply current value corresponding to the test pattern is stored in the current table storage unit 161. The current determination unit 171 compares the output current value of the power supply unit 131 when a certain test pattern is input to the integrated circuit 199 with the power supply current value of a non-defective product corresponding to the test pattern stored in the current table storage unit 161. Then, it is determined whether or not the output current value of the power supply means is normal. According to the present invention, since a non-defective power supply current value is stored in the current table storage unit, the time required for diagnosis is reduced by comparing the power supply current value to the integrated circuit,
The reliability of diagnosis can be improved. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows the configuration of a diagnostic device for an integrated circuit according to one embodiment of the present invention. I. Correspondence Between Embodiments and FIG. 1 Here, correspondences between the embodiment of the present invention and FIG. 1 will be described. The test pattern generation unit 121 corresponds to the control unit 211 and the test pattern generation unit 221. The power supply unit 131 corresponds to the control unit 211, the power supply unit 231, and the power measurement unit 233. The current table storage unit 161 includes a control unit 211, a current value determination unit 2
41, which corresponds to the current table storage unit 243. The current determination unit 171 corresponds to the control unit 211, the logic determination unit 251, and the logic table storage unit 253. The integrated circuit 199 corresponds to the device under test 299. II. Configuration of Embodiment An embodiment of the present invention will be described below assuming that there is a correspondence as described above. In FIG. 2, an LSI tester 200 generates a control unit 211 for controlling the whole, a test pattern, and an external device under test 29.
9, a test pattern generator 221, a power supply unit 231 for supplying power to the device under test 299, a current measurement unit 233 for detecting a current value from the power supply unit 231 to the device under test 299, and a current value determination. Current value determination unit 241 to be performed, a current table storage unit that stores a comparison value for determination by the current value determination unit 241
243, a logic determination unit 251 for performing a logic determination based on a result pattern obtained from the device under test 299, a logic table storage unit for storing a comparison value for performing a logic determination in the logic determination unit 251
Consists of 253. The device under test 299 is a device under test for diagnosis, such as a CMO
Assume LSI of S. The test pattern generation unit 221, the power supply unit 231, the current value determination unit 241, the current table storage unit 243, the logic determination unit 251, and the logic table storage unit 253 are connected to the control unit 211. The test pattern generator 221 is connected to the input terminal of the external device under test 299, and the power supply unit 231 is connected to the input terminal (power terminal) of the device under test 299 via the current measuring unit 233. . The current value judgment unit 241 is connected to the current measurement unit 233 and the current table storage unit 243, and the logic judgment unit 251
It is connected to the output terminal of 299 and the logical table storage unit 253. III. Operation of Embodiment The logical table storage unit 253 stores in advance a non-defective product (C
A stack failure diagnosis is performed for the MOS-LSI, and the result pattern obtained therefrom is stored. Further, the current value of the power supply corresponding to each pattern of the stack failure diagnosis is measured for the non-defective product in the current table storage unit 243, and the measured value is stored. In the following, reference is made to FIG. First, the control unit 211 sends an instruction to the power supply unit 231 and
A voltage for operating the device under test 299 is supplied.
The output voltage of the power supply unit 231 is supplied to the device under test 299 via the current measurement unit 233. The current measurement unit 233 measures the current value at that time and inputs the current value to the current value determination unit 241. Next, the control unit 211 sends an instruction to the test pattern generation unit 221, the logic table storage unit 253, and the current table storage unit 243. The test pattern generator 221 creates a first test pattern and inputs it to the device under test 299. When the test pattern is input, the device under test 299 outputs a result pattern corresponding to the test pattern, and the logic determination unit 251 receives the result pattern. The logical table storage unit 253
A non-defective result pattern corresponding to the first test pattern is input to the logic determination unit 251. The logic determination unit 251 compares the non-defective result pattern from the logic table storage unit 253 with the result pattern input from the device under test 299, and if they are the same, determines that the first test pattern is normal. to decide. In addition, the current table storage unit 243 stores the non-defective power supply current value corresponding to the first test pattern in the current value determination unit 241.
To enter. The current determination unit 241 compares the measured current value of the device under test 2991th input from the current measurement unit 233 with the actually measured value of the non-defective product input from the current table storage unit 243, and considers the variation. Determine if the value is normal. Thus, the determination by the current value determination unit 241 and the logic determination unit 251 for the first test pattern ends. Next, the control unit 211 inputs the second test instruction to the test pattern generation unit 221, the logic table storage unit 253, and the current table storage unit 243, and performs the same determination as that of the first test pattern. Hereinafter, determination is similarly performed for all test patterns. Since the current value detected by the current measurement unit 233 is not stable immediately after the test pattern is changed, the control unit 21 detects the value immediately before the test pattern is changed.
Control is performed by 1. Further, a means (for example, a display or a buzzer) for notifying the quality of the device under test 299 to the outside after the determination by the current value determination unit 241 and the logic determination unit 251 is omitted. IV. Summary of Embodiments As described above, the current value of the power supply is measured by the current measuring unit 233 for each test pattern of the normal stack failure diagnosis.
Then, the current value determination unit 24 determines whether the value is normal.
Judge with 1 and perform short fault diagnosis. Therefore, the stack failure diagnosis and the short failure diagnosis are performed in parallel, so that the time required for the diagnosis can be reduced, and the reliability of the diagnosis can be increased. V. Modifications of the Invention In the above-described embodiment of the present invention, the device under test 299 is a CMOS LSI. However, even for other devices, short-circuit The present invention is applicable as long as the diagnosis can be made. In “I. Correspondence between the embodiment and FIG. 1”,
Although the correspondence between FIG. 1 and the present invention has been described, the present invention is not limited to this, and those skilled in the art can easily infer that there are various modifications. [Effects of the Invention] As described above, according to the present invention, the determination based on the test result pattern corresponding to the test pattern input to the integrated circuit from the test pattern generation unit and the determination based on the output current value from the power supply unit are performed in parallel. This is very useful in practice.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the principle of an integrated circuit diagnostic apparatus according to the present invention, and FIG. 2 is a block diagram showing the configuration of an integrated circuit diagnostic apparatus according to an embodiment of the present invention. In the figure, 121 is a test pattern generating means, 131 is a power supply means, 141 is a first determining means, 151 is a second determining means, 199 is an integrated circuit, 200 is an LSI tester, 211 is a control section, 221 is a test pattern generating section Reference numeral 231 denotes a power supply unit, 233 denotes a current measurement unit, 241 denotes a current value determination unit, 243 denotes a current table storage unit, 251 denotes a logic determination unit, 253 denotes a logic table storage unit, and 299 denotes an element to be measured.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28

Claims (1)

(57) [Claims] Test pattern generating means for inputting a test pattern for diagnosis to an integrated circuit; power supply means for supplying a voltage to the integrated circuit and outputting a current value at that time; non-defective products corresponding to the test pattern for each test pattern A current table storage unit for storing the power supply current value of the power supply unit, an output current value of the power supply unit when a certain test pattern is input to the integrated circuit, and a current pattern corresponding to the test pattern stored in the current table storage unit. A current determining unit that compares the non-defective power supply current value with the output current value and determines whether the output current value is a normal value. 2. A logic table storage unit for storing a non-defective result pattern corresponding to each test pattern; and a test in which a result pattern from the integrated circuit when the test pattern is input to the integrated circuit is stored in the logic table storage unit. 2. The diagnostic device for an integrated circuit according to claim 1, further comprising: a logic determination unit configured to determine whether the result pattern of the non-defective product corresponds to a pattern.