JP2859966B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
And, in particular, store memory cells and information of the memory cells.
Semiconductor storage device with improved information transfer to and from storage unit
About.

[0002]

2. Description of the Related Art Conventionally, in order to improve the cost performance of a computer system, a high-speed buffer is provided between a main memory constituted by a low-speed, large-capacity, and low-cost DRAM and a central processing unit (CPU). It is common practice to provide a small-capacity high-speed memory. This high-speed buffer is called a cache memory, and blocks of data likely to be required by the CPU are copied from the main memory and stored.
When data stored in the address of the DRAM to be accessed by the CPU exists in the cache memory, this is called a hit, and the CPU accesses the high-speed cache memory. On the other hand, when the data stored at the address to which the CPU tries to access does not exist in the cache memory, it is called a cache miss and
The PU accesses the low-speed main memory and simultaneously transfers the block to which the data belongs to the cache memory.

However, since such a cache memory system requires an expensive high-speed memory, it cannot be used in a small-sized system in which cost is important. Therefore, conventionally, a simple cache system has been configured using a page mode or a static column mode of a general-purpose DRAM.

FIG. 5 is a block diagram showing a basic structure of a conventional DRAM device capable of a page mode or a static column mode.

In FIG. 1, a plurality of pairs of word lines (not shown) and a plurality of pairs of bit lines (not shown) are arranged in a memory cell array 1 so as to intersect with each other. (Not shown) is provided. The word line of the memory cell array 1 is a word driver 2
Is connected to the row decoder unit 3 via the. The bit line pair of memory cell array 1 is connected to sense amplifier unit 4 and I
It is connected to a column decoder 6 via an / O switch 5. A row address buffer 7 is connected to the row decoder unit 3, and a column address buffer 8 is connected to the column decoder unit 6. The row address buffer 7 and the column address buffer 8 are supplied with a multiplex address signal MPXA obtained by multiplexing the row address signal RA and the column address signal CA. Further, an output buffer 9 and an input buffer 10 are connected to the I / O switch unit 5.

FIG. 6 is a waveform diagram showing a read operation of a conventional DRAM, and is shown in FIGS. 6 (a), 6 (b) and 6
(C) shows operation waveform diagrams of a normal read cycle, page mode cycle, and static column mode cycle of the DRAM, respectively.

In the normal read cycle shown in FIG. 6A, first, the row address buffer 7 takes in the multiplexed address signal MPXA at the falling edge of the row address strobe signal / RAS and outputs it as the row address signal RA. This is given to the decoder unit 3. Row decoder unit 3 selects one of the plurality of word lines according to the row address signal RA. Thereby, information in a plurality of memory cells connected to the selected word line is read out to each bit line, and the information is detected and amplified by the sense amplifier unit 4. At this point, information of one row of memory cells is latched in the sense amplifier unit 4. Next, the column address buffer 8 takes in the multiplex address signal MPXA at the falling edge of the column address strobe signal / CAS and supplies it to the column decoder section 6 as a column address signal CA. The column decoder unit 6 selects one of the information of one row latched in the sense amplifier unit 4 according to the column address signal CA. The selected information is output to the output data D via the I / O switch unit 5 and the output buffer 9.
_It is taken out as _OUT . The access time (RAS access time) t _{RAC in} this case is the time from the falling edge of the row address strobe signal / RAS until the output data D _OUT becomes valid. In this case, the cycle time t _c is the sum of the time during which the element is in the active state and the RAS precharge time t _RP, and as a standard value, t _c = 100 ns when t _RAC = 100 ns It is about 200 ns.

In the page mode and the static column mode shown in FIGS. 6B and 6C, memory cells on the same row are accessed by changing a column address signal CA. In the page mode, the column address signal CA is latched at the falling edge of the column address strobe signal CAS. In the static column mode, access is made only by a change in the column address signal CA as in a static RAM (SRAM). The bar CAS access time t _CAC and the address access time t _AA in the page mode and the static column mode are almost _値 of the RAS access time t _RAC , and are about 50 ns for t _RAC = 100 ns.
In this case, the cycle time is also _{shortened. In} the case of the page mode, a value of about 50 ns similar to that of the static column mode is obtained depending on the value of the CAS precharge time t _cP .

FIG. 7 is a block diagram showing a configuration of a simple cache system using the page mode or the static column mode of the DRAM device of FIG. FIG. 8 is an operation waveform diagram of the simple cache system of FIG.

In FIG. 7, a main memory 20 has 1M ×
The configuration is made up of 1 Mbyte by eight DRAM elements 21 having one configuration. In this case, the row address signal RA and the column address signal CA have a total of 20 bits (2 ²⁰ = 104857).
6 = 1M). Address multiplexer 22
Supplies a 10-bit row address signal RA and a 10-bit column address signal CA to the main memory 20 in two separate steps, and receives 20 address lines A _{0 to} A ₁₉ that receive a 20-bit address signal. And ten address lines A _{0 to} A ₉ for applying a 10-bit address signal (multiplex address signal MPXA) multiplexed to the DRAM element 21.

The address generator 23 includes a CPU 24
Generates an address signal corresponding to the required data. The latch (TAG) 25 holds the row address signal RA corresponding to the data selected in the previous cycle, and the comparator 26 outputs the 10-bit row address signal RA of the 20-bit address signal and the TAG 25 The stored row address signal RAL is compared with the stored row address signal RAL. If they match, the same row as in the previous cycle has been accessed (hit), and the comparator 26 generates a high-level cache hit signal (Cache Hit) signal CH. The state machine 27 outputs the cache hit signal CH
, The page mode control for toggling the column address strobe signal CAS while keeping the row address strobe signal RAS at a low level is performed. In response, the address multiplexer 22 transmits the column address signal CA to the DRAM element 21. (FIG. 8). In the case of such a hit, output data can be obtained at high speed from the DRAM element 21 at the access time t _CAC .

On the other hand, when the row address signal RA generated by the address generator 23 does not match the row address signal RAL held by the TAG 25, a row different from the previous cycle was accessed (cache miss). That is, the comparator 26 does not generate the high-level cache hit signal CH. In this case, the state machine 27 outputs signals RAS and CA in a normal read cycle.
S control is performed, and the address multiplexer 22 sequentially transmits the row address signal RA and the column address signal CA to the DRAM.
This is given to the element 21 (FIG. 8). In the case of such a cache miss, a normal read cycle starting from precharging of RAS is performed, and a low access time t
_Since output data can be obtained by _RAC , the state machine 27 generates a wait signal Wait, and the CPU 2
Wait for 4. TAG2 in case of cache miss
5 holds the new row address signal RA.

As described above, in the simplified cache system shown in FIG. 7, since data of one row (1024 bits in the case of a 1-Mbit device) of a memory cell array of a DRAM device is one block, the block size becomes unnecessary. As a result, the number of blocks (the number of entries) held in the TAG 25 is insufficient (one entry in the system of FIG. 7), and there is a problem that the cache hit rate is low.

As another conventional example, there is a simple cache system as disclosed in US Pat. No. 4,577,293.
A register for holding data for a row is provided outside the memory cell array, and when a hit occurs, data is directly taken out from this register to speed up access. However, in the simple cache system disclosed in this patent publication as well, the external register holds data for one row of the memory cell array, and the block size (for one row) is unnecessarily large. As in the conventional example shown in FIG. 1, there is a problem that the cache hit rate is low.

A DRAM device with a built-in cache memory shown in FIG. 9 has been proposed.

This DRAM device is different from the DRAM device of FIG. 5 in the following points. That is, the DRAM memory cell array 1 is divided into a plurality of blocks composed of a plurality of columns of memory cells in the address space. In FIG. 9, it is divided into four blocks B1 to B4.
Further, a transfer gate unit 11 and an SRAM memory cell array 12 are provided between the sense amplifier unit 4 and the I / O switch unit 5, and a block decoder 13 and a way decoder 14 are further provided. A part of the column address signal CA is supplied from the column address buffer 8 to the block decoder 13 in accordance with the number of blocks. The activation of the column decoder 13 is controlled by the cache hit signal CH. The way decoder 14 is supplied with a way address signal WA via a way address buffer 15. The way decoder 14 selectively drives a word line of the SRAM memory cell array 12 according to the way address signal WA.

FIG. 10 is a diagram showing in detail the structure of a part of the DRAM device shown in FIG.

[0018] In FIG. 10, the sense amplifier unit 4, tigers <br/> Nsufu § Gate unit 11, SRAM memory cell array 1
2, the I / O switch unit 5 and the column decoder unit 6
A plurality of sense amplifiers 40, transfer gates 110, SRAM memory cells 120, and a plurality of bit lines BL and bar BL of the AM memory cell array 1 are respectively provided.
It comprises an I / O switch 50 and a column decoder 60. A block decoder 13 is arranged corresponding to each block of the DRAM memory cell array 1. Each sense amplifier 40 is connected between each bit line pair BL and / BL. Each bit line pair BL and / BL is a transfer gate 1 composed of N-channel MOSFETs Q1 and Q2.
10 are connected to a pair of bit lines SBL and / SBL of the SRAM memory cell array 12. The bit line pair SBL and bar SBL of the SRAM memory cell array 12 are N
I / I via channel MOSFETs Q3 and Q4, respectively.
It is connected to the O bus I / O and the bar I / O. A common transfer signal is applied to the gates of the MOSFETs Q1 and Q2 of the transfer gate 110 by the block decoder 13 for each block. Also, each I / O switch 50
Of the MOSFETs Q3 and Q4 are supplied with a column selection signal by the corresponding column decoder 60.

In this DRAM device, the block decoder 13 supplies a transfer signal to a transfer gate 110 corresponding to each block, so that data on the same row from the DRAM memory cell array 1 in block units is S.
The data is transferred to the RAM memory cell array 12. If the way the decoder 14 either of the word lines W ₁ to _W-n of the SRAM memory cell array 12 is selected, the data stored in the SRAM memory cell 120 connected each bit line pair to the word line SBL, bar SBL Read on. The data read onto bit line pair SBL and / SBL is supplied to I / O switch 50 by applying a column selection signal from column decoder 60 to I / O switch 50.
O, bar I / O is read.

According to this DRAM device, one row of data in a plurality of columns is regarded as one data block, and a plurality of data blocks on different rows are divided into a plurality of SRAM memory cells 12.
In addition to being held at 0, data blocks on different rows in the same column are simultaneously held on the SRAM memory cell array 12 (association). Therefore, this SRA
If the M memory cell array is used as a cache memory, the number of data entries can be increased, and as a result,
The hit rate of the cache can be improved.

Further, if the word lines W _{1 to} W _n of the SRAM memory cell array 12 are kept inactive, the DR
A configuration in which data is not transferred to the cache memory even at the time of writing to the AM memory cell array 1 or at the time of reading from the DRAM memory cell array 1 becomes possible, and the advantage that the degree of freedom for application to a cache memory system is increased. .

FIG. 11 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG.

In FIG. 11, the main memory 30 has 1M
It is constituted by 1M bytes by eight DRAM elements 31 having a × 1 configuration. The memory system of FIG. 11 differs from the memory system of FIG. 7 in that the number of TAGs 25 and the number of comparators 26 correspond to the number of blocks of the DRAM element 31 and the number of word lines (the number of sets) of the SRAM memory cell array 12. The point of increase and the cache hit signal CH which is the output from the comparator 26
And the way address signal WA is input to the DRAM element 31. Here, the way address signal WA is 2 bits.

FIG. 6 shows the operation of the simple cache system shown in FIG. 11 used for describing the conventional simple cache system.
This will be described with reference to (a), FIG. 6 (c) and the operation waveform diagram of FIG.

The TAG 25 holds a plurality of row addresses corresponding to the row selected in the newest cycle for each block as a plurality of cache address sets.
Here, since two bits are considered as the way address signal WA, four sets of row addresses are held. Therefore, assuming that the number of blocks is 4, 16 address sets are stored in the TAG 25. Also,
A set of frequently used addresses may be fixedly stored in the TAG 25.

First, the address generator 23 generates an address signal corresponding to data required by the CPU 24. The comparator 26 includes a plurality of bits (two bits in the example shown in FIG. 11) corresponding to the block division of the 10-bit row address signal RA and the column address signal CA of the 20-bit address signal, and the address held in the TAG 25. Compare with set. If they match, a cache hit has occurred, and the comparator 26 generates a high-level cache hit signal CH and a way address signal WA of the hit block.
The state machine 27 receives the cache hit signal CH
, The column address strobe signal / CAS is toggled while the row address strobe signal / RAS is kept at a low level. In response, the address multiplexer 22 supplies a 10-bit column address signal CA to the DRAM element 31 ( See FIG. 12). At this time, the DRAM
In the element 31, the column address signal CA is not supplied to the block decoder 13 due to the control by the cache hit signal CH as shown in FIG. Therefore,
The DRAM memory cell array 1 and the SRAM memory cell array 12 are kept separated. Then, one row of SRAM memory cells 1 corresponding to the way address signal WA
Data is read from 20 onto each bit line pair SBL and / SBL. Also, the I / O corresponding to the column address signal CA
The switch 50 is turned on by the column decoder 60. As a result, data in SRAM memory cell 120 corresponding to column address signal CA and way address signal WA is output via I / O bus I / O, bar I / O, and output buffer 9. Thus when hit, the output data to the high speed access time t _{CA C} as page mode from the SRAM memory cell 120 is obtained.

On the other hand, when the address signal generated from the address generator 23 does not match the cache address set held in the TAG 25, a cache miss has occurred, and the comparator 26 generates a high-level cache hit signal CH. do not do. In this case, the state machine 27 controls the RAS and CAS in the normal read cycle, and
Supplies the row address signal RA and the column address signal CA to the DRAM element 31 in order (see FIG. 12). In the case of such a cache miss, output data can be obtained with a low access time _tRAC , so that the state machine 27 generates a wait signal Wait and outputs
Wait 24. In the case of a cache miss, the data of the block including the memory cell accessed at that time is transferred from the bit lines BL and / BL of the DRAM memory cell array 1 via the transfer gate 110 which is turned on by the block decoder 13. Batch transfer to the block of the SRAM memory cell 120 selected by the way address signal WA. Thereby, the storage contents of the SRAM memory cell 120 in this block are rewritten. Further, a new address set is held in the TAG 25 relating to the corresponding way address signal WA of the block.

As described above, in the simple cache system using the DRAM device shown in FIG. 9, since the data of a plurality of blocks is held in the SRAM memory cell array 12 as the cache memory, the number of data entries to the TAG 25 is increased. And the cache hit rate increases.

In this embodiment, when a cache miss occurs, the DRAM memory cell array is accessed and data is simultaneously transferred to the cache memory composed of the SRAM memory cell array. However, all word lines of the SRAM memory cell array are not selected. By setting the state, this transfer can be prohibited. Similarly, in the case of a write operation to the DRAM memory cell array, it is also possible to select whether or not to transfer the data to the SRAM memory cell array.
The example shown in FIG. 11 corresponds to a four-way set associative cache system.

[0030]

However, in the above-described semiconductor memory device with a built-in simple cache memory,
The block size, which is the number of bits (the number of columns) per row in each of the blocks B1 to B4, is fixed. On the other hand, the block size at which the optimum hit rate is obtained generally differs depending on the computer system or the application program.
Therefore, in a semiconductor memory device having a fixed block size and a built-in cache memory, a high hit rate cannot be obtained depending on a computer system or an application program.

The present invention has been made to solve the above problems, and has as its object to provide a semiconductor memory device suitable for a computer system or an application program.

[0032]

Means for Solving the Problems Claim 1 according to the present invention.
The semiconductor memory device described above collectively stores a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and bit information including information of a predetermined number of memory cells among the plurality of memory cells from the memory cell array. Data transfer means for performing a transfer process for transferring data, data storage means for storing the transferred bit information, and selection means for selecting arbitrary bit information from the bit information stored in the data storage means The memory cell array, the data transfer means, the data storage means, and the selection means are integrated on the same chip, and the data
Data transfer means, the data storage means and the memory cell
An action that directs access to one of the arrays
Access control signal, the access control signal
When instructing access to the cell array, the transfer process is performed.
And a switch for executing the predetermined number in the bit information. Further, as in the semiconductor memory device according to claim 2, the memory cell array is further divided into a plurality of blocks in a unit of a plurality of columns, and further includes a block selecting means for selecting the plurality of blocks, wherein the data storage means Can be accessed at high speed, and the bit information is information on a block selected by the block selecting unit among the plurality of blocks, and the block selecting unit determines a number of blocks according to the setting of the switch unit. You may select them all at once. Further, as in the semiconductor memory device according to claim 3, the switch means includes a first wiring for transmitting a first signal indicating a first number as the predetermined number, and a second wiring as a second number as the predetermined number. A second wiring for transmitting a second signal indicating a number;
And a third wiring for determining the number indicated by the signal to the predetermined number by propagating one of the signals and the second signal, and one of the first and second wirings. And a fourth wiring for electrically connecting the third wiring. Further, as in the semiconductor memory device according to claim 4, the switch means includes a first wiring for transmitting a first signal indicating a first number as the predetermined number, and a second wiring as a second number as the predetermined number. A second wiring for transmitting a second signal indicating the number of the second wiring is electrically connected to the first wiring via a first fuse;
And a third wiring for electrically transmitting one of the first and second signals to determine the number indicated by the signal to the predetermined number. And one of the first and second fuses may be blown. Further, as in the semiconductor memory device according to the fifth aspect, the switch means may set the predetermined number in the bit information by wire bonding at the time of packaging. A semiconductor memory device according to claim 6 of the present invention, comprising: a memory cell array comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which stores information;
Receiving an address signal, first selection means for selecting a plurality of memory cells from the previous texture <br/> Moriseru array in response to the address signal, the information stored in the memory cell selected by said selecting means, respectively A predetermined number of information transmission lines that are transmitted in parallel, a plurality of information storage units provided corresponding to the predetermined number of information transmission lines, each of which stores transferred information, and any of the plurality of information storage units A second selection means for selecting the information storage unit, and a control signal which is connected to the predetermined number of information transmission lines and receives a control signal, and when the control signal indicates a first state, First
Are transferred in parallel to the corresponding information storage units, and when the control signal indicates the second state, the first number of the predetermined number of information transmission lines is transmitted. A transfer process of transferring information from a second number of information transmission lines smaller than the information transmission lines in parallel to the corresponding information storage units.
An information transfer means for performing in the same device, the information rolling
Sending means for the information storage unit and the memory cell array;
Access control to instruct access to one of them
And the access control signal is transmitted to the memory cell array.
When instructing access to a
I have.

[0033]

The invention according to any one of claims 1 to 5
The semiconductor memory device is provided with a memory cell array by a switch means.
A predetermined number of bit information to be transferred from
Because it can be set, change the predetermined number according to the application.
Data can be read out from the data storage
Can be increased, and the predetermined number can be reduced.
And to suppress the increase in the amount of current due to the propagation of bit information
Can be. Further, in claim 6, the control signal is the first signal.
Memory state depending on whether the state is the second state or the second state.
The bit width of the information transferred in parallel from the
Switch between a first number and a smaller second number
Computer system or application
Information from the information storage unit according to the application program
You can select a bit width that will increase the probability of reading,
Information transferred in parallel from a memory cell to an information storage unit
Power consumption required for transfer by reducing the bit width of
Can be small, computer system or application
To obtain the optimal semiconductor memory device according to the application program.
Can be.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device with a built-in cache memory according to one embodiment of the present invention. As shown in the figure, the overall configuration is almost the same as that of the conventional example shown in FIG. 9, and the insides of the block decoder 13 'and the column decoder section 6' are different. The memory cell array 1 is divided into H (= 2 ⁽ⁿ⁻²⁾ ) or H / 2. The basic configuration and operation are the same as those of the conventional example shown in FIGS.

FIG. 2 shows the internal configuration of the column decoder section 6 'and the block decoder 13' in FIG. As shown in the drawing, the block decoder 13 'column signal CA ₃ to CA _n or takes in the inverted signal, A
And decoded by ND gate logic circuit group consisting of (G1, G2, G4, G5 only shown), column signal CA ₃ to CA
Connect the decoded result of _{n to} the input A of the switch 16,
The decoding result of the column signals CA _{4 to} CA _n is connected to the input section B of the switch 16.

The switch 16 selects one of the input unit A and the input unit B according to a selection method described later, and outputs the output to A.
The ND gate (only G3 and G6 are shown) is connected as one input, and the AND gate is connected to the cache hit signal C.
H receives the inverted cache hit signal / CH obtained via the inverter as the other input. The output of the AND gate (C and D in FIG. 2) becomes the output of the block decoder 13 ' (hereinafter, referred to as "block decoder output").
One block decoder output is transferred to transfer gate 1
1 are commonly provided to the eight transfer gates 110.

The column decoder section 6 'column signal CA ₃ to CA _n
And the column signals CA _{2 to} CA ₀ or the inverted signals thereof are represented by A
The result is taken into the ND gate 42 and the result is transmitted to the I / O switch unit 5.

When the switch 16 selects the input section A in such a configuration, the block decoder outputs the column signal CA.
Based on the result of decoding ₃ to CA _n, and one block decoder output only H level. Will be described with to FIG. 2 as an example, when the column signal CA ₃ to CA _n is "H", the output C only H level of the AND gate G3. Therefore, at the time of a cache miss, 8-bit data selected by one H-level block decoder output is transferred between the memory cell array 1 and the SRAM memory cell array 12, so that when the switch 16 selects the input section A, The block size of the memory cell array 1 is 8 bits (the number of blocks H).

On the other hand, when the switch 16 selects the input section B, the outputs of the two block decoders go high based on the decoding results of the column signals CA _{4 to} CA _n . To explain by taking FIG. 2 as an example, the column signal CA ₄
If to CA _n is "H", the column signal CA ₃ "H",
Regardless of "L", the output C of the AND gates G3 and G6
And D become “H”. Therefore, at the time of a cache miss, the memory cell array 1, the SRAM memory cell array 12
Since the data transfer of 16 (= 8 × 2) bits selected by the two H-level block decoder outputs is performed between the two, the block size of the memory cell array 1 when the switch 16 selects the input section B is reduced. This is 16 bits (the number of blocks H / 2).

FIG. 3 is an explanatory diagram showing a specific example of the switch 16. As shown in FIG. 1A, the electrical connection between the aluminum wiring layer 51 (input section A) or the aluminum wiring layer 52 (input section B) and the aluminum wiring layer 53 (output OUT) is established. Aluminum wiring layer 54 on a layer different from 53
(Electrical connection between the aluminum wiring layers 51 and 53) and 5
5 (for electrical connection between the aluminum wiring layers 52 and 53). That is, the aluminum wiring layer 5
By selectively using the formation mask of No. 4 and the formation mask of the aluminum wiring layer 55, the input unit A and the input unit B are selected during the masking process.

Further, as shown in FIG.
The input unit A and the input unit B may be selected by blowing one of the fuses 6 and 57.

Further, as shown in FIG. 4A, the P-channel transistor 63 and the N-channel transistor 66 are both turned off or on based on H and L of the selection signal SE, so that the input portions A and B are turned off. One of them can be selected as the output signal OUT. FIG.
In (a), 61 and 62 are N-channel transistors,
64 and 65 are resistors, and 67 is an inverter. The selection signal SE is created from a new external signal. Alternatively, it may be determined by a wire bonding method at the time of packaging the chip.

[0043] Further, the circuit shown in FIG. 4 (b), the block decoder 13 'is provided in front of, on the basis of the selection signal SE, the column signal CA ₃ and as the block decoder 13 and the inverted signal' and the column decoder unit or transmitted to the 6 ', by choosing whether to forcibly H level column signals CA ₃ and the inverted signal, while fixing the switch 16 to the input section a (that is, without providing a switch 16 Good), the block size can be selected from 8 bits and 16 bits.

As described above, the block size changing means such as the switch 16 is provided in the block decoder 13 '.
Since the block size can be changed by the predetermined selection means, the block size can be selected according to the computer system or the application program, and the hit rate can be improved.
That is, a computer system or application
If the program requires high-speed operation first,
Externally read from the SRAM memory cell array 12.
Set to a size that increases the hit rate, which is the probability of being hit
do it. However, computer systems or apps
Application programs demand low power consumption first
In this case, reducing the block size
It is also possible to suppress an increase in the amount of current due to propagation. Toes
The smaller the block size, the higher the hit rate
Computer system or application program
When using in a system, reduce the block size.
Although the cut rate is high and the current consumption is small,
Computer systems that increase the hit rate
For use in systems or application programs
Reduces the hit rate by reducing the block size
However, current consumption is reduced and block size is increased.
By doing so, the hit rate is high, but the current consumption increases.
Your choice depends on the computer system or app you use.
Depending on what the application program requests first.
Computer system or application.
Half with a block size suitable for the application program
A conductor device can be obtained.

In the above description, the block size is switched between 8 bits and 16 bits. However, the block size is not limited to this.
Obviously, the switching can be performed in the same manner even when the number of types is more than one. In the present embodiment, the cache memory
The storage semiconductor memory device has been described as an example, but is not limited thereto.
It consists of multiple memory cells arranged in multiple rows and multiple columns.
A memory cell array for storing the bit information.
Data storage means, the memory cell array and
The data storage means is integrated on the same chip,
Data transfer between the memory cell array and the data storage means
The present invention is applied to all semiconductor memory devices configured
can do.

It is clear that the configuration of the decoders 6 'and 13' is not limited to this example.

[0047]

According to any one of claims 1 to 5,
In the semiconductor memory device of the present invention, the memory cell is
Of bit information transferred from the data array to the data storage means
Because constants can be set, data is
The probability of being read out by the
It is also possible to suppress an increase in the amount of current caused by carrying. In addition,
In claim 6, the control signal is set to the first state or the second state.
From the memory cell to the information storage
The bit width of information transferred in parallel is determined by the first number and
Information that can also be switched between a small second number
Since it has transfer means, it can
Is the optimal semiconductor memory according to the application program.
You can get a storage device.

[0048]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device with a built-in cache memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a block decoder and a column decoder in the semiconductor memory device with a built-in cache memory of FIG. 1;

FIG. 3 is an explanatory diagram showing a specific example of a switch in a block decoder.

FIG. 4 is an explanatory diagram showing a specific example of switches and the like in a block decoder.

FIG. 5 is a block diagram showing a configuration of a conventional DRAM device.

FIG. 6 is a waveform diagram showing a high-speed access function of a conventional DRAM device.

FIG. 7 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG. 5;

FIG. 8 is a waveform chart showing an operation of the simple cache system of FIG. 7;

FIG. 9 is a block diagram showing a configuration of a DRAM device with a built-in cache memory.

FIG. 10 is a block diagram showing a configuration of a part of the DRAM device of FIG. 9 in detail;

FIG. 11 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG. 9;

FIG. 12 is a waveform chart showing an operation of the simple cache system of FIG. 11;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 word driver 3 row decoder section 4 sense amplifier section 5 I / O switch section 6 'column decoder section 7 row address buffer 8 column address buffer 9 output buffer 10 input buffer 11 transfer gate section 12 SRAM memory cell array 13' block Decoder 14 Way decoder 15 Way address buffer 16 Switch

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshio Matsuda 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation, within SSI Research Institute (56) References JP-A-63-69093 (JP, A JP-A-62-214585 (JP, A) JP-A-1-124193 (JP, A) JP-A-1-159891 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (6)

(57) [Claims] A plurality of menus arranged in a plurality of rows and a plurality of columns;
A memory cell array comprising a memory cell; and
Bit information consisting of information of a predetermined number of memory cells
TransferExecute the transfer processData transfer means, and data storage means for storing the transferred bit information
Among the bit information stored in the data storage means.
Selecting means for selecting arbitrary bit information, wherein the memory cell array, the data transfer means, and the data
Data storage means and the selection means are integrated on the same chip.
AndThe data transfer means includes: the data storage means;
Access to one of the memory cell arrays
Receiving an instructing access control signal,
Instructs access to the memory cell array,
Execute the transfer process,  A switch for setting the predetermined number in the bit information
A semiconductor storage device, further comprising means. Wherein said memory cell array is divided into a plurality of blocks of multiple column unit, the plurality of blocks further comprising a block selection means selects to order, the data storage means is accessible at a high speed The bit information is information of a block selected by the block selecting unit out of the plurality of blocks,
The block selecting means is responsive to the setting of the switch means.
2. The semiconductor memory device according to claim 1, wherein the selected number of blocks are selected at a time . 3. The switch means transmits a first signal indicating a first number as the predetermined number.
And a second signal instructing a second number as the predetermined number.
A second wiring to be transmitted and a number indicated by a signal to be propagated among the first and second numbers.
And the third wiring, which determines the number of the first and second wirings, and one of the first and second wirings and the third wiring.
3. The semiconductor memory device according to claim 1 , further comprising: a fourth wiring electrically connecting the wiring . 4. The switch means propagates a first signal indicating a first number as the predetermined number.
And a second signal instructing a second number as the predetermined number.
Electrically connected to the second wiring via the first fuse and the first wiring.
And electrically connected via the second wiring and the second fuse.
And the signal propagating out of the first and second numbers
And third wiring for determining the number designated by the above to the predetermined number.
For example, one fuse of said first and second fuses Bed
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is row-locked . 5. The packaging device according to claim 1, wherein :
The bit information by wire bonding
3. The method according to claim 1, wherein the predetermined number is set.
Semiconductor storage device. 6. A memory cell comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which stores information.
Ruarei, information receives the address signals, first selection means for selecting a plurality of memory cells from the previous texture <br/> Moriseru array in response to the address signal, which is stored in the memory cells selected by said selection means A predetermined number of information transmission lines for transmitting the information in parallel, a plurality of information storage units provided corresponding to the predetermined number of information transmission lines, each of which stores transferred information, Second selection means for selecting an arbitrary information storage unit, and a control signal connected to the predetermined number of information transmission lines and receiving a control signal, and when the control signal indicates a first state, the predetermined number of information transmission lines And transferring the information from the first number of the information transmission lines to the corresponding information storage units in parallel, and when the control signal indicates the second state, among the predetermined number of the information transmission lines, The first number Comprises a information <br/> paper transfer means for performing a transfer process of transferring the information from the even smaller second number of information transmission line in parallel to the information storage unit corresponding respectively in the same device, the information transfer means Is the information storage unit and the memory cell.
That instructs access to one of the
Access control signal, and the access control signal
When instructing access to the recell array, the transfer processing
Semiconductor storage device that executes