JP2860112B2 - Apparatus and method for transmitting test data for integrated circuit and device test circuit for integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a method for inspecting an integrated circuit (IC) alone.
The present invention relates to an integrated circuit test data transmitting apparatus and method, and a device test circuit for an integrated circuit.

(Prior art) IC device test is generated by test data
When the internal signal of the IC is read out to an external terminal, or when a ROM is provided, the contents of the ROM are displayed.
In this case, since a test is performed for each circuit block, there are a plurality of test modes. The test mode is determined by obtaining a test mode signal according to the input test data. The test mode signal enables testing of a predetermined circuit block.

FIG. 13 shows a conventional device test circuit when there are seven test modes. The IC under test has, as test terminals, a terminal P ₃₁ to which test data composed of a test mode identification code is introduced, a terminal P ₃₂ to which a test clear signal for test termination is introduced, and a terminal P to which a test clock signal is introduced. ₃₃ . The identification code register 101 for inputting test data serially inputs the test data according to the test clock and outputs the test data in parallel. This output is decoded by the test mode signal extraction circuit 102,
The test mode signal extraction circuit 102 derives test mode signals 1 to 7 for testing respective circuit blocks (here, 1 to 3 are shown).

In this case, the test mode signal 1 is output from the circuit block (RO
M) The output of 103 is supplied to an AND circuit 104 which gates the output. Thus, when the signal 1 is a logic "1", the output from the circuit block 103 are read out to the terminal P _34. The test mode signal 2 tests the circuit blocks 106 and 107. A signal selector 105 selects the output of the circuit blocks 106 and 107, and switches the signal to be selected by the test mode signal 2. Then, when the test mode signal 2 is logic "1", the output of the circuit block 107 via the signal selector 105 is read out to the terminal P _35. When the signal 2 is logic “0”, the normal mode is set, and a normal output from the circuit block 106 is led out to the terminal P ₃₅ via the signal selector 105. In addition, to the above-mentioned normal mode,
Switching is performed by setting all the contents of the identification code register 101 to logic “0” by the test clear signal.

In the device test circuit, each circuit block enters the test mode in response to one test mode signal becoming logic "1" for one test mode. The identification code register 101 has a 3-bit configuration by setting seven test modes.

However, the device test circuit as shown in FIG. 13, the internal information of the IC, for example, the contents of the ROM even if the do not leak to third parties, easily contents of ROM if found test terminals P ₃₁ to P ₃₃ You can know.

Figure 14 shows a timing chart of the test mode signal obtained as a signal to be supplied to the terminal P ₃₁ ~P _33, a test clear signal, b is the test clock signal, c is the test data
1, d indicates a test mode signal 1, e indicates test data 2, f indicates a test mode signal 2, and g indicates a general form of test data. In test mode 1, test data 1 becomes logic "1" at the third clock, so that the content of register 101 becomes "100" from the input side, and this identification code is decoded to obtain test mode signal 1. . In the test mode 2, the test data 2 becomes logic "0" at the first and third clocks, and becomes logic "1" at the second clock.
The identification code "010" is decoded and the test mode signal 2
Is obtained.

According to the timing chart, there are eight types of codes that can be taken by the test data, and seven types are used as identification codes, so that it does not take much time to try all the cases and set the target test mode. .

Generally, when the number of bits of the mode identification code is n (integer), the number of test modes that can be set is a maximum (2 ⁿ −1).
(1 for normal mode is subtracted from 2n). Conversely, assuming that the number of necessary setting modes is T _N , the number n of bits of the mode identification code (equal to the bit length of the register 101) is reduced to reduce the scale of the test circuit. represents the smallest integer not less than x, and so on).

(Problems to be Solved by the Invention) As described above, in the conventional device test circuit, when the number of test modes is T _N , the bit length of the identification code is set to T _N to reduce the circuit scale. Because it was set to the smallest bit length that could be represented, it was easy to enter test mode. This has the disadvantage that if the internal information of the IC must not be leaked to a third party, it can easily enter the test mode.

An object of the present invention is to solve the above technical problem and to provide a device test circuit with high confidentiality of internal information.

[Configuration of the Invention] (Means for Solving the Problems) A device test circuit for an integrated circuit according to the present invention includes a random number initial value code including an identification code for identifying a test mode, and a random number initial value code following the random number initial value code. Data input means to which test data consisting of the same encryption key code as a naturally occurring random number code based on the input data, an initial value code register in which a random number initial value code including the identification code is set,
A save register that temporarily holds only the identification code from the initial value code register, an identification code register that stores the identification code from the save register, and a random number initial value code from the initial value code register. A random number generation circuit for generating a random number is compared with a random number from the random number generation circuit and an encryption key code from the data input means, and the content of the save register is set in the identification code register based on the comparison result. And a means for outputting a plurality of test mode signals in response to a signal from the identification code register. The method comprises transmitting test data including a code identifying a test mode of a receiving integrated circuit when input to a receiving device, the test data comprising: Has a random number initial value code including a code for identifying the test mode, and a cryptographic key code identical to a random number code naturally generated based on the random number initial value code. An integrated circuit test data transmitting apparatus for transmitting test data including a code for identifying a test mode of an integrated circuit on a receiving side when input to a receiving side, the test data transmitting apparatus for an integrated circuit identifying the test mode. Random number initial value code generation means for generating a random number initial value code including a code to be executed, and encryption key code generation means for generating the same encryption key code as a naturally generated random number code based on the random number initial value code. It is characterized by the following.

(Operation) According to such a configuration, in the first aspect, the number of digital values that can be set in the identification code register becomes larger than the number of test modes, and the number of redundant bits increases, and the probability of finding the test mode identification code increases. Become smaller.

According to the second invention, the probability of entering the test mode is smaller than that of the case where the initial value code register has one or more redundant bits as in the first invention. It will be a few minutes smaller.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of a device test circuit for an integrated circuit according to the present invention, and FIG. 2 is a block diagram showing the embodiment of FIG. 1 in detail.

FIG. 1 shows the configurations of the identification code register 11 and the test mode signal extraction circuit 12. The identification code register 11 is an 8-bit shift register described in detail in FIG.
Test data from the terminal P _1, the test clear signal from the terminal P ₂ and, respectively input a test clock signal from the terminal P _3. Test data, the test clock signal is sequentially shifted from the input-side bit D ₈ to the output side bits D _1.
Test clear signal, the logic of the contents of the bits D ₈ ~D ₁ "0"
Signal.

The test mode signal extraction circuit 12 includes an identification code register 11
Is a circuit that performs a logical operation on each bit output from the above, and in this case, seven test mode signals are extracted. To elaborate,
The test mode signal extraction circuit 12 includes seven AND circuits corresponding to the number of test mode signals and a predetermined number of inverters. The AND circuit 121 that forms the test mode signal 1 outputs each bit output of D ₈ , D ₇ , D ₅ , D ₃ , D ₂ , and D ₁ , D ₆ via the inverter 125, and D ₄ via the inverter 127. Bit output is input. Further, the AND circuit 122 for forming the test mode signal 2 outputs each bit output of D ₇ , D ₆ , D ₄ , D ₃ , a D _8- bit output via the inverter 124,
A D ₅ bit output via the inverter 26, a D ₂ bit output via the inverter 128, and a D ₁ bit output via the inverter 129 are input. Reference numeral 123 denotes an AND circuit for forming the test mode signal 7. The test mode signals 1, 2 to 7 are
Are respectively led to the terminals P _11, P ₁₂ ~P _13, it is supplied to a gate circuit or signal selector circuit block (not shown).

FIG. 2 shows a specific circuit of the identification code register 11. 111
.. 113 are D flip-flops whose outputs are the inputs of the next stage. The contents of each flip-flop are moved with the test clock signal as a shift pulse.

 This embodiment is configured as described above.

According to such a configuration, the bit length of the identification code register 11 is longer than the bit length capable of expressing the number of test modes, so that the bit length of the test data can be increased. For this reason, the number of possible test data increases,
Reduce the probability of accidentally entering test mode.

FIG. 3 is a timing chart showing an operation based on the embodiment of FIG. 1, wherein a indicates a test clear signal, b indicates a test clock signal, c indicates test data 1, and d indicates test data 1. Test mode signal 1 obtained by
E indicates test data 2 and f indicates a test mode signal 2 formed by the test data 2.
g is a general form of test data according to the present embodiment.

To the test mode, the negative pulse T ₁ by the test clear signal a is the content of the identification register 11 becomes all "0". At this time, the mode is the normal mode.

When signal D ₈ to D ₁ = "11010111 shown in c as test data] (test data 1) for inputting the identification code register 11, a test clock 8th, the signal is parallel input to the test mode signal extraction circuit 12 This allows
A signal of all "1" is input to each input terminal of the AND circuit 121, and a test mode signal 1 which changes to logic "1" at the eighth clock is output from the AND circuit 121 as shown in d. In the case of test mode 2, "01101100" shown in e
(Test data 2) is input to the identification code register 11. As a result, the inputs of the AND circuit 122 are all “1”, and the AND circuit 122 outputs the test mode signal 2 having the logic “1” at the eighth clock.

As described above, in this embodiment, the bit length of the identification code register 11 is 8 bits, and the bit length of the test data can be made longer than 3 bits that can represent the number of 7 test modes. Therefore, the greater the number of cases that may take the test data, the probability of entering the test mode by chance, compared to conventional 7/8, the 7/2 ^8.

FIG. 4 is a conceptual diagram generally representing the embodiment of FIG. That is, the solid line portions are the identification code register 11 and the test mode signal extraction circuit 12 which are set so that the bit length and the scale are minimized in accordance with the number of test modes. In this case, the probability P _T that accidentally enters the test mode is Becomes

In the bit length and scale of the solid line, as shown by the dotted line, k
If the test mode signal extraction circuit 12 is expanded by adding bit register cells, the test mode signal extraction circuit
12 is A bit signal is input, and a test mode signal indicating one of the T _N test modes is output. This test mode signal may be in one-to-one correspondence with the test mode as in the embodiment, or a plurality of test mode signals may be active (logic "1") for one test mode. (Signs are composed of the mode signals 1 to 7).

In the case above, the probability of accidentally entering test mode is Becomes Note that k is an integer value of 1 or more, and if the denominator of the equation is rewritten in another expression, it can be said that "an integer not smaller than (log ₂ ( _TN + 1) +1").

Comparing the formulas with the formulas, it can be seen that the probability of entering the test mode in this proposal is 1/2 ^k .

 Next, another embodiment will be described.

FIG. 5 is a block diagram showing another embodiment of the device test circuit according to the present invention, and FIG. 6 is a format of test data in the embodiment of FIG.

In the Figure 5, the terminal P ₂₁ is the input terminal of the test data. Test data from the terminal P _21, as shown in FIG. 6, consists of an initial value code and the dark master key code, the initial value code contains the mode identification code. The initial value code indicates an initial value of the random number, and the encryption key code is a random number sequence generated based on the initial value code. Here, for example, a PN code configured by cyclically controlling a shift register by a predetermined logic circuit is used.

Now, the test data from the terminal P ₂₁ is held in PN initial value code register 21. The PN initial value code register 21
The initial value code 21a and the mode identification code 21b composed of any data set in the initial value code are output separately,
The initial value code 21a is supplied to the PN code generation logic 22, and the mode identification code 21b is stored in the save register 23. The PN generation code logic 22 uses the initial value code 21a as an initial value and
The code 22a is generated. This PN code 22a is the same as the encryption key code input as the test data, and is compared with the encryption key code in the test data by the encryption key comparison means 24.

The output 24a of the encryption key comparing means 24 is an identification code register 25.
Is input so that the register 25 is gate-controlled.
That is, the signal 24a is generated when the PN code from the PN code generation logic 22 matches the encryption key code in the test data.
The identification code held in the save register 23 is the identification code register
The identification code register 25 is controlled so that the identification code register 25 is transferred. The output of the identification code register 25 is input to a test mode signal extracting means 26 equivalent to the embodiment of FIG. 1, and a plurality of test mode signals are formed.

Incidentally, the identification code register 25 and the test mode signal extracting means 26 correspond to the register 11 and the circuit 12 in the embodiment of FIG.

When the encryption key code in the test data does not match the PN code from the PN code generation logic 22, the device test circuit having the above configuration
No identification code is sent to 25. Therefore, since no test mode signal is generated, it is impossible to enter the test mode.

The probability of entering the test mode in the case of the above embodiment is obtained.

Assuming that the initial PN code length is n _P and the test mode identification code length is n _T , the number of required test modes T _N is Have a relationship.

When the code length of the encryption key to be compared by the encryption key comparison means 24 is k bits, the probability of entering the test mode _PT is: Then the formula is Becomes Therefore, it can be seen that the probability of entering the test mode is 1/2 ^k , as in the case of FIG.

Next, a specific embodiment based on the embodiment of FIG. 5 will be described.

FIG. 7 is a circuit diagram showing an example of a specific configuration of the test mode circuit using the random number data.

In this specific circuit, the PN initial value code is 9 bits (of which 3 bits are also used as the test mode identification code), the encryption key code is 55 bits, and the number of test modes is 7.

Terminal P ₂₂ is the input terminal of the test data, the terminal P ₂₃ is the input terminal of the test clock signal, the test data and the test clock signal from the respective terminals are serially input to the initial value code register 31. In this case, the first and sixth and seventh bits D ₁ , D ₁ , among the initial value code composed of D _{9 to} D ₁ bits
D ₆ and D ₇ also serve as test mode identification codes.

PN code generation logic 32 is a 9-bit shift register
The first stage output bit R ₁ and the fifth output bit R _{5 of the} shift register 32 _A are constituted by 32 _A and an exclusive OR circuit 32 _B.
DOO exclusive input to the OR circuit 32 _A, has a structure for feeding back the output final stage (input side) to the output bit R _9. Register 32 _A inputs the initial value code from the initial value code register 31 in parallel by the load pulse LD ₁ from the terminal P _25. The PN code 32a, which is the output of the PN code generation logic 32, selects the _seventh output bit R7.

On the other hand, the test mode identification codes D ₉ , D _4, and D ₃ are input in parallel to a 3-bit save register 33, and the save register 33 holds the identification code by a latch pulse LP ₁ from a terminal P ₂₆ .

The encryption key comparing means 34 includes an exclusive OR circuit 34 ₁ , an OR circuit 34 ₂ ,
Register 34 _3, and an inverter 34 _5, register 34 _6. Exclusive OR circuit 34 ₁ receives the PN code 31a and test data from the 7-th output bits R7, if both inputs match logic "0", and outputs the if disagreement logic "1" . OR circuit 34 ₂ are inputs the output 34b of the output and the register 34 ₃ from the exclusive OR circuit 34 _1, and feedback the OR logic output to the register 34 _3. Such a feedback circuit is a circuit that, when a mismatch is detected even for one bit, holds the subsequent output 34b as a signal of logic "1" indicating the mismatch. The register 34 ₃ starts the comparison operation by the comparator start pulse CS from the terminal P _20, and outputs the operation at the timing of the test clock. This is because the output 34a is not output during the initial value code period.
The output 34b of the register 34 ₃ is input via the inverter 34 ₅ to register 34 _6. Register 34 ₆ takes the output 34b by the latch pulse LP ₂ applied from the terminal P _30, and supplies a latch pulse 34a to the identification code register 35.

The register 34 _6, the test clear signal from the terminal P _24, is cleared operation at the timing of test start.

Identification code register 35, the a same three-bit configuration and the retracted register 33, an identification code Q ₁ and the test mode identification code S ₁ to S _3, which is saved in the save register 33 by the output 34a of capture, the taken introducing to Q ₃ in the test mode signal extraction circuit 36. The test mode extraction circuit 36 is a logic circuit that sets the test mode signals 1 to 7 to logic "1" in one-to-one correspondence with the test mode, similarly to the circuit of FIG.

Reference numeral 37 denotes a timing signal generating circuit for generating the latch pulses LP ₁ and LP ₂ , the comparison start pulse CS, and the load pulse LD ₁ . The timing signal generation circuit 37 generates the above timing signal based on the test clear signal and the test clock signal.

The test clock signal is a clock signal of register 32 _A. In this case, a test clock signal from the terminal P ₂₃ via an inverter 38. In addition to the registers 32 _A.

The timing signal generating circuit 37 has a specific configuration shown in FIG.

In Figure 8, registers F1～F ₇ constitute a ripple counter. Count enable and disable of the ripple counter are controlled by a selector 39.
The output of the final-stage register F ₇ is one clock period held by the register F _8, a latch pulse LP _2. This register F
The selector 39 is switched by the output of ₈ . Inverter 40, the AND circuit 41, the register F _9, F ₁₀ and the NAND circuit 42
, The load pulse LD _1, and sets the generation timing of the latch pulse LP ₁ and Comparative start pulse CS.

FIG. 9 is a timing chart showing the operation of the timing signal generating circuit 37.

In Figure 9, a is the test clear signal, b is the ripple counter output, c is the test clock signal, d is the output 41a of the AND circuit 41, e output 9a of the register F _9, f is the output of the NAND gate 42 (latch pulse LP _1, comparison start pulse
CS), g is the output of the register F ₁₀ (a load pulse LD _1), h
Respectively the output 7a of the register F _7, i is the output of the register F ₈ (the latch pulse LP _2).

FIG. 10 is a circuit diagram showing an example of register 32 _A. This is because, when a negative load pulse is input, the parallel data input is taken into each register cell at the rising edge of the clock, and serial input and parallel output are performed by the clock. If the value code is loaded into register 32 _a, the same PN code 32a and the encryption key signs in the test data is output from the R ₇ bits, the output 32a
And the test data are compared on a bit-by-bit basis. Then, 55 when a mismatch by comparing all bit is not detected, then latch operation the identification code register 35 by the latch pulse 34a, reference numeral Q ₁ to Q ₃ test mode signal based on the test mode identification code from the save register 33 If a mismatch is detected even for one bit, the code signal held in the save register 33 is not supplied to the test mode signal extracting means 36. Thus, a device test circuit having a very low probability of accidentally entering the test mode is realized.

FIG. 11 is a detailed operation explanatory diagram of the device test circuit, and shows a timing chart when the test mode signal 1 is set to logic "1".

In this figure, a is the test clear signal, b is the general form of the test data, c is the test clock signal, d is the general form of the test data 1, e is from specific test data 1, f is the seventh bit D ₇ see test data, g is the load pulse LD _1, h is a latch pulse LP _1, i is the bit output S ₃ of the save register 33, j is compared start pulse CS, k register 34 ₃ output 34b, l is the PN code The output, m is the latch pulse LP ₂ , n is the latch pulse 34 a, p is the output Q ₃ of the identification register 35, and q is the test mode signal 1.

The test clear signal a turns negative at the start of the test. Subsequently, first, a 9-bit initial value code is sequentially input to the initial value code register 31. In the case of the test data 1, the first, sixth, and seventh bits of the test mode identification code are determined to be “0”, “0”, and “1”, respectively, as shown by d. Assuming that the codes D _{2 to} D ₅ , D ₈ , D ₉ = “101100”, the initial value code in the test data 1 becomes like the signal e.

When the test data as mentioned above into the initial value code register 31, the example bit output D _7, as shown in the signal f, the same signal and d is observed from the rise of the third clock. The latch to the save register 33 is a latch pulse
LP ₁ (refer to signal h) is performed at the timing of the ninth clock, so that the signal indicated by P _{15 in the} signal f is held as the signal of the bit S ₃ of the save register 33 ( See signal i). Also, at this time, the load pulse
LD ₁ (reference signal g) be turned to negative, the signal of the initial value code section is transferred from the initial value code register 31 to register 32 _A. As a result, as shown by the signal 1, the initial value code section is indefinite, and the signal indicating the PN code from the encryption key code section is R ₇
Output spontaneously.

When a predetermined data in register 32 _A is held, as shown in j, comparison start pulse starts to negative at the timing of the ninth clock. In this case the test data, since changes to the encryption key code, the exclusive OR circuit 34 _1, PN code output 32a and the encryption key codes are sequentially inputted at the timing of the test clock are compared.

Now, when the PN code output 32a and an encryption key code matches, the output of the exclusive OR 34 ₁ is a logical "0", the register 34 ₃ which latches the signal, a logic "0" Is fed back. Further, when the PN code output 32a and the encryption key codes do not match, the output of the exclusive OR 34 ₁ becomes a logic "1", the register 34 ₃ which latches the signal, a logic "1"
Is fed back. This state continues until the test clock is stopped, for example. Therefore, the signal 34b becomes the signal k
As shown in the figure, when all 55 bits match, a signal of logic "0" is output as shown by a solid line. If a mismatch is detected in the middle, a signal of logic "1" is output from the clock as shown by a dotted line. "become.

As shown in the signal m, the latch pulse LP ₂ rises at the end of the 64 th clock. At this time, the signal 34b becomes logic "0".
When it is, the signal of logic "1" via the inverter 34 ₅ is latched by the register 34 _6. As a result, as shown by the signal n, the latch pulse LP ₂ (32a) exhibits a coincidence pulse of logic “1”, and the identification code register 35 is latched.

Thus, the bit output S ₃ from the save register 33 is transferred to the identification code register 35, as shown by a signal p, the bit output Q ₃ becomes logic "1". If the bit output Q ₃ is logic "1", the test mode signal extraction circuit 36 makes the test mode signal 1 to a logical "1" (reference signal q).

The probability P _T of entering the test mode in the above embodiment is
Assuming that n _T = 3, T _N = 7, and k = 55, P _T = ^7/258 .

In order to realize the same probability in the embodiment of FIG. 1, the identification code register 11 must have a 58-bit configuration, and the test mode signal extraction circuit 12 must have a scale for performing a 58-bit arithmetic processing. On the other hand, in the embodiment of FIG. 7, the number of registers including the registers of the timing signal generation circuit 37 is only 36.

In the embodiment using the encryption key code, the entry probability can be reduced without increasing the hardware scale depending on the setting of k. The value of k can be varied by adjusting the generation timing of the latch pulse LP _2. This further complicates entry into the test mode due to the longer encryption key code.

Generally, when extremely high confidentiality is required as IC internal information, the embodiment of FIG. 5 is more advantageous in terms of hardware scale.

In the embodiment of FIG. 5 (FIG. 7), the test mode identification code length n _T in the initial value code is In this case, n _T may be increased by 1 bit (1 is an integer of 1 or more). In this case, even if the encryption key code is input as the test data, it is not always possible to enter the test mode. According to this, the probability of entering the test mode, the 1/2 ¹ times only smaller.

The embodiment of FIG. 7 may be provided as an external circuit of the IC as shown in FIG. 12A, or may be built in as shown in FIG. 12B.

[Effects of the Invention] As described above, according to the present invention, it is not possible to easily enter the test mode without complicating the circuit scale, and the confidentiality of the internal information of the IC can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a device test circuit for an integrated circuit according to the present invention, FIG. 2 is a block diagram showing the embodiment of FIG. 1 in detail, and FIG. 3 is an embodiment of FIG. FIG. 4 is a conceptual diagram summarizing the embodiment of FIG. 1, FIG. 5 is a block diagram showing a device test circuit showing another embodiment of the present invention, and FIG. FIG. 7 is a format showing test data used in the embodiment of FIG. 7, FIG. 7 is a circuit diagram showing a specific example of the embodiment of FIG. 5, FIG. 8 is a configuration diagram of a timing signal generation circuit used in the embodiment of FIG. 9 is a timing chart of the circuit of FIG. 8, FIG. 10 is a block diagram showing a parallel and serial input / parallel output type register used in the embodiment of FIG. 7, and FIG. 11 is an embodiment of FIG. FIG. 12 is a timing chart showing the operation of FIG. Aspect view, FIG. 13 is a configuration diagram showing a conventional device test circuit, FIG. 14 is a timing chart outlining the operation of the circuit of Figure 13. 11: Identification code register, 12: Test mode signal extraction circuit, 21 (31): Initial value code register, 22 (32):
PN signal generation rosic, 23 (33) ... Save register, 24
(34) ... encryption key comparison means, 22a ... PN code output, 34a ...
... Latch pulse (comparison result).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 H01L 21/66 H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] 1. A test data consisting of a random number initial value code including an identification code for identifying a test mode, and a test key consisting of the same encryption key code as a random number code naturally generated based on the random number initial value code. Data input means, an initial value code register in which a random number initial value code including the identification code is set, a save register temporarily holding only the identification code from the initial value code register, An identification code register that stores an identification code; a random number generation circuit that generates a random number according to the random number initial value code from the initial value code register; a random number from the random number generation circuit; and an encryption key from the data input unit. And an encryption key for determining whether to set the contents of the save register in the identification code register based on the comparison result. Compare means and the device test circuit of the integrated circuit, characterized in that it comprises a means for outputting a plurality of test mode signals in response to a signal from the identification code register. 2. A test data including a code for identifying a test mode of an integrated circuit on a receiving side when input to a receiving side, wherein the test data includes a random number initial value code including a code for identifying the test mode. And a cryptographic key code identical to a random number code naturally generated based on the random number initial value code. 3. An integrated circuit test data transmitting apparatus for transmitting test data including a code for identifying a test mode of an integrated circuit on a receiving side when input to a receiving side, comprising a code for identifying the test mode. A random number initial value code generating means for generating a random number initial value code; and a cryptographic key code generating means for generating the same cryptographic key code as a naturally occurring random number code based on the random number initial value code. Test data transmission device for integrated circuits.