JP2860194B2 - MSK modulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MSK modulator, and more particularly, to an MSK modulator having an improved modulation process for parallel MSK modulation.
It relates to a K modulator. 2. Description of the Related Art As shown in FIG. 7, an MSK modulation apparatus converts a bit stream into parallel data by a serial / parallel converter 71 to obtain a dI signal as a baseband signal, A dQ signal as a baseband signal is obtained through a / 2 data delay circuit 72. Multiplication circuit 73a,
73b multiplies each of the dI signal and the dQ signal by COS (πt / 2Tb) and SIN (πt / 2Tb) to shape the waveform. Here, Tb is a predetermined parameter (symbol rate). Thus, the multiplication circuit 73a
The SI signal and the SQ signal obtained by
4a and 74b, and the SI signal and COS (ω ₀ t + θ
₀ ) signal is obtained by converting the SQ signal and the COS (ω ₀ t + θ ₀ ) signal to −π
The signal is multiplied by a signal shifted by -π / 2 in a / 2 phase shifter 75.
The addition circuit 76 adds the output signals from the multiplication circuits 74a and 74b to obtain a modulated signal. In order to digitize the configuration of the MSK modulator, it is relatively easy to digitize a baseband signal and a clock multiplication unit, but there are the following problems. Occurs. In other words, since the multiplication result by the multiplication unit includes a logically infinite frequency component, the aliasing of the sampling clock becomes a problem. There must be. Also, a large-scale filter having good characteristics is required for attenuating a harmonic of n times the sampling clock generated by digitization. Further, due to the partial digitization, for example, in the above-mentioned baseband signal and clock multiplication unit, the phase relationship between the SI signal and the SQ signal on the analog signal after the D / A conversion is changed by half the data on the input data. Even if the signal is advanced, a deviation occurs in the relationship due to factors such as variations in the analog circuit, so that the deviation must be adjusted. SUMMARY OF THE INVENTION An object of the present invention is to provide an MSK modulator which digitizes a multiplication circuit and obtains simple and stable characteristics. [0005] In order to solve the above-mentioned problems, an MSK modulator according to the present invention digitally multiplies a digital baseband signal and a clock signal by M.
In an MSK modulation device that performs SK modulation, a digital multiplication circuit that multiplies a clock by a dI signal and a dQ signal, which are digital baseband signals, a D / A converter that converts an output of the multiplication circuit into an analog signal, A
A low-order low-pass filter that removes an unnecessary part of the output of the converter, an analog multiplier that multiplies the output of the low-pass filter, an addition circuit that adds the SI signal and the SQ signal that are the outputs of the analog multiplier, The digital multiplying circuit has a band-pass filter that allows only the main lobe of the MSK modulation, which is the output of the adding circuit, to pass the result of multiplying the digital baseband signal and the clock by n times the symbol rate of the digital baseband signal. A memory for sampling at a sampling frequency, dividing one symbol into n and storing the n symbols, a latch for reading and multiplexing the memory contents from the RAM, and outputting a plurality of phase sampling points to be written to the RAM; Includes a phase setting unit that can set the phase difference between the SI signal and the SQ signal to be π / 2 And OM, is configured to include a timing generation circuit for transferring instruction data is a phase sampling point to the RAM from the ROM. According to the present invention, the result of digital multiplication of a digital baseband signal and a clock signal is stored in memories having different access times, and a digital filter is used to remove aliasing generated during multiplication, and is performed by a bandpass filter. Only the main lobe of the MSK modulated wave is allowed to pass. That is, aliasing that occurs at the time of multiplication of the digital baseband signal and the clock signal is removed, the result is stored in the ROM as the multiplication result, and only necessary data is transferred to the RAM and converted to analog. This signal is passed through a low-pass filter, multiplied by a carrier, added to an equivalent signal at the other side of orthogonality, and
A K-modulated wave is obtained, and a target signal is obtained by a band-pass filter that passes only the main lobe. Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an MSK modulator according to the present invention. The baseband signals dI and dQ are input to digital multiplication circuits 1a and 1b, respectively. The digital multiplication circuits 1a and 1b are digital components that generate a multiplication result of the baseband signal and the clock signal based on the baseband signal dI or dQ according to the master clock. The data multiplied by the digital multiplication circuits 1a and 1b are converted by the D / A converter 2
The signals are converted into analog signals by a and 2b. This analog signal is filtered by the low-pass filters 3a and 3b and supplied to the analog multiplier circuits 4a and 4b as an SI signal and an SQ signal. In the analog multiplying circuit 4a, the SI signal and the carrier signal A · COS (ω ₀ t + θ)
₀ ), and the analog multiplication circuit 4b performs analog multiplication of the SQ signal and the signal obtained by shifting the carrier signal by -π / 2 in the -π / 2 phase shifter 5. Analog multiplication circuit 4
The output signals from a and 4b are added by an adder circuit 6. This added signal is amplified by the amplifier 7 and then passes through the band-pass filter 8 to obtain a final MSK modulated wave. FIG. 2 is a block diagram showing the configuration of the digital multiplying circuit 1a or 1b in the embodiment of FIG. The baseband signal dI or dQ passes through a serial / parallel converter (SI / PO) 111 and is taken into a selector 112. The selector 112 includes a timing generation circuit 115
And a selector for switching an address bus to be supplied to the RAMs 116 to 119 based on the signal from the serial interface. The parallel output of the serial-parallel converter 111 is always selected during the multiplication process. RAMs 116 and 117 in which the multiplication results are stored,
The output data of 118 and 119 are latch 1
20, 121, 122 and 123, the output control terminals of the respective latches are controlled and sequentially multiplexed by the latches 124, and the D / A converter 2a at the next stage is latched.
Or 2b. The ROM 113 receives the address signal A (upper bit) from the phase setting unit 114 and receives the address signal A (lower bit) supplied from the timing generation circuit 115 operated by the master clock (CK). In addition, the timing generation circuit 115
RAM 116 that performs a write operation based on an instruction from
To 119 are transmitted. At this time, the selector 11
2 selects the address bus from the timing generation circuit 115. Now, referring to FIG.
In the initial state 9, sampling data is written based on the address data of the timing generation circuit 115 with data of an appropriate initial phase set by the phase setting unit 114 in the initial state.
The reason why four RAMs 116 to 119 are used is that the number of sampling points per data is set to four. The written data is a so-called FIR
Since the content is band-limited by a digital filter of the form, a data string (for several data) of a span having every bit (bit) of the input baseband signal dI is
The data is given to the RAM as data of the RAM address as shown in the timing chart of FIG. According to the given address data, as shown in FIG. 4, sample data of the middle waveform of the data series is output from the RAM. Since the multiplication result SI has two waveform states depending on the initial state as shown in the figure, the RAM stores the control and data based on the control. The output data is latched by a latch circuit with the same pulse, and the output control signal of the latch is switched at a speed four times faster than the latch pulse, and is sequentially latched at 124 and multiplexed. Therefore, 11
In the 4z RAMs 6 to 119, the phase setting unit 114 can set the phase at a resolution of 2 ^m in an area obtained by dividing one data resulting from the multiplication as shown in FIG. When changing the phase determined in the initial state at power-on or when further shifting the phase, desired data is read from the ROM and written into the RAM each time. This corresponds to the waveform shaping unit 2 of the parallel MSK modulation system of FIG.
As can be seen from the two clock equations, the SI signal and the SQ signal are orthogonal, so even if the configuration shown in FIG.
A phase shift occurs between the I signal and the SQ signal, and it is necessary to perform an operation of setting a phase so as to adjust the phase shift. [0011] As shown in FIG.
The waveform portion composed of the sampling data A, B, and C, the phase of which is set at 4, has a phase resolution of 2 ^m . Where 2
^m is １ ／ of the resolution 2 ⁿ of the D / A converter. That is, 2 ^m = 2 ⁿ / 8. In FIG. 1, since the unnecessary frequency components generated during the multiplication are removed by the digital filter in the multiplication result calculated by the digital multiplication circuit, there is no aliasing from the sampling frequency fs. But,
Since a harmonic band is present at n times fs, an analog filter having a pass band up to fs / 2 is necessary to remove a frequency component higher than the band existing usually around fs. Since the bandpass filter 8 that passes only the main lobe of the MSK modulated wave is incorporated in the addition result after the multiplication with the carrier of the signal, the combined characteristics of the two types of filters can be used as shown in FIG.
In order to eliminate aliasing from the double carrier, these filters incorporate low order, moderately attenuating filters. In the above embodiment, the digital dI,
The multiplication process of the waveform shaping circuit that multiplies the clock by the baseband signal whose symbol rate of the dQ signal is Tb and the clock is digitized, and the multiplication result previously stored in the storage element is read and read according to the baseband signal. A digital multiplying circuit for converting a digital signal into an analog signal. The storage element is realized by a combination of a ROM and a RAM having different access times and functions. Further, the sampling frequency of the sampling data is set to four times the symbol rate, and the digital data is processed by a digital filter so that no aliasing occurs in the sampling data when the baseband signal is multiplied by the clock.
Further, in order to adjust the phase of SI and SQ immediately after waveform shaping so that SQ is delayed by 1/2 data with respect to SI,
The ROM stored in advance stores all information corresponding to the phase, and transfers the data of each phase to the RAM as needed. Further, the output after the D / A converter includes unnecessary harmonics having a band centered on the n-times sampling frequency, and based on a double carrier frequency generated by multiplication with a carrier in a subsequent circuit. Since the harmonics are folded back, a low-pass filter is inserted after the DA converter, but a band-pass filter that passes only the main lobe of the MSK modulated wave is used at the end of outputting the modulated wave. A filter having a low order of characteristics is used. As described above, the M according to the present invention is
The SK modulator does not need to adjust the phase between the baseband signal and the clock. Further, since the phase can be set in the digital multiplication circuit, the orthogonality between the SI signal and the SQ signal can be adjusted, and the operation is stabilized without using the delay element used for adjustment in the analog circuit. Further, since the data corresponding to the phase is stored in the ROM in advance and only necessary data is transferred to the RAM, it is easy to apply to a relatively high-speed operation even if the data amount becomes enormous. Furthermore, the disadvantage of digitalization is the design of the filter after the DA converter. This time, the filter is a simple low-order filter utilizing the effect of combination with a band-pass filter that passes only the main lobe of the MSK modulated wave. It will be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic configuration block diagram showing one embodiment of an MSK modulator according to the present invention. FIG. 2 is a block diagram illustrating a configuration example of a digital multiplication circuit in the embodiment of FIG. FIG. 3 is a waveform timing chart for explaining an operation in the embodiment of FIG. 2; FIG. 4 is a waveform timing chart for explaining an operation in the embodiment of FIG. 2; FIG. 5 is a waveform timing chart for explaining an operation in the embodiment of FIG. 2; FIG. 6 is a waveform timing chart for explaining an operation in the embodiment of FIG. 2; FIG. 7 is a configuration block diagram of a normal MSK modulator. [Description of Signs] 1a, 1b Digital multiplying circuits 2a, 2b D / A converters 3a, 3b Low-pass filters 4a, 4b, 73a, 73b, 74a, 74b
Analog multiplication circuit 5,75 -π / 2 phase shifter 6,76
Adder circuit 7 Amplifier 8
Bandpass filters 71, 111 Serial-parallel converter 72
1/2 data delay circuit 112 selector 113
ROM 114 Phase setting unit 115
Timing generation circuits 116 to 119 RAMs 120 to 124
latch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 27/12

Claims (1)

(57) Claims: In an MSK modulator for digitally multiplying a digital baseband signal and a clock signal to perform MSK modulation, a digital device that multiplies a clock by a dI signal and a dQ signal, which are digital baseband signals, respectively. A multiplying circuit, a D / A converter that converts an output of the multiplying circuit into an analog signal, a low-order low-pass filter that removes an unnecessary portion of an output of the D / A converter, and an analog that multiplies an output of the low-pass filter. A multiplier, an addition circuit for adding the SI signal and the SQ signal output from the analog multiplier, and a band-pass filter that passes only a main lobe of MSK modulation output from the addition circuit; The circuit multiplies the digital baseband signal by the clock and calculates the symbol level of the digital baseband signal. Sampled at n times the sampling frequency of over preparative phase sampling for writing one symbol and n number of RAM is divided into n memory, a latch and outputting the read multiple memory contents from RAM, said RAM
Memory points , and the phase difference between the SI signal and the SQ signal.
Including a phase setting unit that can be set to be π / 2
M and a phase sampling point from the ROM to the RAM.
A timing generating circuit for instructing transfer of data to be transmitted .