JP2861275B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit configuration and a circuit for facilitating an internal function test of a data processing device.

[Conventional technology]

Conventionally, when a data processing device breaks down in a field or in an operation inspection after assembly in a factory, a function inspection program is often used. However, if the failure involves a basic function, even the function test program may not work. In such a case, the device was once disassembled and a failure analysis was performed using a CPU emulator or the like.

[Problems to be solved by the invention]

However, this requires disassembly of the device and requires an expensive emulator. It is not easy especially in the field. The object of the present invention is to insert an inspection board as an option board into a part of the equipment,
Inspection of complex systems including the CPU from outside to improve work efficiency.

[Means for solving the problem]

In the data processing device of the present invention, the CPU is connected to the controller of the input / output means, the low-speed memory, the internal controller means such as the interrupt controller, and the like via the I / O bus. Main memory is connected to
The I / O bus can also be accessed via the memory bus, and the expansion slot is provided for all or one of the I / O buses.
Part, having a function test signal in the expansion slot,
Insert a function test board into the expansion slot
By asserting (validating) the signal, the CPU is stopped and the bus controller is directly actuated to acquire the right to access the I / O bus, and the controller of the input / output means connected to the I / O bus and the low-speed memory are used. It is characterized by performing a function test of internal control means such as an interrupt controller and a main memory connected to a memory bus.

[Action]

According to the above configuration of the present invention, the function test board inserted into the expansion slot stops the CPU of the main body by asserting the EMU signal, and directly acts on the bus controller to obtain the access right of the I / O bus. I do. The CPU or board inspection controller circuit on the function inspection board connects the I / O bus and the memory bus with circuits such as the I / O controller and low-speed memory connected to the I / O bus via the I / O bus. Inspection of the internal circuit of the data processing apparatus main body is performed via the data processing apparatus.

〔Example〕

FIG. 1 is a block diagram of one configuration example in an embodiment of the present invention. The configuration of the data processing device of this example is in line with the most common personal computer. The address bus, the data bus, and the control signals associated therewith are collectively referred to as a bus. In this configuration, there are four types of buses. CPU1
CPU bus 15, high-speed memory bus 19, extended memory bus 18, and lower-speed I / O bus 17. The reason why the bus is divided in this way is that the memory bus 19 or the extended memory bus 18 that directly affects the performance of the data processing device operates at high speed, so I / O that does not require much high speed
This is because it is separated from the bus. In FIG. 1, the I / O bus has a display controller 8 and a floppy controller 9
A low-speed memory 10 and other I / Os 11 are connected, and access at a lower speed suitable for these is possible. However, in recent years, higher speed has been required for the display controller. For example, a configuration in which the display controller is connected to another higher speed bus can be considered. Now, these three buses 18, 19, and 17 are respectively connected to buffers 2, 3,
6 separated. The bus controller 7 controls all of these buses, but mainly controls the most complicated I / O bus. Expansion slots 12, 1
Reference numeral 3 denotes a slot for mounting a board for function expansion, to which an I / O bus is directly connected. The terminals of the EMU signal 16 are arranged in each expansion slot. The internal expansion memory 4 and the main memory 5 can read / write data from / to the I / O bus because they support DMA from the normal I / O bus. If this is not possible, only the function test of the internal expansion memory 4 and the main memory cannot be performed by the function test board. The function test board 14 can be mounted on either the expansion slot NO1 (12) or the expansion slot NO2 (13).

Now, in order to diagnose the inside of the device through the expansion slot, the CPU on the test board must have access to the I / O bus and main memory. However, even if the bus controller has a bus arbitration function and the data processing device can share the I / O bus with multiple CPUs,
Only when the CPU operates normally and the bus controller gives the I / O bus access right to the CPU of the inspection board, the inspection board can inspect the I / O bus and the main memory for the first time. In other words, when the main CPU does not operate normally for some reason and the bus access right cannot be given to others, I / O
Inspection of bus and main memory is not possible. When the system does not operate normally, there are many failures around the CPU, which is not sufficient as a system hardware inspection function. Therefore, the CPU is forcibly stopped by asserting the EMU signal, and a signal input (for example, a hold acknowledge signal) indicating that the CPU of the bus controller stops and does not access the I / O bus and the main memory is performed. Force assertion. This is the main CP
Bus masters other than U (DMA controller, refresh controller, external CPU, etc.) can freely access the I / O bus and main memory. In the arbitration of the access right of the normal bus, the priority of the main CPU is high, so that the CPU must be stopped in order to allow other bus masters to freely access.

Now, let us consider a case where the function test board 14 is installed in either the expansion slot NO1 (12) or the expansion slot NO2 (13). As a result, the EMU signal is asserted, and the EMU signal directly acts on the bus controller 7 and the CPU 1 to acquire the bus access right.

FIG. 2 shows an example of how the EMU signal acts on the bus controller and the CPU in more detail. The bus controller 41 in FIG.
Bus request signals such as the bus request signal from the CPU 40, the DMA controller request signal 29 (DRQ) and the external CPU or external master request signal 27 (ERQ) can be arbitrated and the I / O bus can be accessed by priority etc. The request signal source is determined and response signals EAK28, DAK29, etc. are returned. In other words, FIG. 2 shows the case of a data processing device capable of accessing an I / O bus from an external master. In this case, the function test board uses the ERQ signal 27 and EAK signal to
The bus access right is acquired and confirmed, and normal operation is enabled. If it is not possible to access the I / O bus from an external master, a spare bus controller must be provided externally so that the function test board can acquire the I / O bus access right.

The EMU signal 31 is connected to the two ORs 44 and 45, and by asserting the EMU signal 31, the CPU's HOLD24 (hold signal) and R
Forcibly assert S25 (reset signal) to stop CPU40. At the same time, the EMU signal 31 and the HLDA (hold response) signal 22 of the CPU are ORed by OR43, and the HL of the bus controller is
By forcibly asserting the DA input signal 23, the bus controller is notified that the CPU has stopped. This is one means for forcibly stopping the CPU, prohibiting the CPU from accessing the bus controller, and allowing other masters to freely use the I / O bus.

FIG. 3 shows the connection between the CPU and the bus controller by the EMU signal 31.
HLDA input signal 23 is forcibly asserted and ERQ2
After the function test board gains access right by 7, the DRQ
6 is a timing chart showing how an access right of an I / O bus changes when a signal 29 and an RFRQ signal 21 are generated. DAK30
Is an I / O bus access right acquisition response signal to the DMA controller. As you can see from this, the function test board is
Even after acquiring the I / O bus access right, functions such as DMA and refresh can be operated as they are. In other words, the function test can be performed by operating circuits other than the CPU as in the normal case. If the main memory and the extended memory are accessible from the I / O slot, the main memory and the extended memory can be checked. Therefore, almost all functional tests except the CPU of this system are possible.

Next, an embodiment of a function inspection board will be described with reference to FIGS. 4 and 5. FIG. In the example of FIG. 4, the CPU 50 of the function test board is the same as the main CPU of the main body. On the function test board, a function test program (for example, a memory check) of the most basic part of the system is placed in the ROM 57 arranged at a position avoiding an area where the program of the main body runs. Further, simple output means (for example, a buzzer) for notifying the result of the basic function inspection program is provided on the substrate. Inspection of other more complicated functions can be performed by running the main program of the main system, or the inspection program can be loaded from an external storage device to the main memory and run. Here, the connector 51 is a connector on the function test board inserted in the expansion slot, 54 is a bus buffer, 55 is a bus controller, 56 is a bus buffer of the CPU 50, and 58 is a read / write memory (RAM). It is.

In the example of FIG. 5, the CPU 60 of the function test board is the main C of the main body.
It may be different from PU. RO with built-in inspection program for inspecting main body system on function inspection board
An M67 and a controller such as a display controller 71 and a keyboard controller 72 for operating the inspection program and displaying the inspection result are provided. Further, a floppy disk controller 70 and a RAM 68 for loading the program are mounted in order to load a program from a floppy disk and perform a system check. According to this method, the device becomes large and is not very portable, but since the controller of the main body is not used for operating the inspection program and displaying the inspection result, the inspection can be easily performed even when they do not operate normally. is there.

Here, 61 is a connector on the function test board inserted into the expansion slot, 64 is a bus buffer, 65 is a bus controller, 66 is a bus buffer of the CPU 60, and 73 is a CPU buffer.
This buffer is used to separate the 60 buses from the I / O bus of the function test board.

〔The invention's effect〕

As described above, according to the present invention, the data processing device can be directly accessed from the I / O bus by connecting a low-speed memory and controllers of various input / output units to the I / O bus. By having a configuration that can be accessed from the memory bus through the I / O bus, and having a failure detection signal EMU in the expansion slot including all or a part of the I / O bus, a function test board inserted in the expansion slot CPU is stopped by asserting the EMU signal of
By gaining access to the I / O bus, it is possible to check the functions of the main memory and circuit units such as an I / O controller connected to the I / O bus.

In this way, even if the failure is related to the basic function and even the function test program does not work, disassemble the device once and insert the function test board into the expansion slot without using the CPU emulator etc. By running an inspection program or the like, it is possible to easily find a failure point of the data processing device. In this way, the response in the field can be performed more quickly, and a less expensive function inspection system can be configured for failure analysis in a factory. Furthermore, by standardizing expansion slots and sharing the same expansion slot between different models, different CPs can be used.
The same function test board can be used for different models having U. In other words, it is not necessary to develop a tool for functional inspection every time a new model is developed, which saves costs and man-hours.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a data processing apparatus according to the present invention, which can easily perform a function test. FIG. 2 is a detailed block diagram of a portion where the EMU signal of FIG. 1 acts on a CPU and a bus controller according to the present invention. FIG. 3 is a time chart of an embodiment of each signal shown in FIG. 2 according to the present invention. FIG. 4 is a block diagram of a function test board according to the present invention. FIG. 5 is a block diagram of a function test board according to the present invention. 1 Central processing unit (CPU) 2 Bus buffer 3 Bus buffer 4 Internal expansion memory 5 Main memory 6 Bus buffer 7 Bus controller 8 Display controller 9 Floppy controller 10 Low-speed memory 11 Other I / O controller 12 Expansion slot NO1 13 Expansion slot NO2 14 Function test board 15 CPU bus 16 Function test signal (EMU signal) 17 … Extended memory bus 19 …… Memory bus

Claims (1)

(57) [Claims] 1. A central processing unit (hereinafter referred to as a CPU)
And a main memory, input / output means, a controller for the input / output means, and an expansion slot for mounting an expansion board for function expansion. A controller, a low-speed memory, an internal controller means such as an interrupt controller, connected via an I / O bus, wherein the CPU and the main memory are connected to a faster memory bus, while the main memory is connected to an I / O bus. / O bus is also accessible via the memory bus, the expansion slot includes at least a part of the I / O bus,
The CPU is stopped by having a function test signal (hereinafter referred to as an EMU signal) in the expansion slot, inserting a function test board into the expansion slot and asserting (enabling) the EMU signal. A bus controller that directly accesses the I / O bus to obtain an access right to the I / O bus, and a controller for the input / output unit connected to the I / O bus, internal control means such as the low-speed memory and an interrupt controller, and the memory bus A data processing apparatus for performing a function test of the main memory connected to the data processing apparatus.