JP2861604B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a so-called salicide layer is provided on a silicon substrate surface by a reaction with a titanium film or the like in order to compensate for a high resistance of a shallow impurity diffusion region.

[0002]

2. Description of the Related Art With the increase in density and performance of semiconductor integrated circuits, impurity diffusion regions (hereinafter simply referred to as diffusion regions) are becoming shallower and smaller in area. Therefore, the resistance of the diffusion region itself and the contact resistance with the wiring and the like to the diffusion region become large, which limits the speeding up. Increasing the impurity concentration in order to lower the resistance is not preferable because problems such as inactivation of the impurities occur.

On the other hand, there has been proposed a method of equivalently reducing the resistance by selectively forming a low-resistance film on the silicon surface in the diffusion region (for example, see "Ultra-high-speed MOS device" p. 155, published by Baifukan).

In this method, a film of titanium or the like is formed on a silicon substrate, a compound is formed on the silicon surface by a reaction with titanium, and then an unreacted titanium film or the like on the insulating layer is selectively etched. Remove it. According to this method, the resistance can be reduced without changing the impurity concentration or the depth of the diffusion region. A silicon compound formed by such a selective reaction with the silicon surface is called salicide.

[0005]

FIG. 4 is a sectional view showing an example of the salicide forming process. As shown in FIG. 1A, the surface of the silicon substrate 1 is, for example, a known type.
A first element region and a second element region are defined by an isolation insulating layer 2 formed using a LOCOS (local oxidation of silicon) method. A source / drain region 4 formed by ion-implanting impurities using the gate electrode 3 as a mask is formed in the first element region, and a capacitor constituting a memory cell is connected to the second region. The impurity diffusion region 5 to be formed is formed.

Next, an SiO ₂ layer, for example, is deposited on the entire surface of the silicon substrate 1, and this is etched back.
After the sidewall insulating layer 7 is formed on the gate electrode 3 as shown in FIG. 1, a titanium film 8 is deposited on the entire surface of the silicon substrate 1 as shown in FIG. Then, when the silicon substrate 1 is heat-treated, the surface of the silicon substrate 1 in contact with the titanium film 8 reacts to generate a salicide layer. Since the titanium film 8 does not react with the isolation insulating layer 2 and the sidewall insulating layer 7, the titanium film 8 on these insulating layer layers does not become salicide.

Next, the silicon substrate 1 is placed in a mixed solution of, for example, hydrogen peroxide (H ₂ O ₂ ) and ammonium hydroxide (NH ₄ OH).
Immerse. This solution dissolves the metallic titanium but not the salicided titanium. as a result,
As shown in FIG. 4D, the titanium salicide film 8A remains only on the surface of the silicon substrate 1 exposed from the isolation insulating layer 2, and the unreacted titanium film 8 on the isolation insulating layer 2 and the sidewall insulating layer 7 Will be removed.

The titanium salicide film 8A in the first element region contributes to lowering the resistance of the source / drain region 4. However, it may not be preferable that the titanium salicide film 8A exists in the second element region. For example, there is a case where the impurity diffusion region 5 is used as a high resistance layer. In such a case, the first element region is masked with a resist layer 9 and the titanium salicide film 8A in the second element region is selectively formed using a hydrofluoric acid solution as an etchant, as shown in FIG. The removal method is adopted.

However, when the titanium salicide film 8A is formed as described above, generally, a lattice defect is easily generated in the impurity diffusion region 5, so that a leak current at the junction increases. Therefore, there arises a problem that the impurity diffusion region 5 cannot be used as a high-resistance layer, or that it is not desirable to form a memory cell in the impurity diffusion region 5. Note that, for example, a defect also occurs in the source / drain region 4 in the first element region in the same manner. However, since this transistor aims at high-speed operation, leakage at the junction does not matter.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for selectively forming salicide only in a predetermined region in the manufacture of a semiconductor integrated circuit without adding a special step.

[0011]

The object of the present invention is to form a first region and a second region separated from each other by a separation insulating layer on a silicon substrate, and to provide an insulating gate in the first region. Forming a gate electrode of the type field effect transistor, forming an impurity diffusion region on the surface of the silicon substrate in the second region, and then forming a second region covering the first region and the second region. forming a first insulating layer, and then a step of the first insulating layer to expose the first area to form a mask layer which covers the whole of the second region, then the mask By etching the first insulating layer on the first region by reactive ion etching using the layer as a mask, a side wall insulating layer is formed on the side wall of the gate electrode, and Said A step of selectively exposing the silicon substrate, and then, the gate electrode, the sidewall insulating layer, Oyo
And using the first insulating layer on the second region as a mask
The insulated gate electric field by ion implantation.
For forming source / drain regions of high-effect transistors
Forming a metal film over the entire surface of the silicon substrate , and then reacting the metal film with the exposed silicon substrate in the first region by heat treatment to form a silicon compound. , then removing the metal film which does not contribute to the reaction, then at least
It said forming a second insulating layer on the second region, then selectively removing the second insulating layer and the first insulating layer on said second region, the impurity A step of forming an opening reaching the diffusion layer, and then, in the opening, various steps of forming a conductive layer electrically connected to the impurity diffusion layer. This is achieved by a manufacturing method.

[0012]

After forming a predetermined diffusion region in the first and second element regions, a film of titanium or the like is formed by covering the second element region requiring a high-resistance diffusion region with an insulating layer. As the insulating layer, for example, FE formed in the first element region is used.
An insulating layer constituting a sidewall insulating layer serving as a mask when forming LDD (lightly doped drain) of T may be left so as to cover the second element region. Since the titanium film and the like formed in the second element region do not become salicide, they can be selectively removed without using a special mask. Also,
The underlying insulating layer may be left as it is as an interlayer insulating layer.

[0013]

FIG. 1 is a process explanatory view of one embodiment of the present invention. For example, as shown in FIG. 1A, an isolation insulating layer 2 is formed on a surface of a silicon substrate 1 by a well-known LOCOS method. A gate electrode 3 made of, for example, polysilicon is formed in the first element region defined by the isolation insulating layer 2. Using the gate electrode 3 as a mask, for example, phosphorus
(P) ions, acceleration voltage 60 KeV, dose 2 × 10 ¹⁴ / cm ²
To form a low concentration source / drain region 4. In the second element region, for example, phosphorus (P) ions are implanted at an acceleration voltage of 60 KeV and a dose of 5 × 10 ¹⁴ / cm ² to form an impurity diffusion region 5. The above is the same as the conventional process.

Next, for example, by a well-known CVD method, FIG.
As shown in (b), the entire surface of the silicon substrate 1 has a thickness of about
After depositing a 1500 ° SiO ₂ layer 11, a resist layer 12 for selectively masking the second element region is formed. Then, the SiO ₂ layer 11 exposed from the resist layer 12 is anisotropically etched by well-known reactive ion etching (RIE).
Is etched back until the silicon substrate 1 is exposed in the first element region. As a result, as shown in FIG.
The sidewall insulating layer 7 of the gate electrode 3 is formed, and the SiO ₂ layer 11A covering the second element region remains. The figure shows a state where the resist layer 12 has been removed after the anisotropic etching.

Next, for example, by using a resist mask (not shown), for example, arsenic (As) is selectively applied to the first element region.
After implanting ions at an acceleration voltage of 60 KeV and a dose of 4 × 10 ¹⁵ / cm ² , the silicon substrate 1 is placed in an inert atmosphere at 830
Heat treat at ℃ for about 30 minutes. As a result, As is activated, and at the same time, P implanted into the low concentration source / drain region 4 and the impurity diffusion region 5 is activated.

Next, as shown in FIG. 1D, a titanium film 8 having a thickness of about 600 mm is deposited on the entire surface of the silicon substrate 1 by, for example, a well-known sputtering method, and then the silicon substrate 1 is subjected to lamp annealing. , 800 ° C for 30 seconds. As a result, salicide is generated only in the portion of the titanium film 8 in contact with the silicon substrate 1 exposed in the first element region and the titanium film 8 on the gate electrode 3.

Next, the silicon substrate 1 is placed in a mixed solution of, for example, hydrogen peroxide (H ₂ O ₂ ) and ammonium hydroxide (NH ₄ OH).
Immerse. This solution dissolves the metallic titanium but not the salicided titanium. as a result,
As shown in FIG. 1E, a titanium salicide film 8A remains only on the surface of the silicon substrate 1 exposed in the first element region, and an SiO ₂ layer covering the isolation insulating layer 2 and the second element region.
Unreacted titanium film 8 on 11A is removed.

Next, as shown in FIG. 2 (f), an interlayer insulating layer 13 of PSG (phosphosilicate glass) having a thickness of about 5000 mm is deposited on the entire surface of the silicon substrate 1 by a known CVD method. The source insulating layer in the first element region is formed on the interlayer insulating layer 13.
The contact holes 15 and 16 reaching the titanium salicide film 8A on the drain region 4 and the surface of the silicon substrate 1 in the second element region are formed. And the interlayer insulating layer 13
An aluminum film, for example, is deposited thereon, and is patterned by a well-known lithographic technique to form source / drain regions 4 through contact holes 15 and 16 respectively.
And wiring connected to impurity diffusion region 5 (not shown)
To form Contact hole 15 for interlayer insulating layer 13
For example, according to RIE using hydrogen fluoride (HF) gas as an etchant, the titanium salicide film 8A can be formed with a selectivity similar to that of a silicon substrate. It is not affected by the thickness of the _two layers 11A.

An impurity diffusion region 5 as shown in FIG.
And when used as a drain region of the transfer gate FETs Q ₁ shown in FIG. 2, for example, leakage of charge stored in the capacitor for connected storage that this drain region has been described with reference to FIG. 3 The number is smaller than that of the impurity diffusion region 5 formed by the conventional method. Therefore, according to the present invention, it is possible to increase the density of memory cells, improve reliability, and the like.

Further, the present invention improves the withstand voltage of the protection circuit by forming a transistor constituting a protection circuit for protecting an input / output circuit with an external circuit from static electricity in the second region. It is valid. Further, according to the present invention, since the impurity diffusion region can be maintained at a higher resistance than when the salicide layer is formed, the degree of freedom in designing a circuit configuration using the impurity diffusion region as a high resistance is increased. There are advantages.

[0021]

According to the present invention, it is possible to prevent a salicidation reaction on a desired diffusion region without adding a special process, so that the diffusion region is controlled to a desired high resistance and with good reproducibility. And junction leakage in the diffusion region can be reduced. As a result, the performance and manufacturing yield of semiconductor integrated circuits that use diffusion regions as high resistance and high-density semiconductor memories that have memory cells connected to diffusion regions with shallow capacitance to store write charges can be improved. is there.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of one embodiment of the present invention (part 1).

FIG. 2 is a process explanatory view of one embodiment of the present invention (part 2).

FIG. 3 is an equivalent circuit diagram of a memory cell to which the present invention is applied;

FIG. 4 is an explanatory view of a conventional problem 1 silicon substrate 8 titanium film 2 isolation insulating layer 8A titanium salicide film 3 gate electrode 9, 12 resist layer 4 source / drain region 11, 11A SiO ₂ layer 5 impurity diffusion region 13 interlayer insulation Layer 7 Side wall insulation layer 15, 16 Contact hole

Claims (1)

(57) [Claims] A step of forming a first region and a second region separated from each other by a separation insulating layer on a silicon substrate; and forming a gate electrode of an insulated gate field effect transistor in the first region. Forming; forming an impurity diffusion region on the surface of the silicon substrate in the second region; and forming a first insulating layer covering the first region and the second region. If, then, the first insulating layer, said first region exposed, the forming a mask layer in which the second covering the entire area, then reactive ion by the mask layer as a mask by etching, said by etching the first insulating layer in the first region, thereby forming a sidewall insulating layer on sidewalls of the gate electrode, the silicon substrate of the first region selectively dew A step of, then, the gate electrode, the sidewall insulating layer, and the
Using the first insulating layer on the second region as a mask,
Insulation gate type field effect transistor
Forming a source / drain region of a transistor, then forming a metal film on the entire surface of the silicon substrate , and then reacting the silicon substrate and the metal film exposed in the first region by heat treatment. Forming a silicon compound, and then removing a metal film that does not contribute to the reaction; then, forming a second insulating layer on at least the second region; wherein on the second region second insulating layer and said first insulating layer is selectively removed, forming an opening reaching the impurity diffusion layer, then, in the opening, the impurity diffusion Forming a conductive layer electrically connected to the layer.