JP2863249B2 - Reset method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a reset signal transmitted to an input / output bus,
The present invention relates to a reset method for resetting a device connected to the input / output bus to an initial state.

[Prior Art] SCSI standardized by the ANSI standard as an interface standardized as an input / output bus for small computers
(Short for small computer system interface), and the following two forms are known as system forms of a small computer system using this SCSI as an input / output bus.

First, as shown in FIG.
In this embodiment, one or more peripheral devices 2 and 3 (in the figure, two devices are shown) are connected by SCSI4.

Second, as shown in FIG. 3, a plurality of host computers 5, 6 (FIG. 2 shows the case of two computers) and one or a plurality of peripheral devices (FIG. 3 shows the case of two computers). 7,8 and SCS
This is the form connected by I4.

Conventionally, in the case of the first embodiment, when the host computer 1 resets the peripheral devices 2 and 3 to an initial state (meaning a state immediately after startup), a reset signal is transmitted on the SCSI 4 which is an input / output bus. And the peripheral device
A few were forced to an initial state (ie, immediately, regardless of their operating state).

In the case of the second embodiment, the host computer 5
Sends a reset signal on the SCSI 4, which is an input / output bus, to initialize the host computer 6 and the peripheral devices 7 and 8. When the host computer 6 receives the reset signal, The operating state of each part, the extent to which the command being executed has been executed, and the like are stored, and thereafter, the communication with the SCSI is cut off. However, the peripheral devices 7 and 8 are forcibly set to the initial state as in the case of the first embodiment.

That is, in the related art, as a reset method for resetting a device connected to the input / output bus to an initial state by a reset signal sent to the input / output bus, a method for forcibly setting an initial state and a method for actively initializing There was something to put in a state.
These conventional reset methods will be described below by specifically showing the device configuration.

In the case of the reset method that forcibly initializes the state (that is,
In the case of the peripheral devices 2, 3, 7, 8, etc., as shown in FIG. 4, the CPU 10 executes a program stored in the memory 11 to access the FDD 13 via the FDD controller 12. , The mechanism via the mechanism interface 14
Operate 15 or SCSI4 via bus controller 16
As soon as the reset receiver 17 receives the reset signal 19 sent to the SCSI 4 by the host computer while exchanging data with another device connected to the device, the reset receiver 17 , A stop signal is output, and the operation under execution is immediately stopped regardless of the operation state of each part to return to the initial state.

Further, in the case of the reset method for actively resetting to the initial state (that is, in the case of the host computers 5 and 6, etc.), the CPU 20 executes the program stored in the memory 21 as shown in FIG. FDD23 via controller 22
While accessing the device, operating the mechanism 25 via the mechanism interface 24, and exchanging data with other devices connected to the SCSI 4 via the bus controller 26. When the reset receiver 28 receives the reset signal 30 sent to the SCSI 4 by the other host computer, first, the interrupt generation circuit 27 is activated, and the interrupt generation circuit 27 sends an interrupt signal to the CPU 20. Then, the CPU 20 protects the data being processed, stops the operating FDD 13 and the mechanism unit 15, and then cuts off the communication between the SCSI 4 and the bus controller 26 to return to the initial state.

[Problems to be Solved by the Invention] However, in the conventional reset method,
There were problems in the following points.

For example, in the forced reset method shown in FIG. 4, the apparatus is provided with an OCR, a printer, an image scanner, or the like as the mechanism section 15, and the input / output bus (ie, , SCSI4), when it receives a reset signal, it is immediately forcibly initialized.
There is a possibility that the mechanism may be damaged or data being processed may be lost.

In the active reset method shown in FIG. 5, when the CPU 20 of the device receiving the reset signal falls into an inoperable state such as a program runaway for some reason, an input / output bus (ie, SCSI4) is used. Cannot execute the process in response to the reset signal from, and therefore cannot be set to the initial state.

The present invention has been made in view of the above circumstances, and is a reset method for resetting a device connected to the input / output bus to an initial state by a reset signal sent to the input / output bus. To provide a reset method that can surely reset the device to the initial state regardless of the operation state of the CPU of the device to be replaced, and that can significantly reduce damage to the mechanism and data loss due to the reset. With the goal.

Means for Solving the Problems A reset method according to the present invention is a reset method for resetting a device connected to the input / output bus to an initial state by a reset signal sent to the input / output bus. A device connected to the input / output bus, a reset circuit;
An interrupt generation circuit and a reset prevention circuit are provided, and the CPU of the device is further provided with a reset signal prevention function and a reset processing function.

Here, the reset circuit detects the reset signal on the input / output bus, and sends a reset signal to each part to be reset in the device after a certain period of time, and immediately resets each part regardless of its operation state. It is to reset.

The interrupt generation circuit detects a reset signal on the input / output bus and sends an interrupt signal to the CPU in the device.

Further, the reset prevention circuit is for outputting a predetermined signal to the reset circuit to prevent the reset circuit from sending out a reset signal.

On the other hand, the reset signal blocking function and the reset processing function transmit an interrupt signal from the interrupt generation circuit to the CPU.
This function is activated when the reset signal is received.
Activating the reset prevention circuit stops the reset signal from being sent from the reset circuit. In addition, the reset processing function outputs a predetermined command to each part to be reset to store the data being processed and how far the processing has been executed, and terminates the operation of each mechanical part to be reset. Disconnects with the I / O bus later.

The reset method of the present invention has the above-described device configuration.
The apparatus can be reset to an initial state by a command of a CPU in the apparatus.

[Operation] In the reset method according to the present invention, the reset signal transmitted on the input / output bus is detected by the interrupt generation circuit provided in the device to be reset and the reset circuit.
Then, the interrupt generation circuit immediately sends an interrupt signal to the CPU, and the reset circuit starts time counting so as to transmit the reset signal after a predetermined time.

In this case, if the CPU is in a normal operating state, when the interrupt signal is received, the reset signal blocking function and the reset processing function are activated, and the reset signal blocking function immediately activates the reset blocking circuit. Thus, the transmission of the reset signal from the reset circuit is prevented.
In the reset processing function, a predetermined command is output to each part to be reset, and firstly, the data being processed and how far the processing has been executed are stored, and the operation of each mechanical part to be reset is performed. Then, by disconnecting from the input / output bus, the state of the device is smoothly returned to the initial state.

Further, when the CPU is running out of control for some reason and is not in a normal operation state, the reset signal blocking function and the reset processing function do not operate even if an interrupt signal is received from the interrupt generation circuit. However, in such a case, the reset circuit keeps measuring time,
After a certain time, the reset circuit sends a reset signal to each part to be reset to forcibly reset each part.

Therefore, the apparatus can be reliably reset to the initial state regardless of the operation state of the CPU.

In addition, since the forced reset processing by the reset circuit is limited only to the case where the CPU does not operate normally, the forced reset is performed compared to the conventional method in which the reset processing is always executed forcibly. Opportunities to perform the processing are extremely reduced, and it is also possible to significantly reduce damage to the mechanism and data loss due to the forced reset processing.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1, FIG. 6, and FIG.

The reset method of this embodiment is a small computer system using SCSI as an input / output bus, in which a reset signal sent from one host computer connected to the input / output bus to the input / output bus allows the input / output The other devices connected to the bus (the "device" in this case, peripheral devices and other host computers sharing the input / output bus) are reset to the initial state.

In order to execute the reset method of the present invention, it is necessary to improve a device to be reset in advance.

FIG. 1 is a block diagram of a peripheral device 30 improved to execute the reset method of this embodiment.

The peripheral device 30 has a CPU 31 therein. The CPU 31 executes a program stored in the memory 32 to perform a predetermined processing operation. For example, the CPU 31 accesses a floppy disk drive (FDD) 34 via the FDD controller 33, A mechanism unit 36 is operated via a bus 35, and data is exchanged with another device (not shown) connected to an input / output bus 42 which is a SCSI via a bus controller 37.

When a reset signal 43 is sent from the host computer (not shown) to the input / output bus 42, the reset signal 43 is detected by a reset receiver 38.

 The above points are common to the related art.

However, the peripheral device 30 is provided with a reset circuit 39, an interrupt generation circuit 40, and a reset prevention circuit 41 as a new configuration, and further, as functions of the CPU 31, a reset signal prevention function, a reset processing And functions.

The reset circuit 39 and the interrupt generation circuit 40 are connected to the reset receiver 38 by a reset signal 43 on the input / output bus 42.
Is detected, it is notified and a predetermined operation is performed.

Here, when the reset signal 43 is detected by the reset receiver 38, the reset circuit 39 starts clocking, and sends out a reset signal 39a to each part to be reset in the device 30 after a predetermined time. Thus, each part is immediately reset regardless of its operation state.

When the reset signal 43 is detected by the reset receiver 38, the interrupt circuit 40 sends an interrupt signal 40a to the CPU 31 in the device 30.

Upon receiving a predetermined command (reset prevention command) from the CPU 31, the reset prevention circuit 41 immediately outputs a predetermined signal to the reset circuit 39 to prevent the reset circuit 39 from sending the reset signal 39a. is there.

The reset signal blocking function and the reset processing function,
Each of these functions is activated when the CPU 31 receives an interrupt signal 40a from the interrupt generation circuit 40.

Here, upon receiving the interrupt signal 40, the reset signal blocking function sends the reset blocking command to the reset blocking circuit 41 immediately, thereby
Activating the reset signal 39 from the reset circuit 39.
Stops sending a.

Upon receiving the interrupt signal 40, the reset processing function immediately outputs a predetermined command to each part to be reset, and first stores the data being processed and how far the processing has been executed in the memory 32 or the like. At the same time, terminate the operation of the mechanical unit to be reset, and then cut off the communication with the input / output bus 42 by the bus controller 37,
The device 30 is set to an initial state.

FIG. 6 specifically shows a signal flow between the reset circuit 39 and the reset prevention circuit 47, and FIG. 7 is a time chart of each signal shown in FIG.

The processing operation when the reset signal is received will be described below with reference to FIGS. 6 and 7.

The reset signal shown in FIG. 6 and FIG.
The signal portion of "W" indicates the reset instruction, and this "LOW"
1 corresponds to the output signal of the reset receiver 38 in FIG.

The reset circuit 39 outputs a valid reset signal (ie,
Upon receiving a reset signal having a "LOW" portion), the first and second two timer circuits 44, 4 are started immediately.
5 and a NAND gate 46 to which the output signals of the timer circuits 44 and 45 are input.

Here, as indicated by the arrow (a) in FIG. 7, each of the timer circuits 44 and 45 starts clocking at the fall of the reset command. During the clocking period, the output signal of the timer circuit 44 becomes It becomes “LOW”, and the output signal of the timer circuit 45 becomes “HIGH”. As shown in FIG. 7, the time period of the second timer circuit 45 is originally set to be longer than the time period of the first timer circuit 44 (unless it is not blocked by the reset prevention circuit 47).

The NAND gate 46 outputs a valid reset signal when both output signals of the timer circuits 44 and 45 are “HIGH”.

Here, the effective reset signal has a signal portion of "LOW" as shown in FIG.

On the other hand, upon receiving a valid reset prevention command from the CPU 31, the reset prevention circuit 47 outputs a valid reset prevention signal to the second timer circuit 45, and changes the output signal “HIGH” of the timer circuit 45 to “LOW”. Thus, the reset signal output from the NAND gate 46 becomes invalid.

A valid reset prevention command has a signal portion of "LOW" as shown by a broken line in FIG. 7, and is invalid if there is no such portion.

The effective reset prevention signal has a signal portion of "LOW" as shown by a broken line in FIG.
If this part does not exist, it becomes invalid.

As shown by the arrow (b) in FIG. 7, the "LOW" portion of the reset inhibition signal and the "LOW" portion of the output signal of the timer circuit 45 correspond to the fall of the valid reset inhibition command.

When a valid reset prevention signal enters the second timer circuit 45, the output signal of the timer circuit 45 changes to "LOW", and the reset signal output by the NAND gate 46 is indicated by a broken line in FIG. As shown by, the signal portion of “LOW” disappears and becomes invalid. Therefore, in this case,
The reset processing by the reset circuit 39 is prevented.

In the device 30 described above, the reset signal 43 transmitted from the host computer (not shown) onto the input / output bus 42 during the operation of the device 30 is detected by the interrupt generation circuit 40 and the reset circuit 39.

Then, the interrupt generation circuit 40 immediately sends an interrupt signal 40a to the CPU 31, and the reset circuit 39 starts timing to send a reset signal 39a (a valid reset signal in FIG. 7) after a predetermined time. .

In this case, if the CPU 31 is in a normal operating state,
Upon receiving the interrupt signal 40a, the reset signal blocking function and the reset processing function are activated. In the reset signal blocking function, the reset blocking circuit 41 is immediately activated to send the reset signal 39a from the reset circuit 39. Block.

In the reset processing function, a predetermined command is output to each part to be reset, and firstly, the data being processed and how far the processing has been executed are stored, and the operation of each mechanical part to be reset is performed. And terminate
Next, the communication with the input / output bus 42 by the bus controller 37 is cut off, thereby smoothly returning the state of the device to the initial state.

Further, if the CPU 31 is performing a program runaway for some reason and is not in a normal operation state, the reset signal blocking function and the reset processing function do not operate even if the interrupt signal 40a is received from the interrupt generation circuit 40. . However, in such a case, the reset circuit 39 keeps measuring time, and after a predetermined time, the reset circuit 39 sends a reset signal 39a to each part to be reset to forcibly reset each part. I do.

Accordingly, the apparatus can be reliably reset to the initial state regardless of the operation state of the CPU 31.

In addition, since the forced reset processing by the reset circuit 39 is limited only to the case where the CPU 31 does not operate normally, the forced reset processing is forcibly compared to the conventional method in which the reset processing is always executed forcibly. Opportunities for performing the resetting process are extremely reduced, and it is also possible to significantly reduce damage to the mechanism and loss of data due to the forced resetting process.

In the above-described embodiment, the case where the peripheral device is used as the device for carrying out the present invention has been described.
9, the same effect can be obtained even with a host computer or the like as long as the configuration includes the interrupt generation circuit 40, the reset prevention circuit 41, and the like, and further includes the reset signal prevention function and the reset processing function in the CPU 31. it can.

Further, the reset method according to the present invention resets a device connected to the input / output bus to an initial state by a reset signal transmitted to the input / output bus. Although SCSI has been exemplified, the present invention is not limited to this.

[Effects of the Invention] As is clear from the above description, in the reset method of the present invention, when the built-in CPU of the device to be reset is operating normally, the reset signal on the input / output bus is detected. The CPU generates an interrupt signal from the interrupt generation circuit.
The reset signal blocking function and the reset processing function operate to protect the data being processed by the command sent to each part by the CPU and smoothly reset each part to the initial state.

On the other hand, if the CPU has caused a program runaway or the like for some reason and is not operating normally, the reset circuit continues to measure time, and after a certain period of time, the reset circuit sends a reset signal to each part to be reset. Send out and forcibly reset each part.

Therefore, the apparatus can be reliably reset to the initial state regardless of the operation state of the CPU.

In addition, since the forced reset process by the reset circuit is limited only to the case where the CPU does not operate normally, the forced reset process is forcibly performed as compared with the conventional method in which the reset process is always performed forcibly. Opportunities for performing the resetting process are extremely reduced, and it is also possible to greatly reduce damage to the mechanism and data loss due to the forced resetting process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an apparatus configuration according to an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of a system configuration using SCSI as an input / output bus, and FIGS. FIG. 6 is an explanatory diagram of a reset method. FIG.
The figure is a time chart of each signal at the time of reset in one embodiment. 30 ... device, 31 ... CPU, 32 ... memory, 34 ... FDD, 36
... Mechanical part, 37 ... Bus controller, 38 ... Reset receiver, 39 ... Reset circuit, 40 ... Interrupt generation circuit, 41 ... Reset prevention circuit, 42 ... I / O bus, 43 ...
... reset signal, 44 ... first timer, 45 ... second timer, 46 ... NAND gate.

Claims (1)

(57) [Claims] 1. A reset signal sent to an input / output bus,
A reset method for resetting a device connected to the input / output bus to an initial state, wherein a device connected to the input / output bus detects a reset signal on the input / output bus and after a predetermined time after the reset signal is detected. A reset circuit for sending a reset signal to each part to be reset in the apparatus and immediately resetting each part regardless of its operation state, and a CPU in the apparatus by detecting a reset signal on an input / output bus An interrupt generating circuit for transmitting an interrupt signal to the reset circuit, and a reset prevention circuit for outputting a predetermined signal to the reset circuit to prevent the reset circuit from transmitting a reset signal. As a function that operates when an interrupt signal is received from the generation circuit, the reset signal is transmitted from the reset circuit by activating the reset prevention circuit. A reset signal blocking function to stop and output a predetermined command to each part to be reset to store the data being processed and how far the processing has been executed, and to terminate the operation of each mechanism part to be reset A reset method that is equipped with a reset processing function that disconnects the communication with the I / O bus later, so that it can be reset to the initial state by a command of the CPU in the device.