JP2864982B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a flat interlayer insulating film on a device.

[0002]

2. Description of the Related Art In order to enable lithography and etching of miniaturized high-density wiring, the underlying insulating film must be sufficiently planarized in advance. If you need a pattern resolution of 0.5μm or less,
It is necessary to secure the flatness of the base insulating film both locally and over a wide area (over the entire exposed area). The local flatness of the base insulating film can be achieved by a conventionally used oxide film reflow. However, when severe flatness is required over a wide area, only a polishing technique is available.

As a polishing technique used for flattening an underlying interlayer film of wiring, VMIC (1990 PROCEEDIN 1990)
G IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE
) In the proceedings. 438-P. 440 has been proposed. 10 to 11 show the polishing technique of the underlying interlayer film of the wiring in the order of the steps.
11A and 11B are cross-sectional views showing a conventional planarization method using polishing in the order of steps. FIG. 11 is a cross-sectional view showing a conventional planarization method using polishing in the order of steps. It is shown. Hereinafter, the conventional polishing technique will be described in accordance with the above. FIG. 10A shows a cross-sectional structure of an underlying device of an insulating film to be planarized. An element isolation (32), a source (33a), a drain (33b), and a gate electrode (34) are formed on a silicon substrate (31).
A gate electrode (34) and a wiring (35) in the same layer as the gate electrode (34);
In the upper layer, there is a first interlayer insulating film (36) made of reflowed BPSG, on which a contact (37) is formed, and a lower wiring (about 0.9 μm) made of CVD W / TiN / TiSi _2. 38) is formed.

From this state, as shown in FIG.
A 7 μm plasma CVD oxide film is grown on the entire surface. Here, using a colloidal silica slurry as a polishing liquid and a polyurethane pad as a polishing pad, polishing is performed for about 12 to 20 minutes by a usual polishing apparatus. In polishing, the polishing platen becomes a reference flat surface, and the polishing rate is higher in the convex portions than in the concave portions on the surface, so that the surface is flattened. However, in such a usual polishing method, a step of about 20 nm to 50 nm remains as shown in FIG. Further, if polishing is performed to remove such a step, a problem that the lower wiring (38) is exposed without reducing the step occurs.

In order to form a flat surface with higher precision, a method of providing a stopper layer for stopping polishing in a portion where polishing is not desired to be carried out beyond a certain value is disclosed in Japanese Patent Application Laid-Open No. 63-76349. Was proposed in. The method will be described with reference to FIGS. This FIG.
FIGS. 2A to 2B are cross-sectional views of the structure of a wiring and a contact in order to explain how a conventional planarization method by polishing using a stopper film became necessary. 3A is a sectional view of a contact portion of the two-layer wiring. 13B is a cross-sectional view of a contact portion for explaining a problem caused by a conventional planarization method using polishing without using a stopper film, and FIGS. 13A to 13C are diagrams illustrating a conventional stopper film. 14A to 14C are cross-sectional views illustrating a planarization method using polishing using a stopper film in a process order, and FIGS. 14A to 14C are cross-sectional views illustrating a planarization method using polishing using a conventional stopper film in a process order. .

First, the reason why such a highly accurate flat surface is required will be described. FIG. 12A is an explanatory diagram of a two-layer wiring structure requiring a highly accurate flat surface. The second-layer wiring (5) is connected to the first-layer wiring (51) via a contact hole (53) formed in the insulating film (52).
4) shows a cross-sectional structure of a portion connected. In such a contact portion of the two-layer wiring, the diameter a of the contact hole (53) tends to be smaller than the depth b due to the higher integration of the integrated circuit. When the aspect ratio given by b / a becomes large, for example, when aluminum is deposited as the second layer wiring (54), the insulating film (52)
The thickness t ₂ of the aluminum on the side wall of the contact hole becomes t _1> t ₂ with respect to the thickness t ₁ of the aluminum on the flat portion of the.

The value of the current flowing through the aluminum wiring is set by calculating the step area of the aluminum wiring. In the above-described example, the contact hole (53) is formed in the second layer wiring (54).
The cross-sectional area of the second layer wiring (54) on the side surface of
There is a problem that the cross-sectional area becomes smaller than the cross-sectional area of the layer wiring (54), and the resistance becomes large at the contact hole. In order to solve such a problem, a first method as shown in FIG.
A method has been proposed in which a columnar protrusion (59) is provided on the layer wiring (57), and the first layer wiring (57) and the second layer wiring (62) are connected through the columnar protrusion (59). . As a method for adjusting the heights of the columnar projections (59) and the upper surface of the insulating film (52) of this structure, a flattening technique with high precision is required.

When a conventional polishing method is used to form this structure, as shown in FIG. 12B, first-level interconnects (52) of the same level have columnar shapes of the same height as shown by solid lines in the figure. A convex portion (55) is provided, and an insulating film (52) is deposited on the entire surface so as to completely cover the columnar convex portion (55) as shown by a dotted line. Polishing is performed using a polishing technique until the surface of the columnar projection (55) is exposed. In this case, the distribution of the degree of polishing in the surface of the silicon substrate, that is, a portion that is polished too much (over polishing), a portion that is polished just well, and a portion that is not yet sufficiently polished (under polishing) occurs. Is inevitable. In FIG. 12 (b), the left convex part (55) is polished to just the right place, while the right column convex part (55) is over-polished as shown by the dotted line. In such a state, the distribution of the polishing in the silicon substrate is the same as that of the columnar projections (55).
And the level of the second layer wiring (54) becomes non-uniform.

Therefore, a polishing technique having the above-mentioned stopper layer is required. FIGS. 13 and 14 show a process of forming a two-layer wiring for explaining this technique in the order of steps. FIG. 13A shows a structure of an underlying wiring of an insulating film to be planarized. (56) is a support substrate on which the first layer wiring (57) is arranged. An etching stopper (58) and a columnar projection forming member (59) having the same shape are laminated on the first layer wiring (57). From this state, as shown in FIG. 13B, a 1.5 μm-thick PSG film (60) is deposited as an interlayer insulating film. Further, a polishing stopper film (silicon nitride film) (61) having a thickness of 0.3 μm and a resist film (62) are formed on the entire surface so as to be laminated thereon.
Are sequentially deposited.

FIG. 13 shows the polishing stopper film (61).
As shown in (b) and (c), the polishing stopper flat portion (61a) and the polishing stopper raised portion (61b) are made of PSG.
It is formed corresponding to the shape of the film (60). Subsequently, dry etching is performed to remove the polishing stopper protrusion (61b) as shown in FIG. Next, FIG.
The PSG film (60) is polished until the surface of the columnar projection forming member (59) is exposed as shown in FIG. Even if there is a variation in the polishing in the plane of the support substrate, the polishing stopper flat portion (61a) works there to prevent the occurrence of overpolishing.

Therefore, all the columnar convex forming members (5
Until the surface of 9) is exposed, polishing is performed while preventing overpolishing shown in FIG. FIG. 14 is a cross-sectional view of the structure of FIG.
This is shown in FIG. Thereafter, the columnar projection forming member (5)
The etching of 9) is performed to form the columnar projections (59a) shown in FIG. 14C, and then the second layer wiring (62) is formed. The polishing technique provided with the stopper film prevents overpolishing in a relatively small area such as the contact portion of the conventional two-layer wiring as described above, and makes it possible to planarize the insulating film. The polishing stopper flat portion (61a) shown in FIG. 13 (c) covers almost the entire area of the entire surface of the wafer to be polished, and the columnar convex portion forming portion (59) to be flattened (FIG. 14 (a) ) And its surrounding area are very small areas but not small areas.

Accordingly, in a semiconductor device handled in the present invention, in particular, in a memory device having a wide array region (having many repetitive patterns),
When attempting to planarize the surface of the insulating film on this device, overpolishing occurs near the center of the wide array region, which did not occur with the above-described polishing technique using the stopper film, and a flat interlayer insulating film was formed. Shape cannot be obtained. Furthermore,
When the over-polishing becomes severe, a fatal problem appears in that the interlayer insulating film on the device is completely polished and removed, and the upper surface of the device is polished.

[0013]

FIG. 15 schematically shows a cross section of the device in that state. That is, FIG. 15 is a diagram for explaining a problem that occurs when a conventional planarization method using polishing using a stopper film is applied to a memory device.
FIG. 3 is a cross-sectional view of a memory device. When the above-described polishing technique using the stopper film (73) is applied to the device as shown in FIG. 15, the protrusion (7) of the step of the insulating film to be polished and removed is required.
2) Since the stopper film (73) is to be disposed at a position other than (the portion indicated by the dotted line on the device array region (71)), the region where the stopper film (73) exists is shown in the drawing. Due to the narrowness, the over-polishing stop performance is deteriorated, and an over-polishing area (74) is formed. As a result, a desired flat shape cannot be obtained. In the present invention, when the convex portion of the step of the insulating film to be polished and removed is wider as shown in FIG. 15, the convex portion is not over-polished, and furthermore, the convex portion is formed under the convex portion region. An object of the present invention is to provide a polishing flattening technique that prevents a device portion from being polished.

[0014]

According to the present invention, there is provided a process for forming an array of capacitive elements having a predetermined height in a main surface region of a semiconductor substrate, and forming at least an upper portion of the array of capacitive elements with an interlayer insulating film. A step of providing a stop layer having an extremely small polishing rate, a step of depositing an interlayer insulating film on a surface including an upper portion of the stop layer, and polishing and removing the interlayer insulating film until the stop layer is exposed. Forming the flat surface by removing the stop layer by etching.

The present invention is also directed to a step of forming an array of capacitive elements having a predetermined height in a main surface region of a semiconductor substrate; Providing an extremely small stop layer, depositing an interlayer insulating film on the surface including the top of the stop layer, polishing and removing the interlayer insulating film until the stop layer is exposed, and then etching the stop layer. And forming a flat surface by depositing an interlayer insulating film thereon.

A stop layer having a polishing rate much lower than that of an interlayer insulating film, that is, a stopper film can be an insulating film or a conductive film. Specifically, a silicon nitride film or a titanium nitride film is used. A method for manufacturing a semiconductor device. Further, in order to provide a stop layer having a polishing rate significantly smaller than that of the interlayer insulating film, that is, a stopper film, on the upper part of the arrangement of the elements having a predetermined height in the main surface area of the semiconductor substrate, An interlayer insulating film may be provided between the stopper films, or no interlayer insulating film may be provided.

[0017]

In the present invention, a step of forming an array of capacitive elements having a predetermined height in a main surface region of a semiconductor substrate;
A step of providing a stop layer having a significantly lower polishing rate than the interlayer insulating film at least above the array of the capacitor elements;
Depositing an interlayer insulating film on the surface including the top of the stop layer, polishing and removing the interlayer insulating film until the stop layer is exposed, and then removing the stop layer by etching to form a flat surface. The interlayer insulating film of the semiconductor device is formed flat by preventing the convex portion of the step of the insulating film to be polished and removed from being polished, and further preventing the device portion below the convex region from being polished. Is what you can do.

A reference example will be described with reference to the drawings. Reference Example FIGS. 1 to 3 are cross-sectional views showing a reference example of a polishing and flattening technique of a reference example in the order of steps. In the following description, a stack capacitor type DRAM (Dynamic Random Access Memory) in which a large insulating film level difference occurs between a memory array region and a peripheral region is used as a base device for polishing and flattening. The structure of the device
For simplicity, the bit lines are omitted, and only the diffusion layer region to which the bit lines are connected is called a bit line.

FIG. 1 shows a cross section of a device structure under a interlayer film to be planarized. A memory cell (12) is formed on a silicon substrate (11). Although only two memory cells are shown in the figure, these memory cells are arranged to form a memory cell array (14). Hereinafter, only these two memory cells (12) will be described in detail. On the silicon substrate (11), a bit line (15) made of an impurity diffusion layer and a storage node (12a) are formed. The silicon substrate (1) sandwiching the bit line (15)
A gate insulating film (12b) made of a silicon oxide film is formed on the region (1), and a gate electrode (1) is further formed thereon.
By arranging 2c), a switching transistor of the memory cell (12) is configured.

On a silicon substrate (11) including a gate electrode (12c), a first silicon oxide-based insulating film is formed.
It is covered with an interlayer insulating film (16) and an adjacent gate electrode (12
c) and horizontal insulation of the contact hole (16a), as well as vertical insulation between the gate electrode (12c) and the lower electrode (13). The contact hole (16a) is formed in the first interlayer insulating film (16), and the storage node (12
a) and the lower electrode (13) are electrically connected.

The capacitance part, which is a component of the memory cell (12), includes a lower electrode and a capacitance insulating film (1) laminated thereon.
7) and the upper electrode (18). This lower electrode is made of, for example, doped polycrystalline silicon grown by CVD. In 64M DRAM to 1GDRAM, the height of the lower electrode (13) is formed to be about 0.8 μm to 1.2 μm. Further, a composite film of a silicon nitride film and a silicon oxide film is generally used as the capacitance insulating film (17).
The thickness of the silicon oxide film is about 5 nm to about 3.8 nm. Further, the upper electrode is formed by CVD.
It is made of polycrystalline silicon of about 0 to 200 nm. In this state, as shown in FIG. 2, a second interlayer insulating film (19) based on a silicon oxide film is deposited on the entire surface from 0.1 μm to 0.3 μm.

BPS is used as the second interlayer insulating film (19).
Reflow may be performed using a film having a reflow property such as G. Thereafter, a stopper film (20) made of a silicon nitride film is formed by a CVD method of 0.1 μm to 0.2 μm. Subsequently, as shown in FIG. 3A, a silicon oxide film-based third interlayer insulating film (21) is formed in a thickness of about 1.5 μm to 1.8 μm. Polishing is performed from this state. As a polishing technique, either a chemical mechanical polishing method or a mechanical polishing method may be used. The difference between the two is that in the chemical polishing method, not only a normal polishing material (abrasive grains) is suspended in a polishing liquid, but also a property of chemically etching a member to be polished is provided. By law,
Polishing is performed using a polishing liquid containing only a polishing material having no chemical etching property. As a reference example,
The mechanical polishing method will be described.

FIG. 16 is a conceptual diagram of polishing. A polishing pad (82) is stuck on a rotating platen (81), and while a polishing liquid (83) is being applied, a wafer holder (84) is applied.
The wafer (85) held in the wafer is rotated while applying a load to perform polishing. If the polishing pad (82) is made of foamable polyurethane, has a polyester fiber structure impregnated with polyurethane, or has a laminated structure of these, it is suitable for the polishing described in the reference example.
As described above, the polishing liquid is preferably one in which silica abrasive grains are suspended in pure water. In the chemical mechanical polishing method, for example, colloidal silica suspended in an aqueous ammonia solution may be used as a polishing liquid.

When polishing is performed by such a method, FIG.
A portion having a high step formed in the third interlayer insulating film (21) shown in (a) is selectively polished, and the step is reduced. In the experiment, the third interlayer insulating film (2
The reduction rate of the step was about 1.5 to 2 times faster than the reduction amount of the film thickness in 1). Thus, FIG.
Where the stopper film (20) shown in (b) is exposed, there is almost no step, and a flat surface shown as (22) in the figure can be formed.

Here, if the stopper film (20) is not provided as in this reference example and a flat surface is formed, and if the polishing is not stopped, the second interlayer insulating film (19) is formed. ) Is polished, and after about two minutes, the upper electrode (18) is polished. When the polishing of the upper electrode (18) starts, if the upper electrode (18) is made of polycrystalline silicon, the polishing rate is higher than that of the BPSG film constituting the interlayer insulating film. The entire body is polished and no longer functions as a memory cell.

However, when the stopper film (20) made of, for example, a silicon nitride film is provided as in this reference example, the polishing progress speed is higher than that of the BPSG film used as the second interlayer insulating film (19). Since the (polishing rate) is about 5 to 10 times slower, the second interlayer insulating film (19) is not polished even if the polishing is excessively performed for about 12 to 22 minutes after the stopper film is exposed. The capacity portion including the upper electrode (18) is not polished. The time of 12 minutes to 22 minutes is a time sufficient to form a flat surface over the entire surface of the wafer by adding such a time even if a non-uniform image occurs in the polishing rate within the wafer surface. The polishing can be stopped with sufficient margin. Therefore, according to this reference example, the interlayer insulating film on the capacitance portion of the DRAM having the stack capacitance can be easily flattened over the entire surface of the wafer.

Embodiment 1 A first embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a cross-sectional view showing the order of polishing steps for explaining the first embodiment. The cross-sectional shape at the start of polishing is the same as in FIG. From this state, polishing is performed in the same manner as in the reference example. The polishing rate of the third interlayer insulating film (21) in the portion below the step is higher than in the case of the reference example, and the flatness is lower than that of the reference example, that is, FIG.
If a surface shown as a depression (23) is formed, for example, when a silicon nitride film is used as the stopper film (20), the third interlayer insulating film (21) is formed using hot phosphoric acid. The stopper film (2
0) is removed by wet etching.

According to this method, even when the recess (23) is formed, the upper portion of the step can be lowered by the thickness of the stopper film (20). This can also be avoided to form a flat surface similar to the reference example. The difference between the first embodiment and the reference example is that even when the first embodiment is inferior in polishing technique to the reference example, a similar flat surface can be formed, that is, the degree of freedom in the polishing technique is increased. Is a point.

Embodiment 2 Next, a second embodiment will be described. FIG. 1 used for describing the reference example shows a state in which the upper electrode (18) and the capacitor insulating film (17) are patterned. In the second embodiment, patterning is performed as shown in FIG. In a state in which both are attached to the entire surface of the wafer (in the state of the upper electrode member (18a) in FIG. 5A), a stopper layer (20) made of, for example, a silicon nitride film is formed thereon directly by 0.1 μm
From 0.2 .mu.m CVD. Thereafter, a resist (24) is applied, and is patterned into a shape of the upper electrode by a lithography technique. Using this as a mask, the upper electrode member (18a) and the capacitance insulating film (17) are dry-etched to obtain the shape shown in FIG.

Further, a silicon oxide film-based second interlayer insulating film (19) is deposited in a thickness of about 1.5 μm to 1.8 μm. Polishing is started from this state. By this polishing, the upper part of the step of the second interlayer insulating film (19) is selectively removed, and when the stopper film (20) is exposed, a flat surface (22) as shown in FIG. 6 is obtained. This stopper (20)
Since the film has a sufficiently low polishing rate as compared with the second interlayer insulating film as described in the first embodiment and the reference example, the upper electrode (18) is not exposed and polished.

The difference between the second embodiment, the first embodiment and the reference example is that in the first embodiment and the reference example, the stopper film (20) is not disposed immediately above the upper electrode, and the stopper film (2
0) and the upper electrode (18) with an interlayer insulating film interposed. In the second embodiment, since the interlayer insulating film is eliminated, the total height of the interlayer insulating films constituting the entire device is reduced, and the contact formed in the interlayer insulating film is reduced in depth. While its formation is easy,
There is an advantage that the contact resistance is reduced.

Third Embodiment Next, a third embodiment will be described. In the third embodiment, in the polishing of the second embodiment (FIG. 6), the film loss of the second interlayer insulating film (19) around the stopper film (20) is large, and the flatness is higher than in the case of FIG. This is a method for improving the flatness when a shape having an inferior shape is formed. As a shape having poor flatness, there is a shape as shown in FIG.
From this state, only the stopper film (20) not covered with the second interlayer insulating film (19) is selectively removed by etching.

When a silicon nitride film, for example, is used as the stopper film (20) as in the embodiments and reference examples described above, the stopper film (20) not covered with the second interlayer insulating film by hot phosphoric acid is used. ) Is removed as shown in FIG. Thereafter, a silicon oxide film-based third interlayer insulating film (21) is deposited to a thickness of about 0.2 μm to 0.3 μm. According to the third embodiment, after polishing is completed, the stopper film (2
0) and the step between the second interlayer insulating film (19) is 0.2 μm
Even if a flat surface (2
2) can be formed.

As an advantage of the third embodiment, in addition to the fact that a substantially flat surface formed by polishing can be made flatter, a stopper film (20) is formed on a capacitor portion and between adjacent capacitor portions. Since the silicon nitride film does not remain, no stress is applied to the capacitor. As the polishing stopper film, a material that is suitable for processing as a material of the film, that is, a film that is hard and easily generates stress is likely to be selected. Therefore, it is convenient from the viewpoint of device characteristics to remove the stopper film which is a source of stress. In particular, in order to increase the capacitance, a structure with less stress is preferable when a capacitance insulating film (17) is not a laminated structure of a nitride film and an oxide film but a tantalum oxide film having a higher relative dielectric constant than this. It is. In a high-dielectric-constant film, when a stress is applied, the leakage current increases. Therefore, the less the stress, the lower the leakage current and the better the retention characteristics of the memory.

Embodiment 4 Finally, a fourth embodiment will be described. Although the reference example and the first to third embodiments show the case where an insulating film is used as a stopper film, the fourth embodiment will explain the case where a conductive stopper film is used for this.
Instead of the stopper film (20a) on the upper electrode member (18a) shown in FIG. 5A, a titanium nitride film formed by, for example, a sputtering method or a CVD method is grown on the entire surface of the wafer as a conductive stopper film. Further, as described in the second embodiment, the upper electrode, the capacitor insulating film, and the conductive stopper film are patterned into a capacitor shape. FIG. 8A shows a structure after a second interlayer insulating film (19) of a silicon oxide film is grown on this shape. Here, (20a) is a conductive stopper film. The second interlayer insulating film (19) may be formed in a thickness of about 1.5 μm to 1.8 μm as in the previous embodiments.

Polishing is started from the state shown in FIG. By stopping polishing when the conductive stopper film (20a) is exposed, a first flat surface (22a) as shown in FIG. 8B can be formed. In this case, since the stopper film has conductivity, it is not possible to form a wiring in a further upper layer as it is, and as shown in FIG.
By forming the silicon oxide film-based third interlayer insulating film (21), a final second flat surface (22b) can be formed.

In this embodiment, the conductive stopper film (2
Although a titanium nitride film was used as 0a), the function as a stopper for polishing is superior to the stopper film using a silicon nitride film described above, so that the effect of protecting the capacitance portion can be increased. Further, when a high dielectric constant film is used as the capacitor insulating film, a metal-based film is used as the upper electrode.

In these embodiments, the description has been made up to the planarization of the interlayer insulating film on the capacitor. However, in the formation of the memory cell, a contact hole is opened in this interlayer insulating film.
A process of forming a wiring mainly made of aluminum is required. Further, in some cases, another or more wirings are formed in the upper layer. The planarization method of the present invention can be applied to a case where the interlayer insulating film on the wirings arranged in such an array is flattened, and furthermore, a flat surface suitable for forming an upper layer wiring is formed. It is possible to form. Further, among the silicon oxide film-based materials as an interlayer insulating film for planarization,
Although the BPSG film having reflow properties is used, the same effect can be obtained even when an oxide film which does not contain phosphorus and boron having small reflow properties, for example, an oxide film formed by plasma CVD or an oxide film formed by normal pressure CVD is used. Is obtained.

[0039]

According to the method for planarizing an interlayer insulating film of the present invention, a step of an interlayer insulating film between an array region and a peripheral region, which is a problem in a DRAM memory cell array or the like, can be removed, and a flat interlayer insulating film can be formed. Can be formed. This flat interlayer insulating film shape facilitates device formation such as wiring on the upper layer, and has the effect that the device can be miniaturized and highly integrated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of planarizing an interlayer insulating film according to a reference example in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of planarizing an interlayer insulating film according to a reference example in the order of steps.

FIGS. 3A and 3B are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to a reference example in the order of steps;

FIGS. 4A and 4B are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to a first embodiment of the present invention in the order of steps.

FIGS. 5A and 5B are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating a method of planarizing an interlayer insulating film according to a second embodiment of the present invention in the order of steps.

FIGS. 7A and 7B are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to a third embodiment of the present invention in the order of steps.

FIGS. 8A and 8B are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to a fourth embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating a method of planarizing an interlayer insulating film according to a fourth embodiment of the present invention in the order of steps.

FIGS. 10A and 10B are cross-sectional views showing a conventional planarization method using polishing in the order of steps.

FIG. 11 is a cross-sectional view showing a conventional planarization method by polishing in the order of steps.

12A and 12B are cross-sectional views of a conventional wiring and contact structure using a stopper film, and FIG.
It is sectional drawing of the contact part of a layer wiring. FIG. 2B is a cross-sectional view of a contact portion in which a conventional stopper film is not used.

FIGS. 13A to 13C are cross-sectional views showing a conventional planarization method by polishing using a stopper film in the order of steps.

FIGS. 14A to 14C are cross-sectional views showing a conventional planarization method by polishing using a stopper film in the order of steps.

FIG. 15 is a cross-sectional view of a memory device for describing a problem that occurs when a conventional planarization method using polishing using a stopper film is applied to the memory device.

FIG. 16 is a conceptual diagram for describing a polishing technique and a polishing method used in a reference example.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate 12 memory cell 13 lower electrode 14 memory cell array 15 bit line 16 first interlayer insulating film 17 capacitance insulating film 18 upper electrode 18a upper electrode member 19 second interlayer insulating film 20 stopper film 20a conductive stopper film 21 third interlayer Insulating film 22 Flat surface 22a First flat surface 22b Second flat surface 23 Depression 24 Resist 32 Element isolation 33a Source 33b Drain 34 Gate electrode 35 Wiring 36 First interlayer insulating film 37 Contact 38 Lower wiring 39 Second interlayer insulating film REFERENCE SIGNS LIST 40 step 51 first layer wiring 52 insulating film 53 contact hole 54 second layer wiring 55 columnar protrusion 56 support substrate 57 first layer wiring 58 etching stopper film 59 columnar protrusion forming member 59 a columnar protrusion 60 PSG film 61 polishing stopper Film 61a polishing stock Over the flat part 61b polishing stopper ridges 62 resist film 71 device array region 72 convex portion 73 stopper film 74 over-polishing region 81 rotates platen

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/304 321 H01L 21/8242 H01L 27/108 H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (4)

(57) [Claims] A step of forming an array of capacitive elements having a predetermined height in a main surface region of a semiconductor substrate; and stopping at least an upper portion of the array of the capacitive elements at a polishing speed that is significantly lower than an interlayer insulating film. Providing a layer, depositing an interlayer insulating film on the surface including the top of the stop layer, polishing and removing the interlayer insulating film until the stop layer is exposed, and then removing the stop layer by etching. Forming a flat surface. 2. A step of forming an array of capacitive elements having a predetermined height in a main surface region of a semiconductor substrate, and stopping at least an upper portion of the array of the capacitive elements at a polishing speed significantly lower than that of an interlayer insulating film. Providing a layer, depositing an interlayer insulating film on the surface including the top of the stop layer, polishing and removing the interlayer insulating film until the stop layer is exposed, and then removing the stop layer by etching; Forming a flat surface by depositing an interlayer insulating film thereon. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the stop layer having a significantly lower polishing rate than the interlayer insulating film is a silicon nitride film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the stop layer having a polishing rate significantly lower than that of the interlayer insulating film is a titanium nitride film.