JP2865441B2 - Vertical sync signal detection circuit and on-screen display circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing signal detecting circuit for a television receiver.

[0002]

2. Description of the Related Art Conventionally, vertical synchronization frequencies of 50 Hz and 60 Hz have been used.
A television receiver capable of coping with both vertical and horizontal frequencies, the 50/60 Hz discrimination circuit for the vertical synchronization signal has the following 2
There are two forms. 1. Video chroma IC (video signal processing and color signal processing
The decision circuit is built in the integrated circuit for use . 2. The vertical synchronizing signal of the video signal is input to the input port of the microcomputer port, and the microcomputer determines 50/60 Hz.

[0003]

If a 50 Hz / 60 Hz discriminating circuit for a vertical synchronizing signal is incorporated in a video chroma IC, the cost of the IC increases.

[0004] In addition, most of the channel selection microcomputers incorporated in the current television set include an on-screen display circuit, but these microcomputers use a vertical oscillation circuit to take on-screen display timing. A terminal for inputting a pulse from the circuit is provided. However, in the conventional circuit, 50 Hz / 60 Hz cannot be determined at this terminal, and a terminal for inputting a vertical synchronization signal of a video signal must be newly provided. For this reason, there is a disadvantage that an extra microcomputer port is required.

The present invention solves the above-mentioned problem. There is no need to incorporate a discrimination circuit into a video chroma IC, no need to provide an extra microcomputer port, and low cost.
It is an object of the present invention to provide a vertical synchronizing signal detection circuit capable of determining / 60 Hz.

[0006]

In order to solve the above-mentioned problems, a vertical synchronizing signal detection circuit according to the present invention comprises an OR circuit which outputs a vertical synchronizing oscillation pulse from a vertical synchronizing signal oscillation circuit and a vertical synchronizing pulse from a video signal. The synthesized signal is input to the vertical synchronizing signal input terminal of a TV channel selection microcomputer (with a built-in on-screen circuit), and the pulse interval is monitored, and 50 Hz and 60 Hz of the vertical synchronizing circuit are determined. It is configured as follows.

At the time of discrimination, the synthesized vertical synchronizing signal is arbitrarily divided into an even-numbered pulse and an odd-numbered pulse, and the time interval between the even-numbered pulse and the odd-numbered pulse is calculated in the microcomputer. Is determined with higher accuracy.

[0008]

In the circuit of the video chroma system, when a video signal of 60 Hz is input when the vertical synchronizing circuit is on the 50 Hz side, the composite signal described above is a mixture of 50 Hz and 60 Hz. The same applies to the case where a 50 Hz video signal is input when the vertical synchronization circuit is 60 Hz.

At this time, when an even pulse and an odd pulse are distinguished from any pulse of the synthesized signal and their time intervals are measured, one of them becomes 20 msec and the other becomes 16.7 msec.
msec (or 33.3 msec). When such a situation occurs, the microcomputer determines that 50/60 Hz switching is necessary, and switches the polarity of the 50/60 Hz switching signal.

Further, the microcomputer can grasp the current state of the vertical synchronization circuit based on such a judgment, so that the position of the on-screen display at 50 Hz and 60 Hz can be corrected by itself. Becomes

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a vertical synchronization signal detection circuit according to an embodiment of the present invention.
Shown in FIG. 1 shows an example in which an "OR" circuit as an OR circuit for synthesizing a vertical synchronization pulse from a vertical synchronization signal oscillation circuit and a vertical synchronization pulse from a video signal is added to a channel selection microcomputer having an on-screen display circuit. This is shown.

In FIG. 1, reference numeral 1 denotes a channel selection microcomputer having a built-in on-screen display circuit 3, and reference numeral 2 denotes an "OR" circuit which is the above-mentioned OR circuit. And the vertical synchronization pulse Vsync from the video signal are input and synthesized. Also, the channel selection microcomputer 1 has an IF synchronization signal IFsync.
And video sync signal VIDEOsync are input, and 50/60
Hz switching signal is output ("H" is 60Hz, "L" is
50 Hz).

In the above circuit, the synthesized vertical synchronizing pulse is input to the input terminal of the channel selection microcomputer 1, and an interrupt process is performed in the channel selection microcomputer 1 by this input. At this time, the time from interrupt processing to the next interrupt processing can be measured in combination with a timer inside the microcomputer.

As shown in the timing chart of FIG.
A pulse at an arbitrary time of the synthesized vertical synchronization pulse is represented by T1
(Odd number) and the following pulses are T2 (even number), T3 (odd number), T4 (even number), T5 (odd number),..., The pulse interval at each input is as follows: .

When a vertical sync pulse of only 50 Hz is input (hereinafter referred to as "determination A"): Todd + 2-Todd = 40 msec and Teven + 2-Teven = 40 msec When a vertical sync pulse of only 60 Hz is input (hereinafter, referred to as "decision A") Todd + 2−Todd = 33.3 msec and Teven + 2−Teven = 33.3 msec When a 50 Hz + 60 Hz vertical sync pulse is input (hereinafter referred to as “decision C”): Todd + 2−Todd = 20 msec and Teven + 2−Teven = 16.7 msec (33.3 msce) or Todd + 2−Todd = 16.7 msec (33.3 msce) and Teven + 2−Teven = 20 msec, where Todd is an odd number of Tn and Teven is Tn.
Indicates the even number of. By calculating Tn in this manner, it is possible to determine what condition the vertical sync pulse is in.

In this embodiment, the above-mentioned judgment A, judgment B, and judgment C are performed by software of a microcomputer, and the 50/60 Hz
Switching operation is realized. 3, 4, and 5 show flowcharts of the software.

FIG. 3 shows a general flowchart of the 50/60 Hz discrimination. Here, in the TV mode, the presence / absence of the IF synchronization signal IFsync is determined, and in the AV mode, the presence / absence of the video synchronization signal VIDEOsync is determined. If there is no synchronization signal, the 50/60 Hz discrimination flag is set to 50 Hz. Is output. And 50/60
Reset the check counter (RAM name = c_chk). If there is a synchronization signal, a 50/60 Hz switching signal is output according to the 50/60 Hz discrimination flag. When the above processing is completed, the 50/60 Hz discrimination flag indicates "50 Hz processing".
Or "60 Hz processing". A flowchart of the “50 Hz processing” is shown in FIG. 4, and a flowchart of the “60 Hz processing” is shown in FIG.

In the "50 Hz processing" of FIG. 4, first, the above-mentioned "determination A" is performed, and if it is determined that the input is only 50 Hz, the check counter (c_chk) is decremented (-1) when it is not 0. For other inputs,
“Decision C” is performed. If it is determined that there is an input of 50 Hz + 60 Hz, the check counter (c_chk) is incremented (+1).

After the above processing, the check counter (c_
chk) is determined. If c_chk ≧ 20, reset c_chk and set the 50/60 Hz discrimination flag to 60H
Then, the process is terminated.

In "process 60 Hz" in FIG. 5, first, the above-mentioned "judgment B" is performed, and if it is determined that the input is only 60 Hz, it is decremented (-1) when the check counter (c_chk) is not 0. . In the case of other inputs, “determination C” is performed. If it is determined that there is an input of 50 Hz + 60 Hz, the check counter (c_ch)
k) is incremented (+1).

After the above processing, the check counter (c_
chk) is determined. If c_chk ≧ 20, reset c_chk and set the 50/60 Hz discrimination flag to 50H
Then, the process is terminated.

When the state of the 50/60 Hz flag is changed in this way, the check counter always outputs 50 Hz + 60 H.
Since it has been confirmed that the state of z has continued 20 times or more, the accuracy of the determination is extremely high and no error occurs.

The microcomputer 1 selects 50/50 by the above processing.
The output of the 60 Hz switching signal can be determined, and based on the information, the on-screen display circuit 3 operates at 60 Hz at 60 Hz.
The position of the on-screen display at Hz can be corrected.

[0024]

As described above, according to the present invention, the switching of the vertical synchronizing signal at 50/60 Hz, which is a very important factor in a multi-system compatible television, requires the discrimination circuit to be incorporated in the video chroma IC. There is no need to provide an extra microcomputer port, and it can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a vertical synchronization signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing vertical synchronization signals of 50 Hz, 60 Hz, and 50 Hz + 60 Hz.

FIG. 3 is a general flowchart of microcomputer software.

FIG. 4 is a flowchart of a 50 Hz process.

FIG. 5 is a flowchart of processing at 60 Hz.

[Explanation of symbols]

 1 channel selection microcomputer 2 OR circuit 3 on-screen display circuit

Claims (3)

(57) [Claims] (1) A vertical synchronization frequency of 50 Hz and 60 Hz.
TV receiver that can handle
Oscillating pulse corresponding to the input video signal
Oscillation frequency according to the vertical synchronization frequency of the input video signal.
Group and vertical synchronizing signal oscillator for generating switching the wave number, and an OR circuit for synthesizing the vertical sync pulses from the vertical synchronization oscillation pulses and a video signal from the vertical synchronization oscillation circuit, the composite signal from the OR circuit To monitor the pulse interval contained in it and output a signal related to the pulse interval
Monitoring means to calculate a signal related to the pulse interval from the monitoring means
Vertical synchronization signal frequency in the vertical synchronization signal oscillation circuit
And the sync signal frequency of the input video signal.
Determining means for outputting another signal; and oscillating the vertical synchronizing signal oscillating circuit according to the determining signal.
Switching control means for switching a frequency, wherein a synchronizing signal from the vertical synchronizing signal oscillating circuit and an input video signal are provided.
Discrimination when the frequency of the synchronization signal from the signal is different
The switching control means is controlled by a discrimination signal from the means.
The oscillation frequency of the vertical synchronizing signal oscillation circuit is
I will switch it so that it is the same as the signal synchronization signal frequency
Unishi was vertical synchronizing signal detecting circuit. Wherein arbitrarily determined even-numbered and odd-numbered combined pulse signal at the OR circuit, a calculating means for calculating the even-numbered time interval and the odd-numbered time interval, the calculation result of the calculating means The vertical synchronization signal
Of vertical sync signal frequency and input video signal
Determines whether the frequency is the same as the frequency of the synchronization signal and outputs a determination signal
Determining means for oscillating the vertical synchronizing signal oscillating circuit according to the determining signal;
2. The vertical synchronizing signal detecting circuit according to claim 1 , further comprising: switching control means for switching a frequency . 3. A vertical synchronizing signal detecting circuit according to claim 1.
Of on-screen display on a television receiver
Switching display timing from the vertical synchronization signal detection circuit
An on-screen display circuit, which is switched by a control signal .