JP2866129B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to image data processing.
The present invention relates to an image processing apparatus for distributing a binarization error generated at the time of a binarization process into image data of peripheral non-binarized pixels.

[Related Art] In recent years, in image processing apparatuses such as facsimile apparatuses and printers that perform binarization processing, an error diffusion method or an average error minimum method, which is an equivalent processing method, is widely known as a method of reproducing halftones. ing. In these binarization methods, when binarizing a pixel of interest, binarization processing is performed while distributing a generated quantization error to a plurality of peripheral pixels, thereby preserving the average density of an image and performing halftone processing. This is a technique for reproducing.

Further, in the error diffusion method, in terms of hardware scale, processing speed, and the like, the distribution coefficient of quantization errors to peripheral pixels and the sum of coefficients are, as described in JP-A-61-52073, 2 It is often the value of the power of.

And in order to perform the error distribution operation by integer operation,
The processing of the calculation error which is a rounding error becomes a problem. That is,
When the calculation error is truncated, the density is not completely preserved, and problems such as deterioration in gradation occur.

Therefore, it is known from JP-A-1-284172 that complete density preservation is performed by distributing the calculation error generated by the integer calculation to one neighboring pixel.

[Problem to be Solved by the Invention] However, in the technique disclosed in Japanese Patent Application Laid-Open No. 1-284172, a calculation error is distributed to a pixel at one specific position. Has a disadvantage that it is not preferable.

In addition, a dedicated adder must be provided to add the calculation error, and there is a disadvantage that the circuit scale increases and the processing speed decreases.

The present invention has been made in consideration of the above-described problems of the related art, and can correct a calculation error at the time of error distribution without causing an increase in a circuit scale and a decrease in a processing speed.
Further, an object of the present invention is to provide an image processing apparatus capable of preventing generation of texture having directionality and obtaining a high-quality image, because an operation error is distributed to a plurality of pixels.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for storing image data
An image processing apparatus for distributing a binarization error generated in a binarization process to image data of peripheral non-binarized pixels, comprising: an input unit for inputting image data; Binarizing means for binarizing image data into binarized data; calculating means for calculating a binarization error generated by the binarizing processing of the binarizing means; Processing means for weighting the binarization error by a bit shift process to obtain a plurality of error data for a plurality of non-binarized pixels; and calculating the lower multiple bits of the calculation error generated by the bit shift process into data in bit units. Decomposing means for decomposing to obtain a plurality of bit data; and each of a plurality of error data obtained by the processing means for each image data of the plurality of unbinarized pixels Characterized in that by inputting the bit data of bits obtained by said decomposing means to each of a plurality of adders for adding and a correcting means for correcting the calculation error.

[Operation] In such a configuration, error data generated by the binarization processing is weighted by bit shifting to obtain a plurality of error data for a plurality of non-binarized pixels, and a plurality of lower-order bits generated by the bit shift processing are obtained. Decomposing the operation error into bit-unit data and inputting the bit-unit bit data to each of a plurality of adders for adding the error data to the respective image data of the plurality of non-binarized pixels. To correct the calculation error.

Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the binarization processing in this embodiment.

In FIG. 2, input density data 1a is input as image density data 22 for one pixel in synchronization with a rising edge of a page synchronization signal 20, a line synchronization signal 21 and an image clock 23, as shown in FIG. .

11a to 11f shown in FIG. 1 are error components distributed to peripheral pixels.
An adder for adding ED / 8 and an operation error e ₀ e ₁ e ₂ (binary number), where X and Y are addition inputs, CI is a carry input, and Z is
Is an addition output. By these adders 11a to 11f,
The calculation shown in the equation is performed, and the quantization error and the calculation error are added (distributed).

Z = (X + Y + CI) 12a to 12e are one-pixel delay elements such as latches. Reference numeral 16 denotes a delay processing unit, which is a line memory that is four pixels less than one line length. The delay processing unit 16 stores the input density data 1a corresponding to the peripheral pixel on the next line (sub-scanning direction) for the target pixel "*" shown in FIG.

Here, the input density data 1a column is sequentially one pixel delay element
12a to 12c, adders 11a to 11c, and a line delay processing unit 16, while passing through them, add a quantization error caused by binarization that has occurred in surrounding pixels before that. And
The input density data _ID including the binarization error of the surrounding pixels is 2
When the binary data 1b is input to the binarization processing unit 13, the binarized data 1b is compared with a predetermined threshold value T and binarized into simple binary data.

On the other hand, the quantization error calculator 14 that inputs the input density data _ID and the threshold T from the binarization processor 13 performs the calculation shown in the expression to calculate the quantum for the target pixel (the delay element 12e in FIG. 1). Error ED is obtained, and a bit shift processing unit described later
Output to 15.

However, I _A is the theoretical maximum density, T is the threshold.

Next, the quantization error ED due to the above-described binarization is input to the bit shift division processing unit 15, and is distributed to surrounding pixels according to each weight coefficient of a diffusion matrix as shown in FIG.
However, in this embodiment, the surrounding pixels corresponding to the weighting factor "2" of the diffusion matrix shown in FIG. 3 are the delay elements 12b and 12e shown in FIG. 1, and the quantization error ED is calculated by summing the weighting factors. The multiplication is carried out by inputting ED / 8 divided by as an error component to a double (× 2) input Y of the adders 11b and 11f.

That is, the error component distributed in this embodiment is ED / 8, and this division processing is performed by three bit shifts (the lower three bits are discarded). At the same time, the shifted lower three bits e ₂ e ₁ e ₀ (binary number) become a rounding error.

Next, a process of distributing the lower three bits of calculation error data (e ₂ e ₁ e ₀ ) ₂ , which is a rounding error, to surrounding pixels will be described below.

In the conventional method, the operation error data is combined as shown in FIG. 4 and added to adjacent pixels to preserve the density when binarizing. In the present embodiment, however, as shown in FIG. To
The operation error data is decomposed in bit units and distributed to peripheral pixels. At this time, the carrier input CI of each of the adders 11a to 11f shown in FIG. 1 and the lower free bit input of the Y input of the adders (11b, 11f) by shift multiplication are effectively used, as shown in FIG. The operation error data can be distributed to the surrounding pixels according to the distribution matrix, and it is not necessary to add a new adder.

FIG. 6 shows how the calculation error is diffused by the distribution matrix shown in this embodiment. FIG. 6 does not show the diffusion ratio (FIG. 3) but shows the actual diffusion amount. As shown in the figure, it can be seen that the value of the operation error (e ₂ e ₁ e ₀ ) ₂ is equal to the sum of the distributed values, and that the density is preserved.

Through the above processing, the density of the input image is preserved, and a good pseudo halftone image is obtained.

Next, another embodiment according to the present invention will be described below with reference to the drawings.

The diffusion matrix of the quantization error and the distribution matrix of the operation error are not limited to the case shown in the above-described embodiment. For example, when the diffusion matrix of the quantization error is as shown in FIG. The lower four bits of the ED (e ₃ e ₂
It is also conceivable to distribute e ₁ e ₀ ) ₂ to peripheral pixels using a distribution matrix as shown in FIG. Also in this case, similarly, the distribution matrix of the arithmetic error is designed so that the carry input of the adder for distributing the quantization error and the empty input lower than the adder input generated by the bit shift multiplication are effectively used. It is not necessary to add a new adder for distributing the calculation error.

As described above, it is possible to handle all cases where the sum of the weight divisors of the diffusion matrix is a power of two.

In the above-described embodiment, the error diffusion method is used. However, the present invention is not limited to this. For example, the same effect can be obtained by using the average error minimization method.

[Effects of the Invention] As described above, according to the present invention, it is possible to correct a calculation error at the time of error distribution without causing an increase in circuit scale and a reduction in processing speed, and further reduce the calculation error to a plurality of pixels. , It is possible to prevent the generation of texture having directionality and obtain a high-quality image.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration in this embodiment, FIG. 2 is a timing chart of each image signal, FIG. 3 is a diagram showing a diffusion matrix of a quantization error shown in this embodiment, and FIG. FIG. 5 is a diagram showing a calculation error distribution matrix in this embodiment, FIG. 6 is a diagram showing a state of calculation error distribution in this embodiment, and FIG. FIG. 8 is a diagram showing a diffusion matrix of quantization errors in the embodiment, and FIG. 8 is a diagram showing a calculation error distribution matrix in another embodiment. In the figure, 11a to 11f ... adder, 12a to 12e ... one pixel delay element, 13 ... 2
A quantization processing section, a quantization error calculation section, a bit shift division processing section, and a line delay processing section.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 G06T 5/00

Claims (1)

(57) [Claims] 1. An image processing apparatus that generates a binary image generated in a binarization process of image data.
An image processing apparatus for distributing a binarization error to image data of peripheral non-binarized pixels, comprising: an input unit for inputting image data;
Binarization means for performing binarization processing on the digitized data; operation means for calculating a binarization error generated by the binarization processing of the binarization means; Processing means for performing weighting processing by shift processing to obtain a plurality of error data for a plurality of non-binarized pixels; and calculating a plurality of lower-order arithmetic errors generated by the bit shift processing into data in bit units to obtain a plurality of error data. Decomposing means for obtaining bit data; and a plurality of adders for adding each of the plurality of error data obtained by the processing means to each image data of the plurality of non-binarized pixels. An image processing apparatus comprising: a correction unit configured to correct the calculation error by inputting bit data in bit units obtained by the decomposition unit.