JP2867518B2 - Method of manufacturing self-aligned thin film transistor matrix - Google Patents

Description

〔Overview〕

A self-aligned thin film transistor matrix used for driving a liquid crystal display device and the like. The purpose of the present invention is to make it possible to easily cut an active semiconductor layer between a gate electrode and a gate bus line by a simple manufacturing process. In a method of manufacturing a thin film transistor matrix having a pixel driving thin film transistor arranged in a matrix on a substrate and a gate bus line commonly connecting the gate electrode of the thin film transistor by a self-alignment method, the gate electrode of each thin film transistor is provided. And the gate bus line are connected by a plurality of connecting portions, and
When each of the connection portions is irradiated with light from the back side of the transparent insulating substrate to perform back exposure, the connection portion is formed to have a width in which light wraps around the entire connection portion, and during the subsequent back exposure step, The resist film on the connection portion was made photosensitive. The present invention relates to a self-aligned thin film transistor matrix used for driving a liquid crystal display device or the like. The thin film transistor (TFT) used for driving the above-mentioned liquid crystal display device or the like is required to be small in size in order to increase the pixel occupancy, and in order to realize this, a back exposure method using a gate electrode as a mask is required. A self-aligned type for forming source / drain electrodes is indispensable.
In addition, in terms of manufacturing cost and manufacturing yield, a simple manufacturing process is required. [Prior Art] Conventionally, an active semiconductor layer remains not only on an element portion but also on a gate bus line, but this operating semiconductor layer is cut between a channel region and a gate bus line. It is necessary. The main part of the structure of the conventional thin film transistor matrix is
This will be described with reference to FIGS. FIGS. 2B and 2C are cross-sectional views taken along line bb and cc in FIG. In order to obtain the above-mentioned conventional structure, as shown in FIG. 1B, a Ti film 2 is formed on a transparent insulating substrate 1 and patterned to form a gate electrode G and a gate bus line commonly connecting the same. Form the bottom layer of GB. Next, the gate insulating film
3. The operation semiconductor layer 4 and the channel protection film 5 are stacked, and unnecessary portions thereof are removed. Thus, the pattern of the gate electrode G and the gate bus line GB shown in FIG. Next, after forming the contact layer 6 and the electrode metal layer 7, element isolation is performed, and further, a pixel electrode E made of a transparent conductive film is formed. Thereafter, the region of the gate electrode G and the region of the gate bus line GB (the region indicated by hatching (e)) are masked, and the region exposed therebetween is etched to form a gate insulating film. The layer below the layer 3 is removed, and the film laminated thereon is removed up to the active semiconductor layer 4. Cutting the operating semiconductor layer 4 in this manner is necessary to cut off a sneak current from an adjacent drain due to a reduction in the resistance of the channel portion when the TFT is turned on. [Problems to be Solved by the Invention] In the above-mentioned conventional structure and manufacturing method, the operating semiconductor layer 4
Requires a photomask process for cutting the wafer, which complicates the manufacturing process and increases the risk of lowering the manufacturing yield. SUMMARY OF THE INVENTION It is an object of the present invention to enable an operating semiconductor layer to be easily cut between a gate electrode and a gate bus line by a simple manufacturing process. [Means for Solving the Problems] According to the present invention, a gate bus line GB and a gate electrode G of each thin film transistor are connected by a plurality of connecting portions, as can be seen from the configuration explanatory view of the present invention in FIG. And, when the back surface exposure is performed, each of the connection portions is formed to have a width in which light wraps around the entire connection portion, and during the subsequent back surface exposure step, the resist film of the connection portion upper layer is exposed. Made it possible. [Operation] With the above configuration, when a self-alignment method of exposing a positive photoresist by back exposure using the gate electrode G and the gate bus line GB as a mask is performed, the photoresist in the upper layer of the connection portion J is obtained. Is exposed, and no resist film is formed on this portion. Therefore, in the step of etching the channel protective film 5 using the photoresist film as a mask, the channel protective film 5 is removed at the connection portion J, and the operating semiconductor layer 4 is exposed. As described above, since the channel protective film 5 does not exist at the connection portion J, there is nothing to mask the operation semiconductor layer 4 in the subsequent element isolation step. Therefore, in this step, the operation semiconductor layer 4 on the connection portion J is etched. Removed. As described above, the connection portion J
Since the upper operating semiconductor layer 4 is removed in a series of manufacturing steps without using a photomask, the manufacturing steps are simplified, and furthermore, the gate electrode and the gate bus line are connected to a plurality of connecting portions. By performing the connection, the risk of patterning failure of the connection portion due to dust or the like and the disconnection of the electrode of the connection portion lowering the yield can be greatly reduced. Embodiment An embodiment of the present invention will be described below with reference to FIG. In addition, the figure which attached -2 after the figure (a)-(e),
Figures marked with -3 and -3 respectively correspond to figures II-
FIG. 3 is a view taken in the direction of the arrow II, and is a diagram showing a cross section of the portion viewed in the direction of the arrows III-III.

[See FIGS. 2 (a) -1, (a) -2 and (a) -3] A Ti film 2 is formed on a glass substrate 1 by sputtering.
Is formed to a thickness of about 20 nm, unnecessary portions of the Ti film 2 are removed by using a CF ₄ -based plasma etching method, and a pattern of the gate electrode G and the gate bus line GB is formed. In this step, it should be noted that the width of each of the plurality of connection portions with the gate electrode G and the gate bus line GB is smaller than the width of the gate electrode G as shown in the drawing. The value is set to such a degree that the light wraps around the connection portion J and exposes the photoresist film in the back surface exposure step described later. In this embodiment, the width of each of the gate electrode G and each of the plurality of connection portions is about 5 μm and about 1 μm, respectively.
μm.

[See (b) -1, (b) -2, and (b) -3 in the figure] SiN film 3, a-Si film 4, SiO ₂ film 5 by plasma enhanced chemical vapor deposition (P-CVD). Is continuously formed. These films are a gate insulating film, a working semiconductor layer, and a channel protective film, respectively.

[See (c) -1, (c) -2, and (c) -3 in the figure) After applying a positive photoresist, the gate electrode G
Using the Ti film 2 constituting the gate bus line GB as a mask, light hν is irradiated from the back surface of the glass substrate 1 to form a resist film 10. By this step, a resist film 10 which is self-aligned with the gate electrode G and the gate bus line GB is formed. However, since the light goes around the inside of the Ti film 2 serving as a mask by about 0.5 μm, the photoresist film on the connection portion J having a width of about 1 μm is all exposed, and as shown in FIG. No resist film is formed.

[See (d) -1, (d) -2, and (d) -3 in the figure) Using the resist film 10 as a mask, the SiO ₂ film 5 is etched with a hydrofluoric acid-based etchant to form the channel protective film 5.
Is removed, and the surface of the underlying a-Si film 4 is exposed. According to this step, the channel protective film 5 remains on the gate electrode G and the gate bus line GB, but the connection portion J
Above is removed and the a-Si film 4 is exposed.

[See (e) -1, (e) -2, (e) -3 in the figure) Next, an n ⁺ a-Si film (contact layer) 6 doped with P (phosphorus) is formed at a substrate temperature of 120 ° C. Then, a Ti film (metal electrode film) 7 is formed thereon at room temperature. After that, the resist film 10 is dissolved and removed with acetone, and the resist film 10 is removed.
The n ⁺ a-Si film 6 and the Ti film 7 adhering on 10 are lifted off and removed. Further, a resist film (not shown) for element isolation is formed,
Etching is performed using this as a mask, and Ti film 7, n ⁺ a-Si
The exposed portions of the film 6 and the a-Si film 4 are removed, and the source electrode is removed.
S, a drain electrode D are formed. Since the a-Si film 4 on the connection portion J is exposed as described above, it is removed in this etching step. As described above, in the present embodiment, the a-Si film 4 which is formed astride the gate electrode G and the gate bus line GB at first,
It is separated at the connection portion J. Thereafter, a pixel electrode and a drain bus line are formed to complete a thin film transistor matrix according to the present invention. As described above, in the thin film transistor matrix manufactured in the present embodiment, since the a-Si film 4 as the operating semiconductor layer is separated at the connection portion J, a signal is applied to the adjacent drain bus line DB during actual driving. From the gate electrode G, and a good display can be obtained. Moreover, a photomask for separating the active semiconductor layer is not required, so that the manufacturing process is simplified and the manufacturing yield is improved. [Effects of the Invention] As described above, according to the present invention, a photomask and an isolation step for separating an active semiconductor layer are not required, the steps are simplified, and the risk of lowering the production yield is reduced. Good display can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the structure of the present invention, FIG. 2 is an explanatory view of an embodiment, FIG. 3 is an explanatory view of a conventional problem, in which 1 is a transparent insulating substrate (glass substrate) and 2 is a gate metal. Film (Ti film), 3 is a gate insulating film (SiN film),
4 is an operating semiconductor layer (a-Si film), 5 is a channel protective film (SiO ₂ film), 6 is a contact layer (n ⁺ a-Si film), 7 is a metal film (Ti film), G is a gate electrode, GB indicates a gate bus line, S indicates a source electrode, D indicates a drain electrode, E indicates a pixel electrode, and DB indicates a drain bus line.

──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-3-105324 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1 / 136 G02F 1/1343

Claims (1)

(57) [Claims] 1. A method of manufacturing a thin film transistor matrix having pixel driving thin film transistors arranged in a matrix on a transparent insulating substrate and a gate bus line commonly connecting gate electrodes of the thin film transistors by a self-alignment method. In the above, the gate electrode of each thin film transistor and the gate bus line were connected by a plurality of connecting portions, and each of the connecting portions was irradiated with light from the back side of the transparent insulating substrate to perform back exposure. A method for producing a self-aligned thin film transistor matrix, wherein the resist film on the connection portion is formed to have a width such that light wraps around the entire connection portion so that the resist film on the connection portion can be exposed in a subsequent back exposure step. .