JP2867935B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates relates to a method of manufacturing a semiconductor device, in particular EPROM cells, EEPROM cells,
The present invention relates to a method for manufacturing a structure of a nonvolatile memory cell having a floating gate and a control gate such as a flash memory cell.

[0002]

2. Description of the Related Art FIGS. 13 to 15 are sectional views showing the steps of a method for manufacturing a conventional nonvolatile memory cell such as an EPROM cell or a flash memory. In these drawings, FIG. It is sectional drawing of a parallel direction, (B) is sectional drawing of a direction perpendicular | vertical to the control gate formed.

First, as shown in FIG. 13, after forming an element isolation region 2 on a silicon substrate 1, that is, after forming a field silicon oxide film by a selective thermal oxidation method (LOCOS method) or the like, a tunnel oxide film is formed. 3 is formed by thermal oxidation, a first polycrystalline silicon film 17 serving as a floating gate is formed by a CVD method, and a photoresist 19 serving as a mask for patterning the floating gate is applied thereon.

Next, as shown in FIG. 14, a photoresist 19 is patterned by a lithography technique, and using this as a mask, the first polycrystalline silicon film 17 is selectively etched to form a floating gate in a first direction. A shape (a cross section shown in FIG. 3A) is formed.

Next, as shown in FIG. 15, after removing the photoresist 19, an insulating film 15 is formed, a second polycrystalline silicon film 18 serving as a control gate is formed, and a photoresist (not shown) is formed. ) Is used as a mask to selectively etch the second polycrystalline silicon film 18, the insulating film 5, and the first polycrystalline silicon film 17 sequentially, so that the second polycrystalline silicon film 18, the first polycrystalline silicon film 17, and the second polycrystalline silicon film 17 are perpendicular to the first direction. Is formed (cross section shown in (B)), and the photoresist used in this step is removed.

That is, in FIG. 15, the floating gate 14 is obtained from the first polycrystalline silicon film 17 and
The control gate 16 is obtained from the polycrystalline silicon film 18 of FIG.

In this conventional technique, the first polycrystalline silicon film serving as a floating gate is etched on a device isolation region using a photoresist as a mask.
After the vertical step of the floating gate 14 is formed and the etching for forming the cell is performed, the remaining 11 of the fence-shaped insulating film by the insulating film 15 is generated as shown in FIG.

When the control gate 16 is etched to form a shape, if the necessary amount of etching is performed to remove the remaining portion 11 of the insulating film, the element isolation region is simultaneously etched, as shown in FIG. Then, a depression 12 is generated in the element isolation region 2.

Another conventional technique is disclosed in Japanese Patent Application Laid-Open No. 2-15 / 1990.
As disclosed in Japanese Unexamined Patent Application Publication No. 0071, there is a method of etching a silicon substrate in a region where a gate is to be formed to provide a concave portion. In this case, too, since a floating gate is formed by etching using a resist as a mask, The same problem as in the above-described related art occurs.

[0010]

As described above, in the conventional method of manufacturing an EPROM cell, a flash memory cell, or the like, since a floating gate is patterned by a resist mask to form a shape, a floating gate is formed on an element isolation region. A vertical step of the gate is formed, and an insulating film for insulating the floating gate and the control gate remains in a fence shape, causing particles, thereby causing a problem in device characteristics and reliability.

On the other hand, when the above-mentioned fence-shaped residue of the insulating film is etched, the insulating film is formed of a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film. In this case, since the silicon oxide film in the element isolation region is simultaneously etched, the element isolation region is excessively etched, which causes a problem in device characteristics and reliability.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device and a manufacturing method which solve the above problems and improve device characteristics and reliability.

[0013]

[0014]

[0015]

[0016]

Means for Solving the Problems The feature of the present invention includes the steps of forming a field silicon oxide film for partitioning the element region on a semiconductor substrate, forming a pattern of silicon oxide film on the upper surface of the field silicon oxide film A step of forming a tunnel insulating film on the element region, and a step of forming a first conductive film to be a floating gate;
A step of an upper surface of the first conductive film planarizing the first conductive film so that the upper surface and the same surface of the silicon oxide film, the silicon from flattened first conductive film
Forming an insulating film over the oxide film, forming a second conductive film serving as a control gate on the insulating film, and using the photoresist as a mask to form the second conductive film;
Dry etching the film, the insulating film and the first conductive film.
Forming a control gate and a floating gate from the second and first conductive films , respectively , by selectively and sequentially etching by a etching method.

Here, the flattened shape of the floating gate in one direction is preferably formed in a self-aligned manner by the element isolation region or the insulating layer. Further, the planarization of the first conductive film serving as the floating gate can be performed by a CMP method.

As described above, in the present invention, since the upper surface of the floating gate is flattened on the same plane as the upper surface of the element isolation region, an insulating film between the floating gate and the control gate is formed on the flat surface. Fence-shaped rest,
Alternatively, excessive etching of the element isolation region does not occur.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a structural diagram showing a memory cell according to a technique related to the present invention. By a selective thermal oxidation (LOCOS) method using an oxidation resistant film such as a silicon nitride film as a mask, a field silicon oxide film partially buried in the main surface of the silicon substrate 1 and partially protruding from the substrate is formed in the element isolation region. 2 and adjacent to the element isolation region 2, it is possible to inject carriers into the floating gate or tunnel out carriers from the floating gate onto the element region of the silicon substrate defined by the element isolation region 2. Tunnel insulating film 3 is formed of a thin silicon thermal oxide film.

The floating gate 4 formed on the tunnel insulating film 3 on the device region of the silicon substrate extends over the tapered end of the device isolation region 2, but on the flat upper surface of the device isolation region 2. However, the upper surface of the element isolation region 2 and the upper surface of the floating gate 4 are flush with each other. The shape of the floating gate 4 in the direction of AA 'in FIG. 1, that is, the shape in the direction perpendicular to the direction between the source region and the drain region of the memory cell is determined by the pattern of the element isolation region 2.

Since the upper surface of the floating gate 4 is flattened so as to be flush with the upper surface of the element isolation region 2, the insulating film 5 is also flat from the upper surface of the floating gate 4 to the upper surface of the element isolation region 2. A control gate 6 is formed thereon as a film.
In the BB 'direction in FIG. 1, that is, in the direction between the source region and the drain region of this memory cell, the control gate 6, the insulating film 5, and the floating gate 4
Are patterned in the same shape.

FIGS. 2 to 6 are views for explaining a method of manufacturing the memory cell of FIG. 1 in the order of steps. In each of the drawings, (A) is a process sectional view corresponding to the AA 'section of FIG. FIG. 2B is a process sectional view corresponding to a section taken along line BB 'of FIG.

First, as shown in FIG. 2, after a device isolation region 2 is formed on a silicon substrate 1 by a LOCOS method, a tunnel insulating film 3 is formed by thermal oxidation.

Next, as shown in FIG. 3, a first polycrystalline silicon film 7 serving as a floating gate is formed by a CVD method. At this time, the first polycrystalline silicon film 7 is formed on the tunnel insulating film 3 so as to protrude from the same plane as the element isolation region 2.

Next, as shown in FIG. 4, the first polycrystalline silicon film 7 is polished by CMP (chemical / mechanical polishing) until it is flush with the upper surface of the element isolation region 2.

Next, as shown in FIG. 5, after forming an insulating film 5 for insulating between the control gate and the control gate by CVD, a second polycrystalline silicon film 8 serving as a control gate is formed by CVD. Further, a photoresist 9 serving as an etching mask when forming the gate structure of the cell is patterned by lithography.

Next, as shown in FIG.
Using the second polycrystalline silicon film 8 and the insulating film 5 as masks
Then, the first polycrystalline silicon film 7 is selectively and sequentially etched by a dry etching method, and then the photoresist 9 is removed, whereby the memory cell in the state of FIG. 1 is obtained.

Thereafter, using the stack gate structure and the element isolation region as a mask, an impurity of the conductivity type opposite to that of the substrate is introduced into the substrate to form source and drain regions, and an interlayer insulating film and a wiring layer are formed. Thus, a memory semiconductor device in which a large number of the memory cells are arranged is obtained.

FIG. 7 is a structural diagram showing a memory cell according to an embodiment of the present invention. In FIG. 7, parts having the same or similar functions as those in FIG.

In FIG. 7, a silicon oxide film 10 is formed as an insulating layer pattern on the upper surface of the element isolation region 2 formed of a field silicon oxide film formed by a selective thermal oxidation method to form a step portion as a whole. I have.

That is, the lower part adjacent to the element region of the silicon substrate is the element isolation region 2 of the field silicon oxide film.
The floating gate 4 is formed from the upper part of the tunnel insulating film 3 in the element region to the lower part of the element isolation region, and the floating gate 4 is separated from the element region. The upper surface is flattened so as to be flush with the upper surface of the silicon oxide film 10 constituting the upper step. Thereby, the insulating film 5 formed from the upper surface of the floating gate 4 to the upper surface of the silicon oxide film 10 is a flat film.

FIGS. 8 to 12 are drawings for explaining the manufacturing method according to the embodiment of the present invention in the order of steps. In each drawing, (A) is a sectional view taken along the line AA 'of FIG. FIG. 8B is a corresponding process cross-sectional view, and FIG. 8B is a process cross-sectional view corresponding to a BB ′ cross-section in FIG. 7.

First, as shown in FIG. 8, an element isolation region 2 is formed on a silicon substrate 1 by a LOCOS method.
A silicon oxide film 10 is formed by the VD method.

Next, as shown in FIG.
Using silicon as a mask, the silicon oxide film 10 is selectively etched to form a pattern of the silicon oxide film 10.

Next, as shown in FIG. 10, after forming the tunnel insulating film 3 by thermal oxidation, a first polycrystalline silicon film 7 serving as a floating gate is formed by a CVD method. At this time, the first polycrystalline silicon film 7 is formed on the tunnel insulating film 3 with a thickness protruding from the same plane as the silicon oxide film 10.

Next, as shown in FIG. 11, the first polycrystalline silicon film 7 is polished by the CMP method until it is flush with the upper surface of the silicon oxide film 10.

Next, as shown in FIG. 12, after an insulating film 5 serving as an insulating film with a control gate is formed by a CVD method, a second polycrystalline silicon film 8 serving as a control gate is formed by a CVD method. Using the photoresist as a mask, the second polycrystalline silicon film 8, the insulating film 5, and the first polycrystalline silicon film 7 are selectively and sequentially etched by a dry etching method, and then the photoresist is removed. Memory cell in the state shown in FIG.

[0039]

[0040]

[0041]

As described above, according to the present invention, the floating gate is formed by the polysilicon film planarized on the same plane as the element isolation region or the insulating layer on the element isolation region. There is no problem of generation of a fence-like residue of the insulating film when processing the gate. Alternatively, there is no problem of generation of a dent in the element isolation region due to removal of the fence-shaped residue. Therefore, a semiconductor device with improved device characteristics and reliability can be obtained.

Further, a step portion made of an insulating layer is provided on the element isolation region, and the floating gate is planarized on the same surface as the upper surface of the insulating layer. It is also possible to obtain an advantage that a large capacitance ratio to the gate capacitance can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a memory cell according to a technique related to the present invention.

FIG. 2 is a sectional view showing one step of a method for manufacturing the memory cell of FIG . 1 ;

FIG. 3 is a sectional view showing a step continued from FIG. 2;

FIG. 4 is a sectional view showing a step continued from FIG. 3;

FIG. 5 is a sectional view showing a step continued from FIG.

FIG. 6 is a sectional view showing a step continued from FIG. 5;

FIG. 7 is a diagram showing a structure of a memory cell according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing one step of the manufacturing method according to the embodiment of the present invention.

FIG. 9 is a sectional view showing a step continued from FIG. 8;

FIG. 10 is a sectional view showing a step continued from FIG. 9;

FIG. 11 is a sectional view showing a step continued from FIG. 10;

FIG. 12 is a sectional view showing a step that follows the step shown in FIG. 11;

FIG. 13 is a cross-sectional view showing one step of a conventional manufacturing method.

FIG. 14 is a sectional view showing a step continued from FIG. 13;

FIG. 15 is a sectional view showing a step continued from FIG. 14;

FIG. 16 is a diagram showing a problem of the memory cell of the related art.

FIG. 17 is a diagram showing another problem of the memory cell of the related art.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 element isolation region 3 tunnel insulating film 4, 14 floating gate 5, 15 insulating film 6, 16 control gate 7, 17 first polycrystalline silicon film 8, 18 second polycrystalline silicon film 9, 19 photo Resist 10 Silicon oxide film 11 Remaining insulating film 12 Depression in element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/78 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A fee for dividing an element region on a semiconductor substrate.
Forming a field silicon oxide film, the field
Forming a pattern of silicon oxide film on the upper surface of the silicon oxide film, forming a tunnel insulating film on the element region, forming a first conductive film to be the floating gate, the first sheet top surface of the conductive film wherein
Flattening the first conductive film so as to be flush with the upper surface of the silicon oxide film , and forming an insulating film from the flattened first conductive film to the silicon oxide film. a step for forming a second conductive film serving as a control gate on said insulating film, and a mask a photoresist
Then, the second conductive film, the insulating film, and the first
Selectively and sequentially etch conductive film by dry etching method
The method of manufacturing a semiconductor device characterized by a step of it <br/> respectively control gate and a floating gate shape formed from the second and the first conductive film. Unidirectional shape wherein said planarized floating gate method according to claim 1 semiconductor device, wherein a is a self-aligned manner by the silicon oxide film. 3. A process according to claim 1, the semiconductor device according to flattening of the first conductive film serving as the floating gate is characterized in that it is carried out by CMP.