JP2868938B2 - Method of forming semiconductor element isolation region - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor element isolation region for electrically isolating elements constituting a semiconductor integrated circuit built on a semiconductor substrate.

[0002]

2. Description of the Related Art The capacity of ultra LSIs such as DRAMs and SRAMs has been increasing at a rate of four times in three years.
Currently, 256 kbits and 1 Mbits of RAM are mainly produced. In addition, 4Mbit, 16
Mbit is being studied intensively, and is expected to evolve to 64 Mbit and 256 Mbit.

[0003] Such an improvement in the degree of integration within a limited chip area is brought about by miniaturization of each element constituting an integrated circuit. For example, currently 1Mbit
The minimum size of a MOS transistor used in a DRAM is about 1 μm, and it is certain that the size will be further reduced to 0.5 μm and 0.25 μm in the future. Similarly, reduction of the element isolation region is indispensable for miniaturization, and the isolation width is also one.
It has become necessary to narrow it to less than μm, and even less than 0.5 μm.

Generally, a selective oxidation method is used to form an element isolation region. In this method, a silicon nitride film covering a silicon substrate is patterned and opened, and the exposed silicon substrate surface is selectively oxidized to form a silicon oxide film as an insulating film. However, this method has caused the following problems with the reduction of the element region and the element isolation region. First, the oxidation of the silicon substrate proceeds to the area covered with the silicon nitride film during the selective oxidation, and the silicon oxide film called bird's beak spreads. Is becoming more difficult. Secondly, there is a problem that a long-time oxidation process is required, and a stress is applied to the silicon substrate due to volume expansion due to the oxidation, thereby causing defects and deteriorating device characteristics.

As an example of an element isolation method replacing the selective oxidation method having the above problem, a trench filling isolation method has been proposed.
FIG. 3 is a view for explaining the trench filling separation method. That is, a concave groove 22 is formed on the surface of the silicon substrate 21,
The inside of the groove 22 is filled with a silicon oxide film 23 or the like. Thereafter, the silicon oxide film 23 is formed by a vapor deposition method (CVD).
A thin film 24 having high fluidity, such as BPSG or SOG, is formed thereon to flatten the surface [FIG. 3 (a)].

Next, by etching the thin film 24 and the silicon oxide film 23 at the same speed until the silicon substrate 21 is exposed, the trench 2 in which the silicon oxide film 23 is
2 is formed [FIG. 3 (b)]. In this method, since only the concave groove portion of the silicon substrate processed using the resist pattern formed in the lithography process as an etching mask becomes the separation region, the separation region can be reduced to the limit of lithography.

[0007]

[Problems to be solved by the invention] By the way, [Fig.3
(A) Embedding of the silicon oxide film 23 shown in the step
The silicon oxide film 23 is sequentially formed from the side walls on both sides of the groove 22.
Is accumulated from both sides at the center of the groove 22.
The embedded silicon oxide film 23 hits and the embedding is completed.
Will be. Generally, silicon oxidation at the center of the groove 22
The film quality of the film 23 is very weak.
Etching rate is much faster than that deposited on flat areas.
No. However, at the end of the element isolation process, [Fig.3(B)]
As shown in FIG.
Is indispensable in the semiconductor device formation process because it is exposed on the surface
After the hydrofluoric acid solution treatment, the silicon in the center of the groove 22
Only the oxide film 23 is rapidly etched.3
A slit 26 as shown in FIG.

When the slit 26 is present, [FIG.3
(D)] As shown in FIG.
Even after the formation of 27 and 28,
The gate electrode material 29 remains without being etched and is
The gate electrodes 27 and 28 are short-circuited. Book
The invention solves the above-mentioned problems of the trench isolation method.
Semiconductor devices suitable for highly integrated semiconductor integrated circuits
An object of the present invention is to provide a method for forming an isolation region.

[0009]

Means for Solving the Problems In order to achieve the above object, the present invention provides a method for forming a first thin film on a silicon semiconductor substrate, and then forming a resist pattern on the first thin film. Using the resist pattern as a mask, removing the first thin film on the substrate serving as an element isolation region, etching the substrate in that portion to form a first groove having a predetermined depth, and then removing the resist pattern And then removing the first groove so as to fill the first groove.
After the second thin film is formed on the thin film, the second thin film is etched so that the first thin film is exposed and the second thin film inside the first groove remains. Forming a slit in the central portion of the second thin film remaining inside the groove by hydrofluoric acid solution treatment, and further etching anisotropically until the slit bottom reaches the substrate surface; The second thin film and the second thin film remaining on the side walls of the first groove are used as a mask to etch the substrate immediately below the slit to form a second groove. The second thin film remaining on the side wall of the first groove is removed, and then a third thin film is formed on the substrate so as to fill the first and second grooves. Forming a flowable fourth film, and then Serial is a substrate of the portion except in each groove characterized by having a step of etching the fourth thin film and the third film to expose.

[0010]

[0011]

According to the present invention, a slit reaching the substrate is formed in the central portion of the second thin film embedded in the first groove, and the second thin film remaining on the side wall is used as a mask to form the second thin film. Grooves can be formed. A third thin film is buried in the T-shaped groove formed by the first and second grooves, and an element isolation region is formed .

[0012]

[0013]

FIG. 1 and FIG. 2 are diagrams for explaining an embodiment of the present invention over time. Hereinafter, description will be made with reference to these drawings. First, after the surface of the silicon substrate 1 is thinly oxidized to form a silicon oxide film 2 of 100 to 300 mm,
A silicon nitride film 3 having a thickness of t ₁ is deposited by a low pressure CVD method. Subsequently, a resist pattern 4 defining an element isolation region is formed by a photolithography process. Here, the opening 4a of the resist pattern 4 is an isolation region, the width and W _1. In this embodiment, t ₁ = 0.12
μm, W ₁ = 0.4 μm. [FIG. 1 (a)].

[0014] Then, then delve into the resist pattern 4 RIE as a mask (Reactive Ion Etchi-ng) method by opening 4a silicon nitride film 3, the silicon substrate 1 to a depth d ₁ after removing the silicon oxide film 2 Thus, a first groove 5 is formed. In this case, d ₁ is the width W ₁ of the opening 4a
D which is shallower than 1/2 of the total depth of the groove.
₁ + t ₁ is made deeper than _１ ／ of W ₁ . To be precise, the total depth of the first groove 5 includes the thickness of the silicon oxide film 2, but can be ignored here because it is very thin. That is, it is as shown in equation (1).

W ₁ / 2−t ₁ <d ₁ <W _1/2 (1) where d ₁ =
0.15 μm [FIG. 1 (b)]. Next, a silicon oxide film 6 having a thickness t ₂ is buried in the first trench 5 and deposited on the silicon nitride film 3. At this time, t ₂ is the width W of the first groove 5
Make it thicker than 1/2 of ₁ . That is, it is as shown in equation (2).

T ₂ > W _1/2 (2) where t ₂ = 0.25 μm Under this condition, the silicon oxide films 6 sequentially deposited from both sides of the first groove 5 are Clash in the center. This collision surface, that is, the collision surface 7 is formed.
[FIG. 1C] Next, if the silicon oxide film 6 is etched by the RIE method until the silicon nitride film 3 is exposed, the silicon oxide film 6 remains embedded only in the first trench 5 [FIG. FIG.
(D)].

Next, the silicon oxide film 6 is slightly etched using a hydrofluoric acid solution. At this time, the first groove 5
Since the film quality of the collision surface 7 formed by the collision of the silicon oxide film 6 at the center of the first groove 5 is very weak, the etching proceeds rapidly at that portion, and a slit S is formed at the center of the first groove 5 [FIG. 1 (e)]. Further, the silicon oxide film 6 is anisotropically etched by RIE to expose the surface of the silicon substrate 1 at the bottom of the slit S [FIG.
(A)].

Subsequently, using the silicon nitride film 3 and the silicon oxide film 6 as a mask, the silicon substrate 1 is dug down to d ₂ at the position of the slit S, and the second groove 9 is formed into the first groove 8.
It is formed immediately below (FIG. 2B). Next, after removing the silicon nitride film 3 using a heated phosphoric acid solution and removing the silicon oxide films 6 and 2 using a hydrofluoric acid solution, the first groove 5 and the second groove 5 are formed in the silicon substrate 1. A T-shaped groove is formed by the two grooves 9 (FIG. 2C).

Next, a silicon oxide film 10 for burying the first groove 5 and the second groove 9 is deposited. At this time, the thickness t ₃ of the silicon oxide film 10 needs to completely fill the first groove 5 so that the surface of the silicon oxide film 10 is higher than the original surface of the silicon substrate 1. Therefore,
The silicon oxide film 10 is deposited so as to satisfy the relationship shown in the equation (3).

T ₃ > d ₁ (3) Under the above conditions, the deposited silicon oxide film 10 is formed from the side of the groove.
The collision surface 11 where the collision occurs is substantially limited to the inside of the second groove 9, and does not reach the original surface height of the silicon substrate 1. In this embodiment, t ₃ = 0.3 μm. Furthermore, boron phosphorus glass (BPSG) or SPIN ON GL
A highly fluid thin film 12 such as ASS (SOG) is deposited to flatten the surface [FIG. 2 (d)].

Finally, the flowable thin film 12 is formed using the RIE method.
Then, the silicon oxide film 10 is etched at a constant speed until the silicon substrate 1 is exposed, thereby completing the element isolation region forming step according to the present invention [FIG. 2 (e)]. Thereafter, by forming a semiconductor element such as a transistor according to a normal process, a semiconductor integrated circuit is formed.

As a result, an element isolation region having a width W ₁ defined in the photolithography process performed at the beginning of the process is formed. Further, since the upper portion of the colliding surface 11 of the buried oxide film 10 is not exposed to the surface, there is no problem that a slit is formed at the center of the groove even after the treatment such as hydrofluoric acid .

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

As described above, according to the present invention, a T-shaped groove is formed in a substrate, and an oxide film is buried in the groove to prevent generation of a slit in the groove. Therefore, it is possible to avoid a circuit failure due to a short circuit between adjacent gate electrodes. In addition, fine separation according to the mask size specified in a single photolithography process can be realized, the manufacturing process is simplified, and the reliability of the integrated circuit is improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a first embodiment of the invention;

FIG. 2 is a schematic sectional view illustrating a first embodiment of the invention;

FIG. 3 is a schematic cross-sectional view illustrating a conventional example.

[Explanation of symbols]

 1 ··· silicon substrate 2, 6, 10 ··· silicon oxide film 3 ··· silicon nitride film 5 ··· first groove 9 ··· second groove 7, 11 ··· ..Collision surfaces

Claims (1)

(57) [Claims] A first thin film formed on a silicon semiconductor substrate;
After forming, a resist pattern is formed on the first thin film
Using the resist pattern as a mask.
Removing the first thin film on the substrate to be
Of the predetermined depth by etching the substrate
After forming the first groove, the resist pattern is removed,
Then, the first thin film is filled so as to fill the first groove.
After the second thin film is formed thereon, the first thin film is exposed.
And the second thin film inside the first groove remains.
Etch the second thin film so that
The center of the second thin film remaining inside the groove by the solution treatment
After generating a slit in the part, the slit bottom
Etching anisotropically until the part reaches the substrate surface
Then, on the first thin film and the first groove side wall,
Using the remaining second thin film as a mask, just below the slit
By etching the above substrate, a second groove is formed.
After the formation, a residue is left on the first thin film and the first groove side wall.
The remaining second thin film is removed, and then the first and second thin films are removed.
Form a third thin film on the substrate so as to fill the groove of No. 2.
After the formation, a flowable fourth thin film is formed on the third thin film.
After that, the part of the substrate excluding the above each groove is exposed
Etch the fourth thin film and the third thin film until
A method for forming a semiconductor element isolation region.