JP2869893B2 - Semiconductor panel - Google Patents

Description

The present invention relates to a semiconductor panel having a semiconductor element and a wiring layer, such as a thin film transistor panel used for an active matrix type liquid crystal display device.

[Conventional technology]

For example, an active matrix type liquid crystal display device used for a liquid crystal television or the like generally includes a thin film transistor panel as shown in FIG. In this thin film transistor panel, a transparent pixel electrode 2 made of an ITO film or the like and a thin film transistor 3 serving as a switching element connected to the pixel electrode 2 are formed in a matrix on an insulating substrate 1 made of glass or quartz. Are arranged in a plurality. Further, on the substrate 1, a gate line made of chromium or tantalum (scanning) connecting the gate electrodes of the plurality of thin film transistors 3 along one direction (horizontal direction in the figure) by sewing between the pixel electrodes 2 Line) 4 and a drain line (data line) 5 made of chromium or tantalum, which connects drain electrodes of a plurality of thin film transistors 3 in a direction (vertical direction in the figure) intersecting with the line. I have.

FIG. 4 shows a cross-sectional configuration of the thin film transistor 3 as viewed from the AA direction. In FIG. 1, a gate electrode 6 made of chromium or tantalum and having a thickness of about 100 nm is formed on a substrate 1, and the entire surface thereof is covered with a gate insulating film 7 made of a silicon nitride film. An a-Si semiconductor layer 8 made of a-Si (amorphous silicon) is provided in a predetermined region thereon, and n-type impurities are contained in a-Si on both sides of the a-Si semiconductor layer 8. N ⁺ −a mixed with high concentration
A source electrode 10 and a drain electrode 11 made of chromium or tantalum are formed via a contact layer 9 made of a -Si semiconductor layer. Further, one end of the pixel electrode 2 shown in FIG. 3 is connected to the source electrode 10.

The gate electrode 6 and the gate line 4 extending from the gate electrode 6 (FIG. 3) are simultaneously patterned on the substrate 1, and the source and drain electrodes 10, 11 and the drain line 5 ( (Fig. 3)
Simultaneously, a pattern is formed.

[Problems to be solved by the invention]

In the above-mentioned conventional thin film transistor panel, as a material for the gate line 4 (including the gate electrode 6) formed on the insulating substrate 1 such as glass or quartz, the adhesion to the substrate 1 is high and the surface is hardly oxidized. Chromium (Cr) and tantalum (Ta) were used. However, such a thin film made of chromium or tantalum has a high resistivity. For example, the sheet resistance of a 100-nm-thick chromium film or a tantalum film formed by a sputtering device is as high as 7 to 10Ω. was there.

Therefore, the driving capability of the gate line 4 is low,
Many transistors could not be driven, and it was difficult to increase the number of pixel electrodes 2. Also,
In order to reduce the resistance of the gate line 4, the line width must be widened, which makes it difficult to increase the density. For these reasons, conventionally, high performance of the thin film transistor panel has been prevented.

On the other hand, if copper (Cu) is used as the material of the gate line 4, it is possible to reduce the resistance. However, copper has poor adhesion to the substrate 1 and is easily peeled off. Since there is a problem that electrical connection is difficult to obtain, a gate line has not been formed using copper so far.

Note that the above-described problems have occurred not only in the thin film transistor panel but also in various fields having a metal wiring layer formed on an insulating substrate such as glass or quartz.

The present invention has been made in view of the above-described conventional problems, and its object is to achieve a significant reduction in resistance, and also to improve adhesion to an insulating substrate and oxidation resistance of the surface. An object of the present invention is to provide a semiconductor panel having an excellent wiring layer.

[Means for solving the problem]

The present invention relates to a semiconductor element on a substrate, and a first layer made of one or more kinds of metal materials selected from white copper, titanium, aluminum, and molybdenum connected to the semiconductor element;
And a wiring layer in which a second layer made of copper is laminated.

[Action]

White copper, titanium, aluminum, and molybdenum used as the metal material of the first layer all have excellent adhesiveness to a glass substrate or a quartz substrate, as well as excellent adhesiveness to copper, and have the property of being hardly oxidized. have. Therefore, the wiring layer composed of the first layer made of such a metal material and the second layer made of a metal material containing copper enhances the adhesion to the substrate and the underlying layer, and prevents oxidation of the surface. , Low resistance.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a thin film transistor obtained by applying an embodiment of the present invention to a gate electrode (gate line) of the conventional thin film transistor shown in FIG.

In the figure, an insulating substrate 1 made of glass or quartz is shown.
On the entire film, a first metal layer 12a having a thickness of about 50 °, a second metal layer 12b having a thickness of about 200 °, and a third metal layer 12c having a thickness of about 50 ° are sequentially laminated. 3 which is about 300mm thick
A gate electrode 12 having a layer structure is formed. The thickest second metal layer 12b is made of copper (Cu), and the first and third metal layers 12a and 12c formed thinly over the upper and lower surfaces are made of copper (Cu). 15% by weight nickel (N
It is made of white copper (NiCu) containing i). In addition,
The gate line extending from the gate electrode 12 also has the same three-layer structure as the gate electrode 12.

Other structures are the same as those of the conventional thin film transistor shown in FIG. That is, the entire surface of the substrate 1 including the gate electrode 12 is covered with a gate insulating film 7 made of a silicon nitride film (SiN).
A-Si semiconductor layer 8 made of Si (amorphous silicon)
Is further provided on both sides of the a-Si semiconductor layer 8.
A source electrode 10 and a drain electrode 11 made of chromium or tantalum are formed via a contact layer 9 made of an n ⁺ -a-Si semiconductor layer in which n-type impurities are mixed at a high concentration in Si. One end of the pixel electrode 2 is connected to the source electrode 10.

Next, an example of a manufacturing method for forming the gate electrode 12 having a three-layer structure on the substrate 1 will be described below with reference to FIG.

First, as shown in FIG. 2 (a), the entire surface of the substrate 1 is formed by using a sputtering method in the order of white copper, copper, and white copper.
The first metal layer (white copper) 12 is formed by sequentially depositing the respective layers so as to have a thickness of approximately 50 °, 200 °, and 50 °.
a, second metal layer (copper) 12b, third metal layer (copper) 12c
Is formed.

Subsequently, the above-mentioned three-layer film is collectively patterned by a photolithography method, as shown in FIG. 2 (b), so that the three-layer film composed of the first to third metal layers 12a, 12b and 12c is formed. A gate electrode 12 and a gate line having a structure are formed. The etching used for the patterning is performed by, for example, wet etching with a 5% nitric acid aqueous solution or dry etching with ion milling.

According to this embodiment, the gate electrode 12 and the gate line extending therefrom have a three-layer structure, and copper, which is a low-resistance wiring material, is used as the material of the thickest second metal layer 12b. Low resistance is possible. For example, even when the first, second, and third metal layers 12a, 12b, and 12c have a thickness of 50 °, 200 °, and 50 °, respectively, and have an ultrathin three-layer structure with a total thickness of 300 °, The sheet resistance is
Although it is extremely low at 1.5 Ω, and thus is considerably thinner than the conventional gate electrode (gate line) having a thickness of 100 nm, a remarkable lower resistance is realized as compared with the conventional sheet resistance of 7 to 10 Ω.

In addition, the substrate side and the surface side of the second metal layer 12b made of copper are the first and second metal layers 12a and 12a made of white copper, respectively.
It is covered with 2c, and has a property that the white copper has high adhesiveness with copper and a glass substrate or a quartz substrate, and is hardly oxidized. From this, the second metal layer
The substrate 12b and the substrate 1 are securely adhered to each other by the first metal layer 12a, and the oxidation of the surface of the second metal layer 12b is reliably prevented by the third metal layer 12c. The first metal layer 1
If the thickness of 2a is about 50 °, sufficient adhesion can be obtained, and if the thickness of the third metal layer 12c is also about 50 °,
Sufficient oxidation resistance can be obtained.

Therefore, the substrate 1 of the gate electrode 12 (and the gate line)
The resistance of the gate electrode 12 (and gate line) can be significantly reduced while maintaining high adhesion to the substrate and high oxidation resistance of the surface. As described above, in particular, by enabling the gate line to have a remarkably low resistance, the driving capability of the gate line in the thin film transistor panel is improved, and a large number of thin film transistors can be driven, and thus the number of pixel electrodes can be increased. it can.
Further, even if the width of the gate line is reduced, the resistance can be reduced as compared with the conventional gate line made of chromium or tantalum, so that the density of the thin film transistor can be increased. From these facts, it is possible to improve the performance of the thin film transistor panel to which this embodiment is applied.

Further, even if the gate electrode 12 and the gate line have an extremely thin structure of about 300 mm, since the resistance can be reduced as described above, the drain electrode 11 that traverses over the gate electrode 12 and the gate line via an insulating film. And drain line (third
(See the figure) can be reduced. Therefore, problems such as a short circuit between the gate line and the drain line, a disconnection of the drain line, and the like, which have conventionally occurred at the step, can be reduced, and the yield can be improved.

In the above embodiment, the present invention is applied to the gate line. However, the drain line may be formed on the substrate depending on the type of the thin film transistor. In such a case, the present invention is applied to the drain line. can do. In addition, the present invention can be applied not only to the gate lines and drain lines of the thin film transistor panel as described above, but also to various wiring layers formed on an insulating substrate such as glass or quartz, for example, a memory. The present invention can be applied to a wiring layer used in a memory device having a structure in which thin film transistors having functions are arranged in a matrix on an insulating substrate.

The first and third metal layers sandwiching the second metal layer made of copper from both sides include chromium, nickel, tantalum, titanium, aluminum, molybdenum, and tungsten in addition to the above-described copper. It can be used, and the materials of the first metal layer and the second metal layer need not be the same.

〔The invention's effect〕

According to the semiconductor panel of the present invention, a semiconductor element, a first layer made of at least one metal material selected from the group consisting of copper, titanium, aluminum and molybdenum, and a second layer made of copper are stacked on a substrate. With such a wiring layer, it has the effects of increasing the adhesion to the substrate and the underlying layer, preventing oxidation of the surface, and reducing the resistance of the wiring layer.

[Brief description of the drawings]

FIG. 1 is a sectional view of a thin film transistor obtained by applying one embodiment of the present invention to a gate line (gate electrode) of a thin film transistor panel. FIGS. 2 (a) and (b) are gate lines (gate) of the same embodiment. FIG. 3 is a plan view of a general thin film transistor panel used in an active matrix type liquid crystal display device, and FIG. 4 is a plan view of a thin film transistor in a conventional thin film transistor panel. It is sectional drawing. DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 3 ... Thin film transistor, 4 ... Gate line, 5 ... Drain line, 7 ... Gate insulating film, 8 ... a-Si semiconductor layer, 9 ... Contact layer, 10 ... Source Electrode, 11 ... Drain electrode, 12 ... Gate electrode, 12a ... First metal layer, 12b ... Second metal layer, 12c ... Third metal layer.

Continuation of the front page (56) References JP-A-57-161882 (JP, A) JP-A-61-2134 (JP, A) JP-A-2-83533 (JP, A) JP-A-2-151835 (JP) JP-A-2-281237 (JP, A) JP-A-3-72318 (JP, A) JP-A 62-188734 (JP, U) JP-A 63-162326 (JP, U) (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/1343 G02F 1/1345 H01L 29/78 617

Claims (1)

(57) [Claims] A semiconductor device and a first layer connected to the semiconductor device, the first layer being made of at least one metal material selected from the group consisting of copper, titanium, aluminum, and molybdenum;
And a wiring layer formed by laminating a second layer made of copper.