JP2870487B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a Rambus type DRA having a plurality of banks.
About M.

[0002]

2. Description of the Related Art A Rambus-type DRAM (referred to as "RDRAM") for improving a data transfer speed between a controller such as a microprocessor and an image processor and a DRAM (Dynamic Random Access Memory).
Has been proposed.

In a general-purpose DRAM, an address is input from an address terminal, and data is input and output through a data terminal. Therefore, if the memory capacity and configuration change, the required number of address terminals and data terminals changes, and the package and terminal configuration change.

On the other hand, RDRAMs use bus data (B
usData) A protocol-type access method of inputting or outputting an address and data using terminals 0 to 8 is used. For access to the memory, an operation function (such as read / write) and an access address are input by a request packet. Read data and write data are performed using data packets. This example is shown in FIG.

[0005] A packet called a request packet having operation functions and access start address information is sent from the controller to the RDRAM. The RDRAM inputs this request packet in synchronization with the external clock RxClk.

According to the operation and address specified by the request packet, for example, in the case of a read operation, read data is output by a data packet using bus data (BusData) 0 to 8.

FIG. 7 shows an outline of the request packet. Here, only an area indicating an address is shown, and information such as designation of an operation function exists in a blank portion.

Adr [9: 2] (second to second address signals)
9 bits), Adr [17:10], Adr [26: 1
8] and Adr [35:27] indicate the access start address.

As described above, in the RDRAM, since an access is performed using a request packet and a data packet instead of directly inputting an address from an address terminal, a package and a terminal arrangement are common regardless of a memory capacity and a configuration. Can be.

[0010] For example, RDRAM currently being commercialized
The package and terminal arrangement are exactly the same for the 16 Mbit product and the 8 Mbit product.

[0011] In the RDRAM, a sense amplifier of a general-purpose DRAM is used as a sense amplifier cache.
ROW previously accessed by the controller
If it is a (row) address, data is exchanged with the sense amplifier without accessing the memory cell.

In order to increase the hit rate of the sense amplifier cache, it has been considered to divide the memory cell array into a plurality of banks. For example, a 16 Mbit RDRAM has a 2-bank (8 Mbit per bank) configuration. Note that 8M has a one-bank configuration.

The number of banks of the RDRAM is stored in an area called Bankbits in a part of a device type (DeviceType) register, and is determined by reading the contents of the device type register from the controller. .

FIG. 8 shows an RDRAM device type (D
3 shows the configuration of an (deviceType) register. The device type register has a 9-bit width (0 to 8 bits) and an area for 4 bytes. Here, the bit indicated by “R” indicates a reserve (Reserve), and the current RD
This indicates that the RAM is not used.

This device type (DeviceType
e) The register contains the number of bits of the row address of the RDRAM (RowBits), the number of bits of the column address (ColumnBits), whether the data width is 8 bits or 9 bits (Bonus), and the version of the RDRAM (Ver
area), an RDRAM type (Type), and a bit (BankBits) indicating the number of banks.

The controller reads these contents and outputs R
Determine the attributes of the DRAM.

The value of BankBits is as follows: "0" is 1 bank, "1" is 2 banks, "2" is 4 banks, and 16Mbit RDRAM has a 2-bank configuration, so that BankBits is "1", 8Mbit RDRAM
Is a one-bank configuration, and BankBits is “0”. Since the 32 Mbit RDRAM has a two-bank configuration, BankBits is “1”, and the 64 Mbit RDRAM is “1”.
Is a 4-bank configuration, and BankBits is “2”.

In the 16 MR DRAM and the 8 MR DRAM, the same value is set for bits other than Bankbits.

FIG. 9 shows a conventional 16 Mbit RDRAM.
FIG. 10 is a block diagram showing the configuration of an 8-Mbit product.

A conventional 16 Mbit RDRAM is Ram
bus control unit 1, 8M bit upper bank (Upp
erBank; upper bank) Cell array 2, 8 Mbit lower bank (Lower Bank; lower bank)
Cell array 3, device type register (DiceT
type register 14).

The 16-Mbit product has two banks with one 8-Mbit memory cell array as one bank. The configuration of the device type register 14 is configured as shown in FIG. 9. When a request to read the device type register is input by a request packet from the controller, a register read enable (Register) is set.
ReadEnable) signal 142 attains a high level, and a bank bit (Bank) which is an AND gate output is output.
Bits) 141 becomes High level and Rambu
"1" is read from the s control unit 1, indicating that the product is a two-bank product.

At the time of accessing the memory section, when accessing the upper bank (Upper Bank) cell array 2, a bank select (BankSelect) signal 10
1 becomes High level and the upper bank (Uppe
(rBank) cell array 2 is selected. In the case of accessing the lower bank (Lower Bank) cell array 3, a bank select (BankSelect) signal 1
01 becomes the Low level, and the lower bank (Lowe
(rBank) cell array 3 is selected.

Next, referring to FIG.
The RAM will be described. 8Mbit RDRAM is Ra
mbus control unit 21, 8M bit cell array 20, (D
deviceTypeRegister) 24.

When a read request from the controller to the device type register (DeviceTypeRegister) 24 is input, the register read enable (RegisterReadEnable) signal 212 is set to the high level, and the bank bit (Ban) is set.
kBits 211) is at the Low level, and “0” is read out, indicating that it is a one-bank product.

The bank selection signal is always supplied to the cell array 2
0 has been selected and the data bus 20
01 to input / output data.

[0026]

As described above, 16M
The bit product and the 8M-bit product are the same except for the capacity and the bank configuration except for the package and the like. Therefore, when a defective bit exists in only one bank out of two banks in a 16M bit product, the product can be used as an 8M bit product by accessing only the other bank.

However, in the conventional RDRAM, whether it is a 16-Mbit product or an 8-Mbit product is a device type register (D
The device type is set to 1 bank product or 2 bank product (ROM state), and it is impossible to use 16M of a good bank as 8M as it is.

Because, when the controller reads the device type register of the bank good product of the 16 Mbit product,
Recognized as 16M bit product, 16
It may be accessed as an M-bit product.

In the 16-Mbit product, the bank to be accessed is determined by the bank address from the controller. For this reason, 8 banks of 16 Mbit products are
When an attempt is made to use an M-bit product, a normal operation cannot be performed unless a non-defective bank is specified from the controller. However, it is difficult to detect and specify a defective bank of the RDRAM by the controller.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to access only other banks when defective products exist only in some banks, For example, it is an object of the present invention to provide a semiconductor device that can remedy a single bank failure of a 16 Mbit product as an 8 Mbit product.

[0031]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of banks of Ra.
In the mbus type DRAM, at the time of chip test,
Non-defective / defective products are determined for each bank, and when it is determined that a certain bank is defective, means for indicating that the bank is defective is provided by the device type register indicating chip attributes. And a means for setting a bank selection signal so as to access only good banks.

[0032]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of the first embodiment of the present invention, and shows a configuration in a case where the present invention is applied to a 16-Mbit RDRAM of a two-bank configuration in a block diagram.

Referring to FIG. 1, a 16 MR DRAM according to a first embodiment of the present invention includes a Rambus control unit 1 and an 8 Mbit upper bank (Upper Ban).
k) Cell array 2, 8 Mbit lower bank (Lo)
(Lower Bank) cell array 3, device type register (DeviceTypeResister) 4, bank selection circuit 5, lower bank (Lower Bank) detection circuit 6, and upper bank (Upper Bank)
And a detection circuit 7.

The lower bank detection circuit 6 includes a fuse 61 for cutting when a defective bit exists in the lower bank cell array 3 and an output 6 when the fuse 61 is cut.
01 to a low level.

Similarly, the upper bank detection circuit 7 includes a fuse (fuse) 71 for cutting when a defective bit exists in the upper bank cell array 2, and a fuse 71.
And an n-channel transistor 72 for fixing the output 701 to a low level at the time of cutting.

In the n-channel transistors 62 and 72, the channel length L is usually increased in order to suppress the current when the fuses 61 and 71 are not cut.

The bank selection circuit 5 includes outputs 601 and 701 of the lower bank and upper bank detection circuits 6 and 7.
And the bank select (Ba) from the Rambus control unit 1
nkSelect) 101, a bank selection signal 501,
502 is output.

The device type register 4 determines the level of Ramb according to the levels of the outputs 601 and 701 of the detection circuits 6 and 7.
register read enable (Reg) from the us control unit 1
When “interReadEnable” 102 is at a High level, bank bits (Bankbits) 401
Is output to the Rambus control unit 1.

Next, the operation of the first embodiment of the present invention will be described. FIG. 2 shows a flowchart at the time of the chip test.

If no defective bit exists in both the upper and lower banks during the chip test, none of the fuses 61 and 71 of the detection circuits 6 and 7 are cut. In this case, the detection circuits 601 and 701
It is fixed at the h level.

It is assumed that a request packet for reading the device type register 4 has been input to this chip.

The register read enable 102 from the Rambus control unit 1 becomes High level, the bank bit 401 outputs High level, and the Rambus control unit 1 outputs Rambus.
The control unit 1 outputs a bank bit "1" indicating that the chip has a two-bank configuration to a controller (not shown) (step 203 in FIG. 2).

Next, it is assumed that there is a memory access from the controller to the upper bank cell array 2. In this case, the bank select 101 becomes High level indicating upper bank access.

The bank selection circuit 5 has a bank select 10
1 is at a high level and the outputs 601 and 701 of the detection circuits 6 and 7 are at a high level,
The upper bank cell array 2 is accessed by setting the upper bank selection signal 501 to High level, and outputs data to the Rambus control unit 1 through the data bus 201.

Similarly, in the case of access to the lower bank cell array 3, the bank select 101 goes to the low level indicating the lower bank access, and the bank select circuit 5 turns the bank select 101 to the low level, Outputs 601 and 701 of 6, 7 are Hig
The low level causes the lower bank selection signal 5
02 is set to High level, the lower bank cell array 3 is accessed, and Rambu is
The data is output to the control unit 1.

Here, it is assumed that a defect exists in the lower bank cell array 2 during the chip test (see step 202 in FIG. 2).

In this case, only the fuse 61 of the lower bank detection circuit 6 is cut (see step 205 in FIG. 2). Thereby, the output 6 of the lower bank detection circuit 6 is output.
01 is fixed at the low level. The output 701 of the upper bank detection circuit 7 is at a high level.

In the bank selection circuit 5, since the output 601 of the lower bank detection circuit 6 is at a low level, the upper bank selection signal 501 output from the bank selection circuit 5 is at a high level, and the lower bank selection signal 502 is at a low level. Fixed to level.

Also, no matter what level the bank select 101 from the Rambus control unit 1 has, the output of the bank select circuit 5 is not affected.

Thus, the upper bank cell array 2 is always selected for this chip.

Next, it is assumed that a request packet for reading the device type register 4 is input to this chip.

Although the register read enable 102 is at a high level from the Rambus control unit 1, the output 601 of the lower bank detection circuit 6 is at a low level, so that the bank select 401 outputs a low level.
“0” indicating that the chip has a one-bank configuration is output from the Rambus control unit 1 to the controller (step 207).

On the other hand, if there is a defect in the upper bank cell array 2, the fuse 701 of the upper bank detection circuit 7 is cut (step 206 in FIG. 2). As a result, the output 701 of the upper bank detection circuit 7 becomes Lo
Fixed to w level. The output 601 of the lower bank detection circuit 6 is at a high level.

Since the output 701 of the upper bank detection circuit 7 is at the low level, the upper bank selection signal 501 output from the bank selection circuit 5 is low.
ow level, the lower bank selection signal 502 is set to High.
Fixed to h level.

As a result, the lower bank cell array 3 is always selected for this chip. When a request packet for reading the device type register 4 is input, the bank bit 401 is similarly set to Low.
The level becomes “0”, and “0” indicating that the chip has a one-bank configuration is output from the Rambus control unit 1 to the controller.

The above is summarized as shown in FIG.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram of the second embodiment of the present invention. In a 64-Mbit DRAM having a 4-bank configuration with 16 Mbits as one bank, any bank has a defect. If you do
An example is shown in which saving is performed as a 32-Mbit product having a bank configuration.

Incidentally, in the second embodiment of the present invention, 2
An example is shown in which one bank is a set and one of the two banks is defective when one of the banks has a defect.

64 MR DRAM according to this embodiment
Is a Rambus control unit 41, 16M bit bank 0
It comprises a cell array 21, a bank 1 cell array 22, a bank 2 cell array 23, a bank 3 cell array 24, a device type register 44, a bank selection circuit 45, a bank 23 detection circuit 46, and a bank 01 detection circuit 47.

The bank 23 detection circuit 46 includes a fuse 61 for cutting when a defective bit exists in the bank 2 cell array 23 or the bank 3 cell array 24, and an n-channel transistor for fixing the output 4601 to a low level when the fuse 61 is cut. 62.

Similarly, the bank 01 detection circuit 47 includes a fuse 71 for cutting when a defective bit exists in the bank 0 cell array 21 or the bank 2 cell array 22;
An n-channel transistor 72 for fixing the output 701 to a low level when the fuse 71 is cut.

The transistors 62 and 72 are connected to the fuse 6
In order to suppress the current when 1, 71 is not cut,
Usually, the channel length L is increased.

The bank selection circuit 45 includes the banks 23, 01
The outputs 4601 and 4701 of the detection circuits 46 and 47 and Ra
Bank select 4101 and 4 from mbus control unit 41
102, the bank selection signals 4501, 4502, 450
3, 4504 are output.

The device type register 45 is stored in the bank 2
3,01 Outputs 4601 and 4701 of detection circuits 46 and 47
When the register read enable 4112 from the Rambus control unit 41 is at the High level,
The bank bits 401 and 402 are stored in the Rambus control unit 41.
Output to

In the 64 MR DRAM, the number of banks is 4, and the bank bit (Ban) of the device type register 4 is
kBits) indicates 2. In this embodiment, the lower bits of the bank bits (BankBits) are represented by bank bits 4401, and the upper bits are represented by bank bits 4402.

The signals 4401 and 4402 and the bank bit (BankBit) output from the Rambus control unit 41
The following table shows the relationship with s).

[0067]

[Table 1]

Next, the operation of the second embodiment of the present invention will be described.

If no defective bit exists in both banks during the chip test, the fuses 6 of the detection circuits 46 and 47
Neither of 1 nor 71 cuts the fuse. In this case, the detection circuit outputs 4601 and 4701 are Hi.
gh level.

It is assumed that a request packet for reading the device type register 44 has been input to this chip. When the register read enable 4112 becomes high level from the Rambus control unit 41, the bank bit 4
A low level 401 is output and the bank bit 440 is output.
2 outputs a High level, and as a result, “2” is output from the Rambus control unit 41 as a bank bit, and the controller is notified that the chip has a 4-bank configuration.

Next, it is assumed that there is a memory access from the controller to the bank 0 cell array 21. in this case,
The low level of each of the bank selects 4101 and 4102 is output from the Rambus control unit 41.

The bank selection circuit 45 includes a bank select 4
The bank 0 selection signal 4501 is set to Hi due to the low levels of 101 and 4102 and the outputs 4601 and 4701 of the detection circuits 46 and 47 being High level.
gh level, the bank 0 cell array 21 is accessed, and the Rambus control unit 4
Output data to 1.

Here, when it is determined that a defect exists in the bank 0 cell array 21 during the chip test, only the fuse 71 of the bank 01 detection circuit 47 is cut.

As a result, the output 4701 of the detection circuit 47
Is fixed at a low level. Further, the output 4601 of the bank 23 detection circuit 46 remains at High level.

Since the output 4701 of the detection circuit 47 is at the low level, the bank selection circuit 45 outputs the signal 4 of the selection circuit 45.
Reference numeral 505 indicates a low level, and reference numeral 4506 indicates a high level. As a result, the bank 0 selection signal 4501 and the bank 1
The selection signal 4502 is fixed at a low level. The bank 2 selection signal 4502 and the bank 3 selection signal 4503 are Ra
Bank select signal 4101 from mbus control unit 41
, Bank 2 or bank 3 is selected, and bank 0 having a defect is not accessed.

Next, it is assumed that a request packet for reading the device type register 44 is input to this chip.

When the register read enable 4112 outputs a high level from the Rambus control unit 41, the output 4701 of the detection circuit 47 is a low level, so that the bank bit 4401 outputs a high level and the bank bit 4402 outputs a low level. Rambus
“1” indicating that the chip has a two-bank configuration is output from the control unit 41 to the controller.

The same operation is performed for the other banks. These operations are summarized as shown in FIG.

[0079]

As described above, according to the present invention, for example, a single bank good product of 16 Mbit product can be rescued as an 8 Mbit product, and a chip to be a defective product is an 8 Mbit product. As a product
This leads to a cost reduction of the entire 6M bit product.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation at the time of a chip test according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a list of operations according to the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a list of operations according to the second exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an outline of access to an RDRAM;

FIG. 7 is a diagram showing an outline of a request packet.

FIG. 8 is a diagram showing a configuration of a device type (DeviceType) register.

FIG. 9 is a block diagram showing a configuration of a conventional 16 Mbit RDRAM.

FIG. 10 is a block diagram showing a configuration of an 8-Mbit RDRAM;

[Explanation of symbols]

1, 21, 41 Rambus control unit 2 Upper bank (cell array) 3 Lower bank (cell array) 4, 14, 24, 44 Device type register (De)
ViceTypeRegister 5, 45 Bank selection circuit 6 Lower Bank detection circuit 7 Upper Bank detection circuit 20 8M bit cell array 21 Bank 0 (Bank 0) cell array 22 Bank 1 (Bank 1) cell array Bank 23 23 ) Cell array 24 Bank 3 (Bank 3) cell array 46 Bank 23 (Bank 23) detecting circuit 47 Bank 01 (Bank 01) detecting circuit 61, 71 Fuse 62, 72 N-channel transistor 101, 4101, 4102 Bank select (Ban)
kSelect signal 102, 142, 212, 4112 Register read enable (RegisterReadEnable) signal 201 Upper bank (Lower Bank) data bus 301 Lower bank (Lower Bank) data bus 601 Upper bank (Upper Bank) selection circuit 6 Output line 701 Lower bank (Low) Selection circuit 7 output line 2001 8 Mbit cell array data bus 2101 Bank 0 (Bank 0) cell array data bus 2102 Bank 1 (Bank 1) cell array data bus 2103 Bank 2 (Bank 2) cell array data bus 2104 Bank 3 (Bank 3) cell array data bus 4505 Bank 01 (Bank01) selection signal 4506 Bank23 (Bank2) ) Selection signal 141,212,401,4401,4402 bank bit (BankBits) signal

Claims (1)

(57) [Claims] 1. A Rambus type DR having a plurality of banks.
In the AM, at the time of a chip test, a non-defective product and a defective product are determined for each bank, and when it is determined that a certain bank is a defective product, means for indicating that the bank is defective is provided by: And a means for setting a bank selection signal so as to access only good-quality banks.