JP2871296B2 - Synchronous signal regeneration repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous signal regenerating repeater for relaying and transmitting a synchronous signal using a communication path handled by an exchange.

[0002]

2. Description of the Related Art With respect to a method of relaying and transmitting a synchronization signal using a communication path handled by an exchange, a method of transmitting a synchronization signal between stations (Reference 1) and a method of distributing the synchronization signal in the exchange (Reference 2). ). Reference 1: Masami Yabuzaki, Seizou Onoe, Takemi Arita, Junki Shinagawa,
"Continuous Channel Switching Control in Digital Mobile Communication", Transactions of the Society of Electronics, Information and Communication Engineers B-II, J73-B-
II, 11, PP. 585-594 (1990) Reference 2: Hironao Tanaka, “Synchronous signal distribution method”, Japanese Patent Application No. 3-
No. 246557

In this prior art,
Documents 1 and 2 describe a method of transmitting a synchronization signal between stations, but there is no description of a redundant configuration control method when a redundant configuration is given to a synchronization signal between stations.
Document 2 describes a redundant configuration relating to the synchronization signal distribution in the station and a control method thereof. However, since the redundant configuration control method leaves the decision to the switching software, the load of the switching software becomes heavy. was there.

[0003]

According to the present invention, there is provided a synchronous signal regenerating repeater for relaying and transmitting a synchronous signal through a communication path handled by an exchange. Monitoring means for monitoring a cycle every time; input selection means for selecting one of the plurality of input synchronization signals according to a predetermined priority based on a result of the monitoring means; and counting a clock given from the exchange. Counter means for outputting, as a counter value, a predetermined cycle and a phase corresponding to a given initial setting signal with respect to the output synchronization signal of the own apparatus, and inputting the output value of the counter means as an address of a nonvolatile memory In addition, the data stored in the non-volatile memory is read out, and from the read out data, a predetermined timing is applied to the synchronization signal of the own device and the output synchronization signal. Timing means for outputting a signal having a relationship, and comparing the phase of the synchronizing signal output from the input selection means with the timing signal of the non-volatile memory output, when a predetermined relation is established, an initial setting signal is sent to the counter means. And an initial setting control means for prohibiting the output of the initial setting signal to the counter means when all cycles of the input synchronizing signal are determined to be abnormal.

[0004]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a synchronous signal regeneration relay device of the present invention.

In FIG. 1, a period monitoring circuit 1, 2, 3
Monitors the cycle of the input synchronization signals a, b, to c and sends the monitoring result to the input signal selection control circuit 4. The input signal selection control circuit 4 selects one normal input synchronization signal in accordance with a predetermined priority, and instructs the selector circuit 5 of the selection result.
The selector circuit 5 selects one of the input synchronization signals a and c according to the instruction of the input signal selection control circuit 4. The address counter circuit 9 counts the clock signal d from the exchange as a reference to determine the period of the reproduction output synchronizing signal f, and the output counter value sets the read address of the data ROM circuit 10. The data ROM circuit 10 outputs the data at the address set by the address counter circuit 9 as a reproduction output synchronization signal f, and sends a timing signal g written at the same address to the timing control circuit 6. The timing control circuit 6 compares the phase of the synchronization signal h output from the selector circuit 5 with the timing signal g output from the data ROM circuit 10, and determines that the synchronization signal h output from the selector circuit 5 is within the timing range defined by the data ROM circuit 10. When the number deviates from the set number, the gate of the AND circuit 8 is opened, the address counter circuit 9 is initialized by the initial setting signal i, and the phase of the reproduction output synchronizing signal f is corrected.

Next, the operation of this embodiment will be described.
When the period monitoring circuits 1 to 3 detect a period abnormality for each of the input synchronization signals a and c, the period monitoring circuits 1 to 3 report the abnormality to the input signal selection control circuit 4. The input signal selection control circuit 4 selects a normal input signal from the monitoring results of the cycle monitoring circuits 1 to 3 based on the determined priority, and instructs the selector circuit 5 on it. The selector circuit 5 selects and outputs an input signal based on the instruction result. Here, for convenience of explanation, the synchronization signal is a signal that periodically becomes “1”, and otherwise becomes “0”.

The reproduction operation is performed by the address counter circuit 9 and the data ROM circuit 10. Address counter circuit 9
Determines the period of the reproduction output synchronizing signal f, and the output value of the address counter circuit 9 is used as it is in the data ROM circuit 1
0 is set as the address. Data ROM circuit 10
For example, data of "1" is written in a specific bit only at the address of the timing at which the synchronization signal is output, and "0" is written in the specific bit otherwise. This specific bit is output as the reproduction output synchronization signal f. In addition, "1" is written in another bit in the data ROM circuit 10 in data in an address range having a certain width before and after the output timing at which the reproduction output synchronization signal becomes "1", and "0" is written in other cases. The result of reading the bit data is output as a timing signal g.

The timing control circuit 6 compares the synchronization signal h output from the selector circuit 5 with the timing signal g output from the data ROM circuit 10, and outputs the output synchronization signal of the selector circuit 5 while the timing signal g is "1". Signal h is "1"
Count the number of times that does not occur. When the count value exceeds the set number of times, a synchronization signal h output from the selector circuit 5 is output as an initial setting signal i via an AND circuit 8 to correct the phase of the reproduction output synchronization signal f, and an address counter is output. The circuit 9 is initialized.

When all the input synchronizing signals a, b to c become abnormal, the input signal selection control circuit 4 sends out all the input signal abnormal signals e to the AND circuit 8 via the inverter circuit 7, and the address counter The initialization signal i is not output to the circuit 9. Thereafter, the address counter circuit 9 runs by itself,
The phase of the reproduction output synchronizing signal f is held in a state before the abnormality.
When the abnormality of one of the input synchronizing signals is recovered, the recovered synchronizing signal h of the output of the selector circuit 5 is output again as the initial setting signal i via the AND circuit 8, and the address counter circuit 9 is initialized and reproduced. The phase of the output synchronization signal f is reset.

[0010]

As described above, the synchronous signal reproducing repeater of the present invention selects one of a plurality of input synchronous signals by hardware logic, and reproduces the synchronous signal based on the selected synchronous signal phase. Since the output is performed, there is an effect that control by the exchange software is almost unnecessary.

Further, since the pattern of the reproduced output synchronizing signal written in the nonvolatile memory and the pattern of the timing signal related to the phase of the reproduced output synchronizing signal are data, the data is changed to change the output synchronizing signal. And the method of controlling the output phase and the output phase can be set freely.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a synchronization signal regeneration relay device of the present invention.

[Explanation of symbols]

 1 to 3 Period monitoring circuit 4 Input signal selection control circuit 5 Selector circuit 6 Timing control circuit 7 Inverter circuit 8 AND circuit 9 Address counter circuit 10 Data ROM circuit a, to c Input synchronization signal d Clock signal e All input signal abnormal signal f Reproduction output synchronization signal g Timing signal h Synchronization signal of selector circuit 5 output i Initial setting signal

Claims (1)

(57) [Claims] 1. A synchronizing signal regenerative repeater for relaying and transmitting a synchronizing signal through a communication path handled by an exchange, a monitoring means for monitoring a period of each of the plurality of input synchronizing signals for each input synchronizing signal; Input selecting means for selecting one of the synchronization signals in accordance with a predetermined priority order based on the result of the monitoring means, and counting a clock supplied from the exchange to a predetermined period for an output synchronization signal of the own apparatus Counter means for outputting, as a counter value, a phase corresponding to the given initial setting signal, inputting the output value of the counter means as an address of a nonvolatile memory, and reading data stored in the nonvolatile memory. Timing means for outputting, from the read data, a signal having a predetermined timing relationship with respect to the synchronization signal of the own device and the output synchronization signal; The phase of the synchronization signal output from the input selection means is compared with the timing signal output from the nonvolatile memory, and when a predetermined relationship is established, an initial setting signal is output to the counter means, and the period of the input synchronization signal is all abnormal. And an initial setting control means for prohibiting the output of the initial setting signal to the counter means.