JP2871866B2 - RS-CS delay compensation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RS-CS signal delay compensator for data transmission by the ATM system.

2. Description of the Related Art In data transmission by an ATM (Asyncronous Transfer Mode) system, as shown in FIG. 2, when data including voice, data and video information is transmitted from a local terminal to a remote terminal, a point B in FIG. As shown in FIG. 3B, HDLC (High Level Data Link Control Procedure)
re) to generate fixed-byte-length data (hereinafter referred to as cells).

While this cell is being transmitted to the opposite station, due to the waiting of cell transmission in the own station, transmission delay between stations, etc., at point C in FIG. The delay will be different. Therefore, in the game, it is necessary to absorb the delay (hereinafter referred to as fluctuation) of these cells.

[0004] Similarly, RS-CS delay compensation requires RS-CS delay compensation because the fluctuation cannot compensate for the delay between the RS-ON cell and the data cell. Note that RS means a transmission request signal, and is a signal for controlling a transmission carrier sent from the data transmission terminal device to the signal conversion device. CS is a transmission enable signal, and the signal conversion device receives the RS, and This is a control signal indicating completion of preparation sent to the data transmission terminal device after a certain period of time.

[0005]

2. Description of the Related Art FIG. 6 shows a conventional RS-CS delay compensation system. In the conventional method, the fluctuation absorbing memory 51 and the RS
-Two memories including the CS delay compensation memory 53 are used. The operation will be described below with reference to FIG. First, when the write control unit 50 receives a cell (parallel data) from a game, the data is written to the fluctuation absorption memory 51. Further, the fluctuation timer 55 is activated at the same time as the data reception, and a fixed byte length data (hereinafter, referred to as a cell) is made to stand by for the fluctuation time, thereby absorbing the fluctuation time of each cell (see the time chart of FIG. 7). Timer1).

After absorbing the fluctuation (rising of the fluctuation timer), the read / write control unit 52
The received data is read out from the fluctuation absorbing memory 51 and R
The writing to the S-CS compensation memory 53 is performed again. At this time, a CD (carrier detection signal) is detected from the parallel data B, an RS-CS timer 56 is started, and the RS-CS
The data is made to wait in the RS-CS delay compensation memory 53 for the delay compensation time (Ti in the time chart of FIG. 7).
mer2).

Next, after the delay compensation (rising of the RS-CS timer), the Read control section 54 performs the RS-CS delay compensation by reading data from the delay compensation memory 53.

[0008]

However, in the above-mentioned conventional system, two memories are required for one channel of the terminal.
And read / write control is performed for each of them. Therefore, when a large number of terminals are to be supported, it is necessary to use twice as many memories as the number of supported channels, and an increase in the number of memories results in an increase in cost and an increase in mounting area. Was. In addition, there has been a problem that the data processing delay time also increases.

The present invention has been made in view of the above circumstances, and solves the above problem by reducing the memory for fluctuation absorption and RS-CS compensation to one memory and performing read / write control. To provide an RS-CS delay compensating device.

[0010]

FIG. 1 shows the principle configuration of the present invention. Referring to FIG. 1, the present invention relates to a delay compensating apparatus for data transmission by the ATM system, comprising: a write control unit 1 for controlling memory writing of received data; and a 1 for absorbing a change in cell waiting time and performing RS-CS delay compensation. A delay time variation absorption / delay compensation memory 2, an RS-CS timer 3 and a delay timer 4, which start upon receiving a signal from the write control unit 1 when data is received, and an RS-CS timer 3 and a delay timer 4. The data read timing is determined and read out from the waiting time fluctuation absorption / delay compensation memory 2 according to the result of the comparison of the timing end timing, and thereby reading is performed by one memory to control the waiting time fluctuation absorption and delay compensation. And a control unit 5.

According to the RS-CS delay compensating apparatus of the present invention, the write control unit 1 detects the head of data and the CD from the received parallel data, so that the delay timer 4, R
The S-CS timer 3 is started, the conditions of these two timers are monitored by the read control unit 5, and the fluctuation is absorbed, and the RS-CS
Delay compensation, waiting time fluctuation absorption / delay compensation memory 2
Is to read data from.

[0012]

According to the present invention, when the write controller 1 recognizes the RS-ON cell from the received data, the signal becomes RS-ON.
-When the CS timer 3 is started and the data cell is recognized,
The fluctuation timer 4 is started. In the read control unit 5, the fluctuation absorption time and R
Recognizing the S-CS delay compensation time, the data can be read from the fluctuation absorbing and RS-CS delay memory 2 under the condition of the data read timing.

That is, when the RS-CS delay compensation time is shorter than the fluctuation absorption time at the data reading timing, the memory output sends out the signal all “High” after the RS-CS delay compensation time, and After the elapse, the data is transmitted. In addition, the fluctuation absorption time is RS-
When the time is shorter than the CS compensation time, after the RS-CS compensation time, the signal all “High” (8 bits) is transmitted, and then the data is transmitted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited by this. FIG. 4 is an RS-CS showing one embodiment of the present invention.
FIG. 3 is a configuration diagram of a delay compensation device. Referring to FIG. 1, the present invention is a delay compensating device for data transmission by the ATM system, and controls a write of received data into a memory.
(Writing) control unit 10, one fluctuation (waiting time fluctuation) absorption / RS-CS delay compensating memory 14 that absorbs the waiting time fluctuation of the cell and compensates for the RS-CS delay, An RS-CS timer 11 and a fluctuation (delay) timer 13 that are activated in response to a signal from the control unit 10, and a fluctuation absorption / RS according to a comparison result of timing end timings of the RS-CS timer 11 and the fluctuation timer 13.
-Determine the data read timing from the CS delay compensation memory 14 and read it out, thereby controlling the fluctuation absorption and RS-CS delay compensation in one memory.
ad (read) control unit 15, CD register 12 and H
And a DLC FLAME conversion unit 16.

FIG. 5 is a time chart of this embodiment. In both figures, the RS-ON is provided to the Write control unit 10.
When a cell is received, the RS-CS timer 11 starts,
The CD register 12 is turned on. When a data cell is received, the fluctuation timer 13 starts, and the data is stored in Wri.
memory 14 for fluctuation absorption / RS-CS delay compensation indicated by the Write address generated by the te control unit 10
(Hereinafter referred to as a memory).

Next, the RS-
A comparison is made between the CS delay compensation time and the fluctuation absorption time,
Data is read from the memory 14 according to the comparison result, and the read data is stored in the HDLC FLA.
The ME converter 16 converts the data into serial data corresponding to the terminal and outputs the serial data. The maximum time of the time measured by the fluctuation timer 13 is limited due to the transmission characteristics of the ATM. If the next cell does not arrive within the time, the data is discarded. The signal output from the fluctuation timer 13 is a trigger signal for instructing the read control unit 15 to read.

Next, a description will be given of processing contents according to the result of comparison between the RS-CS delay compensation time and the fluctuation absorption time. (1) Case of RS-CS delay compensation time <fluctuation absorption time As shown in case 1 of FIG. 5, after the RS-CS delay compensation time, it is unknown whether data is written in the memory 14 or not. , Read permission cannot be given,
Therefore, the memory output data is all “High”. However, in the HDLC FLAME converter 16, this all
“High” becomes a flag (8-bit signal: 01111110) and is output.

After the fluctuation absorption time, 8 bits all “Hi
gh ”, the data is output from memory 14 while H
The 8-bit all “Hi” is output by the DLC FLAME converter 16.
"gh" is converted to a flag and output. That is, RS
-Since a time interval occurs between the timing when the CS time ends and the timing when the fluctuation absorption time ends, a flag is inserted once, and if the interval is long, a flag corresponding to the interval is additionally inserted, and then data is transmitted. To work.

(2) Case of RS-CS delay compensation time> fluctuation absorption time As shown in case 2 of FIG. 5, after the fluctuation absorption time, data is written in the memory 14, but the RS-CS delay is longer. Since no compensation has been made, reading cannot be permitted, and the memory output data is all “High”. And RS-CS
After the delay compensation time, after 8 bits all “High”, the data is output from the memory 14, and the 8 bit all “High” is converted into a flag by the HDLC FLAME converter 16 and output.

That is, as in Case 2, RS-
If the waiting time of the CS time is later than that of the fluctuation absorption time, a flag is inserted once at the same time as the waiting time ends, and the data is continuously transmitted as it is.

The data is supplied to the RS-CS timer 11 and the fluctuation timer 13 in accordance with the read address generated by the read control unit 15, and to absorb the fluctuation / RS-CS
It is read from the compensation memory 14.

The conventional read / write control section 52 shown in FIG. 6 performs an operation of reading data after the fluctuation time of the fluctuation timer 55 and an operation of outputting the CD after reading and activating the RS-CS timer 56. Go separately, that is, after absorbing the fluctuations, RS
Since the operation of compensating for the delay of -CS was performed stepwise, it was necessary to control two memories via the read / write control unit 52.

Therefore, conventionally, fluctuation absorption time and RS
-A waiting time was generated for each of the CS delay compensation time. However, in this embodiment, as described above, since there is only one memory, it is not necessary to wait twice before data transmission.

[0024]

According to the present invention, two memories conventionally used for fluctuation absorption and RS-CS delay compensation can be reduced to one memory, so that the cost is reduced and the mounting area is reduced. Can be reduced. Also,
Since the delay time generated in the data processing can be reduced, it greatly contributes to the improvement of the characteristics of the RS-CS delay compensation system.

[Brief description of the drawings]

FIG. 1 is a principle view showing a basic configuration of the present invention.

FIG. 2 is a schematic diagram showing a configuration of ATM transmission according to the present invention.

FIG. 3 is a time chart of ATM transmission according to FIG. 2;

FIG. 4 is a block diagram showing a configuration according to an embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional example.

FIG. 7 is a time chart showing the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write control part 2 Memory 3 RS-CS timer 4 Delay timer 5 Read control part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (1)

(57) [Claims] 1. A delay compensator for data transmission according to an ATM system, comprising: a write control unit (1) for controlling writing of received data into a memory;
One latency fluctuation absorption / delay compensation memory (2) for S-CS delay compensation, and a write control unit (1) when receiving data
The waiting time fluctuation according to the comparison result between the RS-CS timer (3) and the delay timer (4), which are activated in response to a signal from the timer, and the timing end timing of the RS-CS timer (3) and the delay timer (4). The data read timing from the absorption / delay compensation memory (2) is determined and read out, so that the read control unit (5) for controlling the waiting time fluctuation absorption and the delay compensation in one memory is provided. Characteristic RS-CS delay compensation device.