JP2872117B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a memory for storing instructions, and more particularly to a microprocessor that performs a pipeline operation.

[0002]

2. Description of the Related Art A cache memory will be described as an example of an instruction storage memory.

A microprocessor without a built-in cache memory reads and executes an instruction to be executed from an external main memory as needed in response to a control signal using an address bus and a data bus of external terminals. Therefore, it is possible to determine the instruction being executed by observing the state of the external terminal, particularly the address bus and the control signal, and it is possible to realize an instruction trace by an in-circuit emulator or the like.

Further, in an electrical characteristic test of a device using an LSI tester or the like, Fail, that is, a state of an external terminal is compared with an expected value generated by a simulation or the like as needed.
Even when a mismatch signal occurs, it is easy to determine the instruction being executed, so that the problem location can be quickly identified.

However, in a microprocessor having a built-in cache memory, if an instruction to be executed hits the built-in cache memory, the external main memory is not accessed. It was impossible to specify the instruction, and the instruction trace could not be performed.

Therefore, there is a method of realizing instruction tracing by observing an external terminal so that the cache memory is always disabled and access to the external main memory is always performed when instruction tracing is performed.

Referring to FIG. 16, which shows an example of a conventional system configuration in which the use of a cache is prohibited, an instruction cache memory unit (hereinafter, referred to as an instruction cache unit) 11, a data cache memory unit (hereinafter, cache) 12), a register file section 13, an operation execution section 14, a program counter section 15, a branch address generation section 16, a bus interface section 17, and a control section 18, and a mishit signal 501 output from the instruction cache section 11. And the cache use prohibition signal 565 are input to the OR circuit 177, and the output is input to the control unit 18 and the bus interface unit 17, respectively. The output signal 503 of the program counter unit 15 is supplied to the instruction cache unit 11 and the bus interface unit 17.

The register file RF13 outputs the output 504 to the branch address generator 16 and the selector 1 of the operation execution unit 14.
01, and the other output 505 of the register file 13 is connected to the latch 103.

The other input terminal of the selection circuit 101 is a bus 50
7 connects to the branch address generator 16, the instruction cache 11, the controller 18, and the bus interface 17.

The branch address output of the branch address generator 16 is supplied to the program counter 15, and the fetch address of the program counter 15 is supplied to the branch address generator 16.

[0011] The output of the latch 10 2 and 103 ALU
The output of the ALU 105 is supplied to the latch 106, the data cache unit 12, and the bus interface unit 17, respectively. The output of the latch 104 is supplied to the data cache unit 12, the bus interface unit 17, and one input terminal of the selection circuit 107 via a bus 508, and the output of the latch 106 is supplied to the other input terminal of the selection circuit 107.

The output of the selection circuit 107 is supplied to a latch 108, and the output is supplied to an input terminal of a register file RF13.

The mishit signal 510 and the cache use prohibition signal 565 of the data cache unit 12 are supplied to the bus interface unit 17 and the control unit 18 via the NOR circuit 176, respectively.

The microprocessor 1c having the above-described configuration notifies that the use of the cache memory is prohibited by a cache use prohibition signal 565 generated from an external terminal or a register in the microprocessor. By forcibly activating the mishit signal 501 from the cache memory, a cache mishit always occurs, and the cache is not substantially used.

Referring to FIG. 17 showing a timing chart of a pipeline at the time of a cache miss for explaining the operation, an access to the external main memory for instruction fetch occurs at each of the instructions inst1 to inst5. That is, in the memory read bus cycle, an address signal is output to the external address bus in response to the timing at which the bus cycle start signal goes low, and when the bus cycle start signal changes from the low level to the high level, the external data bus sends the signal to the external data bus. The read read data is input.

On the other hand, while using the cache memory,
A conventional example in which an address is output to the outside when a branch is taken by a branch instruction is described in Japanese Patent Laid-Open No. 4-319974. Referring to FIG. 18 which shows a configuration diagram of a microprocessor having a debug support function described in the publication, the microprocessor includes a bus interface unit 18.
1, cache memory unit 182, instruction prefetch unit 1
83, an instruction decoder / address calculation unit 184, and an operation execution unit 185.

The bus interface section 181 is for transmitting and receiving signals to and from the outside. In particular, the bus interface section 181 and the external address bus 571 and the terminal 186 and the external data bus 57
2 and the terminal 187 exchange data with an external main memory.

The cache memory unit 182 is a cache memory built in the microprocessor, and is of a mixed instruction and data type. Instruction prefetch unit 18
3 and outputs a hit / miss hit display signal 573 to the bus interface unit 181 indicating whether the access has been hit or missed.

When an instruction fetch request is issued, the instruction prefetch unit 183 first supplies a fetch address to the cache memory unit 182 via the address bus 577. If the access is hit, the instruction prefetch unit 183 transmits the instruction from the cache memory unit 182 via the data bus 578. It receives a code and other data, and when a miss occurs, receives an instruction code and other data from an external main memory through the bus interface unit 181.

When an address of a branch destination, which will be described later, is given from the arithmetic execution unit via the branch address bus 576, the cache memory unit 182 is referred to in response to the new address, and at the same time, the bus interface unit 18
A signal 579 indicating that the instruction is an instruction fetch after branching to 1.
Is output.

The instruction decoder / address calculator 184
Instruction prefetch unit 1 through instruction data bus 574
When the instruction code is received from 83, it is converted into an instruction format executable by the operation execution unit 185, and an address for an operand required for execution of the operation is calculated.

The operation execution unit 185 receives the instruction code and the address of the operand from the instruction decoder / address calculation unit 184 via the instruction data bus 575, and determines whether or not the operand is data on the memory based on the received address. It is determined that the data is in the memory, the cache memory unit 182 is referred to via the address bus 577 and the data bus 578, and the data is received from the cache memory unit 182 via the data bus 578 when hit.

On the other hand, when a miss occurs, data is received from the external main memory through the bus interface unit 181. If the received instruction code indicates a branch instruction, the branch condition is checked if necessary, and if a branch is required, the address of the branch destination is set to the branch address bus 57.
6 to the instruction prefetch unit 183.

When receiving a signal 579 from the instruction prefetch unit 183 indicating that the instruction is an instruction fetch after branching, the bus interface unit 181 indicates a branch indication signal 5 indicating that the instruction fetch is performed first after the branch.
80 is output to the outside via the terminal 188.

At this time, a hit / miss hit display signal 573 is received from the cache memory unit 182, and if the hit / miss hit display signal 573 is hit, a hit display signal 581 is output to the outside via the terminal 189, and the cache memory at that time is output. The address provided to the memory unit 182 is received through the address bus 577, and is received by the external address bus 5
71, and output to the outside via the terminal 186.

Therefore, in this microprocessor, whether or not a branch was taken in the course of the instruction sequence and whether or not the first instruction fetch after the branch hit in the cache memory unit are determined by the branch display signal and the hit display signal, respectively. The external address bus 5 can be monitored externally, and not only addresses accessed to the external main memory but also addresses accessed in the cache memory unit are provided.
71.

If the branch is not taken, the instructions are executed sequentially, so that a miss occurs in the cache memory unit 182 and an address when an access to the external main memory occurs through the bus interface unit 181. The instruction sequence can be predicted from the address at the time of execution of the branch instruction.

For example, FIG. 19 shows a timing chart when a branch is taken by a branch instruction.
Assuming that the branch instruction 1 is executed after the st1 and the branch instruction 2 is executed after the instruction inst4, during the period when the bus cycle start signal is at the high level, the branch instruction signal and the branch indication signal are output at the timing when the branch instruction 1 executes the RF The hit display signals go high, and the branch address is output to the external address bus. Similarly, at the timing when the branch instruction 2 executes the RF, the branch display signal and the hit display signal each become high level, and the branch address is output to the external address bus.

[0029]

As described above, a microprocessor having a built-in cache memory and operating by pipeline control is generally assumed to operate using the cache memory. Therefore, while operating by hitting the cache memory,
As shown in a timing chart of FIG. 11, which will be described later, the pipelines are all in a clogged state, and are executed substantially by one instruction and one clock, indicating that the pipeline operation has a high speed.

However, in the conventional example shown in FIG. 16 in which instruction tracing is performed with the use of the built-in cache memory disabled, as shown in the timing chart of FIG. 17, the pipeline extends up to four clock cycle periods. For example, four clocks are required for one instruction, and it is not possible to create timing when a cache memory is used.

Therefore, there is a problem that the instruction trace can be performed only at a timing different from the original operation timing of the program to be debugged.

In the conventional example shown in FIG. 18 for outputting the branch destination address to the outside, as shown in the timing chart at the time of the write bus cycle shown in FIG. If the external address bus is used in a data write cycle, it is impossible to output the branch destination address.

Similarly, as shown in the timing chart at the time of the bus hold shown in FIG. 21, the timing at which the branch instruction executed after the instruction inst4 executes the RF to output the branch destination address (in FIG. 21). At the timing indicated by the dotted line), the bus hold request signal (HLDRQ)
Is output and the hold request is accepted , that is,
If the external bus cannot be used due to the active state of the hold response signal (HLDAK), the instruction trace cannot be performed because the branch destination address cannot be output.

A branch instruction b having the same branch destination address (target) as shown in the instruction sequence shown in FIG.
If eqz, beqz, and jump exist in close proximity,
It becomes impossible to determine which branch instruction has been executed, and accurate instruction tracing cannot be performed.

An object of the present invention has been made in view of the above-mentioned drawbacks, and has been made to enable complete instruction tracing without being affected by the state of an external bus or an instruction sequence while using a built-in memory. Another object of the present invention is to provide a microprocessor capable of improving characteristics and performance and increasing speed.

[0036]

A feature of the microprocessor of the present invention is that a microprocessor responds to a clock signal every clock.
Program counter that updates and outputs the execution instruction address
And the execution instruction address in response to the clock signal.
When a cache hit occurs, the corresponding instruction code is
On output to a mishit and a cache memory for instruction storage for outputting a mishit signal, said receiving said instruction code
An instruction execution system that executes the instruction in response to a clock signal
Control means and the external instruction bus for holding the execution instruction address.
Connected bus interface and the program
And the clock signal to the instruction execution control means.
Generates a pipeline operation enable signal that permits supply of data
Pipeline execution means, and the execution instruction address
Update, output of the instruction code, and execution of the instruction
In a microprocessor which performs a pipeline operation in units of one clock , said pipeline stopping means
Is the pipeline when the mishit signal is generated.
In operation enable signal is deactivated and the clock signal
Signal supply, and the bus interface
When a mishit signal is generated or when the microprocessor
When the processor is in debug mode,
Output to the external bus .

[0037] In addition, the pipeline stop means is, before Symbol
A circuit combining inputs the Mi Suhitto signal, first for inputting an inverted signal of the combination the first control signal for the stop of the operation of the pipeline input from the output signal and an external circuit
And an output of the first AND circuit
The pipeline operation permission signal is supplied to a logic circuit to which a clock of pipeline control means is supplied, and when the first control signal becomes active, the pipeline operation is performed by the output of the first AND circuit. The pipeline signal is forcibly stopped by masking the output of the clock signal of the logic circuit by deactivating the enable signal, and the program counter and the instruction execution are forcibly stopped.
The row control means is configured to hold the internal state at this time.

Further, the pipeline control means to which the pipeline operation permission signal is supplied includes: a latch means for receiving an address of the instruction storage cache memory; and a latch means for receiving an address of the data cache memory.
Logic circuit for masking the clock signals respectively supplied to the latch means of said instruction execution control means for generating a predetermined control signal and the branch instruction from the decode result of the instruction code and instruction decoder address updating means of said program counter It is.

Further, the first control signal is a signal obtained by inverting a reception notification signal of a bus hold signal outputted from an internal circuit to an externally connected memory controller.

The pipeline stopping means uses a second control signal generated by an internal circuit in place of the first control signal input from the outside, and the second control signal is A second AND circuit which takes the logical product of the bus cycle start signal and the data strobe signal generated by the circuit, and an inverted output of the second AND circuit and an inverted signal of the reception notification signal of the bus hold signal. An OR circuit for outputting the second control signal by taking a logical sum, forcibly stopping the pipeline operation by activating the second control signal during bus hold, and It is configured to hold the internal state at the time.

Further, during the write bus cycle, the second
Constitute forcibly the pipeline operation by activating the control signal to stop.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing a system configuration using a microprocessor according to the first embodiment of the present invention, a microprocessor 1a, a main memory 2, and an address between the microprocessor 1a and the main memory 2 are shown. Memory controller 3 for controlling transmission and reception of data and data via address bus 5 and external data bus 6, HLDAK signal for notifying reception of bus hold transmitted from microprocessor 1a to memory controller 3, and this signal A configuration is provided in which the signal is inverted by the inverter 4 and returned to the microprocessor 1a as a pipeline operation stop signal pipeSTOP.

Referring to FIG. 2 showing the configuration of the microprocessor 1a according to the first embodiment of the present invention, it is assumed that a cache memory is built in as a memory, and a RISC having an instruction length of 32 bits is fixed. And operates in a synchronous 5-stage pipeline.

The microprocessor 1a includes an instruction cache unit 11, a data cache unit 12, a register file unit 13, an operation execution unit 14, and a program counter unit 1.
5, branch address generator 16, bus interface 1
7 and a control unit 18, and a mishit signal 501 output from the instruction cache unit 11 is input to the control unit 18 and the bus interface unit 17, respectively. The instruction cache unit 11 and the bus interface unit 17 provide an address output signal 50 of the execution instruction from the program counter unit 15.
3 are supplied respectively.

The output 504 of the register file RF13 is transmitted to the branch address generator 16 and the selector 1 of the operation execution unit 14.
01 to the latch 102 and the latch 104 , respectively, and the other output 505 of the register file 13 is supplied to the latch 103.

The other input terminal of the selection circuit 101 is connected to the bus 50
7, a signal is supplied from the instruction cache unit 11 and the control unit 18, and a signal is input from the bus interface unit 17 via the bus 506.

A branch signal is supplied from the bus 507 to the other input terminal of the branch address generator 16. The output is sent to the program counter section 15.
Is supplied to the branch address generator 16.

The outputs of latches 102 and 103 are ALU
105, and the output 508 of the ALU 105
Are supplied to the latch 106, the data cache unit 12, and the bus interface unit 17, respectively. Latch 104
The output 509 is supplied to one input terminal and a data cache unit 12 and bus interface unit 17 of the selection circuit 107 via the bus, the output of the latch 106 is supplied to the other input terminal of the selection circuit 107 .

The output of the selection circuit 107 is supplied to the latch 108, and the output is supplied to the input terminal of the register file 13.

The mishit signal 5 of the instruction cache unit 11
01 is supplied to the bus interface unit 17 and the control unit 18, respectively.

Referring to FIG. 3 showing the configuration of the instruction cache unit, the instruction cache unit 11 has a 4K byte direct map, that is, a configuration in which an entry is uniquely selected by the lower bits of the address. Instruction cache address I generated by program counter unit 15
The CAddr 503 is set to a pipeline operation enable signal pipe.
In response to the output signal of AND 119 that outputs the clock signal CLK when OK is at the high level, the latch 111 receives it, and the lower 12 bits (11 to 0) of the address are decoded by the decoder 112 to select one entry. The contents of the tag unit 113 and the data unit 114 held are read.

The tag unit 113 holds the upper 20 bits (31 to 12) of the address used when rewriting the contents of the instruction cache unit 11 via the input buffer 116, and from the tag unit 113 via the output buffer 117. By comparing the read high-order 20 bits with the high-order 20 bits of the fetch address output from the latch 111 by the comparator 115, it is possible to determine whether the contents of the entry hit or missed the requested address.

If the comparison result is a mismatch, the comparator outputs a high level, and the mishit signal ICMis
The control unit 18 is notified as s501. When a hit occurs, data read from the data section 114 via the output buffer 118 is output as an instruction code 507.

Referring to FIG. 4 showing the configuration of data cache unit 12, data cache unit 12 has the same configuration as instruction cache unit 11 shown in FIG.
1 is the instruction cache address ICAdd
r only changes to a data cache address DCAaddr, and the same applies to a 4K byte direct map.

The data address DCAddr generated by the operation execution unit 14 is received by the latch 111 via the bus 508, and the lower 12 bits (11 to 0) are decoded by the decoder 112 to select one entry.
The contents of the tag unit 113 and the data unit 114 held are read.

The lower 12 bits output from the tag unit 113 via the output buffer 117 are compared with the upper 20 bits of the data address by the comparator 115. If the comparison results do not match, the comparator 115 outputs a high level. Then, the control unit 18 and the bus interface unit 17 are notified as the mishit signal DCMiss 510.

The register file section RF13 reads the
Ports (signals 504 and 505) and one write port (signal 511) can be read simultaneously from two ports.

The operation execution unit 14 has a register file unit R
The data 504 and 505 are received from F13 and the actual calculation is performed by using the arithmetic and logic unit (ALU) 105.

Referring to FIG. 5 showing the configuration, the program counter section 15 generates an instruction fetch address and holds the address of the instruction currently being executed. The fetch address is usually signal 528 every cycle.
Is incremented by +4 by the adder 128, is selected by the selection circuit 127 in response to the selection signal 523 in the normal state, and the output 527 is used as the next fetch address. When the branch by the branch instruction is selected in response to the selection signal of the branch TAKEN address 52 4 generated by the branch address generation unit 16 as a fetch address, exception address when branching to fixed addresses exception 525 to select signal 522
The execution of the program is controlled by selecting a fetch address in response to the fetch address.

The addresses selected by the selection circuit 127 are sequentially transferred to the registers 124 to 126 in synchronization with the outputs of the AND circuits 121 to 123 for controlling the output of the clock signal by the pipeline operation confirmation signal pipeOK.
Each output address is selected by the selection circuit 129 and transferred to each pipeline stage as an address signal 503.

Referring to FIG. 6 showing the configuration, branch address generating section 16 includes current program counter value 527 and offset value 541 specified in the instruction code.
Is added by the adder 131, and the branch destination address 542 is added.
Generate The comparator 133 determines whether or not the value of the general-purpose register is all “0”. The output 546 and the branch instruction beqz547 are matched by the AND circuit 134, and whether the data 545 is a negative number is determined. By judging from the most significant bit, the condition of the branch instruction bltz 548 is matched with the AND circuit 135, and when they match each other, the result is notified to the program counter unit by the TAKEN signal 521 indicating that the branch is performed via the OR circuit 136. .

Referring to FIG. 7 showing the structure, bus interface section 17 is a section for transmitting and receiving signals to and from the outside. In particular, an external address bus, an external data bus, and an external main memory To exchange data with

When a mishit occurs in the instruction cache unit 11 and the data cache unit 12, the fetch address 527 output from the program counter 15 is received in the case of an instruction cache miss, and the data address is received in the case of a data cache miss. In response to data cache miss signal 510, selection circuit 147 selects a data address and outputs it to read address buffer 148,
The data is output to the external memory via the output buffer 149. At this time, the read address buffer 148 compares the strobe signal 553 at the time of cache miss output from the sequencer 141 with the DEBUG mode signal by the OR circuit 144, and when the DEBUG mode signal is low level, the strobe at the time of cache miss. If the signal 553 is at a high level, A
In synchronization with the clock signal 557 output from the ND circuit 145, an external main memory is accessed to read data, and then the data is passed to each cache memory. Above
Of a cache miss output from the sequencer 141
The strobe signal 553 of the external
Access is required, and the address for that
Is a signal for latching in the
The EBUG mode signal is not only used for cache misses,
Address buffer 148 to latch the address.
For the purpose of this, it is inputted to the OR circuit 144.

The data read from the external memory is transmitted to the sequencer 141 in response to the control signal data ready signal.
Signal 551 supplied from the external circuit 142 to a high level, the clock signal 554 is supplied from the AND circuit 142 to the read data buffer 155, the data read from the external memory is latched in the read data buffer 155, and the data cache is output via the output buffer 157. To the instruction cache unit 11 via the input buffer 156.

A write buffer 150 is provided, and when there is a write to the external main memory by a store instruction, the data address is output to the write address buffer, and the write signal 552 output from the sequencer 141 matches the clock signal. The address and data are held in synchronization with the AND circuit output 555, and the data is independently written from the output buffer 153 to the external main memory without affecting the pipeline operation.

[0067] When performing the debugging is an object of the present invention further provides a clock signal 557 of the AND circuit output by the DEBUG mode to the high level to the read address buffer 148. Data cache
Data cache miss signal if no error occurs
The inverted signal 556 of 510 becomes high level, and the selection circuit
147 selects a fetch address. Therefore, every
Read cycle fetch address to read address buffer 1
48, and the instruction fetch address is always
Can be output to the dress bus, and instruction tracing externally
It is possible to do.

Referring to FIG. 8 showing the configuration, control unit 18 includes instruction cache miss signal 501 and data key.
Input the cache miss signal 510, and
A combinational circuit 161 that outputs a low level if the signal is low, an AND circuit 163 that takes the logical product of its output 561 and the inverted signal of the pipeSTOP signal 101,
AN that masks the clock signal of the IPOK signal 562
D circuit 164 and decoder 1 for decoding instruction codes
66, to have a latch group 165 to generate the various commands from the signal of the decoding result. A cache miss has occurred
In this case, the output of the combinational circuit 161 becomes low level.
The pipeOK signal 5 which is the output of the AND circuit 163
62 is uniquely low level and the pipeline is stopped.
Let Also, an external pipeSTOP signal is activated.
And when it goes low,
The pipeOK signal 562, which is the output of the path 163, is unique.
To a low level to stop the pipeline. The latch group 165 is connected to the output clock signal 56 of the AND circuit 164.
Latches 168 to 17 for reading instruction code 564 in synchronization with 3 and sequentially transferring the instruction code to the next stage and outputting a transfer register number
0 and the output of the decoder 166 are read in synchronization with the clock signal 563, and the branch instructions beqz, bltz, JUM
p, a latch 171 for generating an ALU control signal, and an output of the latch 171 are read, and a signal Store, DCvali
A latch 172 for generating d and a latch 173 for reading the output of the latch 172 and generating a signal WBvalid are provided, and a NOR 167 generates a conditional branch instruction from the instructions beqz and bltz.

Referring to FIG. 9 showing the structure of the add (addition) instruction, each field has an instruction code 1 and an instruction code 2 representing the type of the instruction, and an addition source 1 so that the instruction code 564 can be easily decoded. Source 1 register No. for specifying the general-purpose register for reading the value of the register, Source 2 register No. for specifying the general-purpose register for reading the value of the addition source 2, and storage register No. for specifying the general-purpose register for storing the result Can be classified.

First, in order to read the value of the source, the source 1
The register number and the source 2 register number are output to the register file section RF13. The instruction decoder decodes the instruction code 1 and the instruction code 2 to determine the type of the instruction. If it is determined that the instruction is an add instruction, the ALU control signal is sent to the arithmetic execution unit 1 to use the ALU as an adder.
Output to 4.

Since it is necessary to store the addition result, WB
A WBvalid signal is output at the WB stage indicating that there is a write to the register file 13 at the stage,
Write control to the register file 13 is performed. The transfer register number for storing the addition result is held up to the WB stage and output to the register file unit 13.

Referring also to FIG. 10 showing a timing chart for explaining these operations, a pipe OK signal indicating that the pipeline may proceed from the mishit signal of the instruction cache unit 11 and the data cache unit 12 562 is generated.

Each pipeline has a pipeOK signal 562
Can be synchronized and proceed to the next stage only when is at the high level. A signal pipeSTOP for stopping the pipeline, which is a component of the present invention, is input from an external terminal, and is forced by outputting a low-level pipeOK signal at a timing when the cache miss signal 561 output from the combination circuit 161 becomes high. The pipeline can be stopped effectively.

The pipelines are IF, RF, EX, DC,
There are five stages of WB, and as shown in the timing chart of the pipeline operation from the cache hit to the cache miss shown in FIG. 11, the execution is normally performed in one stage and one cycle, and therefore, substantially one instruction and one cycle. The details of each stage and the operation of each section are as follows.

In the IF stage, the instruction cache unit 11 is accessed with the fetch address signal 503 generated by the program counter unit 15 to obtain an instruction code. If there is a mishit in the instruction cache unit 11, the external main memory is accessed through the bus interface unit 17 and an instruction code is input.

At the RF stage, the value of the general-purpose register to be used is read from the register file RF13. Also,
In the case of a branch instruction, a branch destination address is generated by the branch address generation unit 16, and if a branch condition is satisfied, the fetch address is switched to the branch destination address.

In the EX stage, the operation execution unit 14 executes an operation with the value of the general-purpose register read in the RF stage or the immediate value specified in the instruction code as an input. In the case of a load / store instruction, the calculated value becomes a data address.

In the DC stage, access is made to the data cache unit 12 at the time of a load instruction or a store instruction. For instructions other than load / store instructions, nothing is executed at this stage. EX for load / store instructions
The data cache unit 12 is accessed by the data address generated in the stage, and if a hit occurs, data is obtained. When a miss occurs, the external main memory is accessed via the bus interface unit 17.

In the WB stage, the register file 13
Write to.

When an instruction cache miss or a data cache miss occurs, the pipeOK signal of the control unit 18 goes low, and all the pipeline stages are stopped.

Next, the operation of the microprocessor 1a according to the first embodiment of the present invention will be described with reference to a timing chart. Referring to FIG. 12 showing a timing chart when an address cannot be output to an external bus due to a bus hold request or the like, a bus hold request is generated when an external system performs a DMA transfer using an address bus and a data bus. Occur. Therefore, during the bus hold period, the microprocessor 1a cannot drive the address bus and the data bus.

The notification of the bus hold request is made by the HLDREQ signal from the external system. The reception of the bus hold request of the microprocessor 1a is performed by HLDA
This is done by activating the K signal. Therefore, as shown in the system configuration diagram of FIG.
The K signal is inverted by the inverter 4 and input as a pipeSTOP signal. That is, the HLDAK signal is low active and the pipeSTOP signal is high active. Therefore, the pipe OK signal is masked during the bus hold, and the pipeline can be stopped.

[0083] Since all the pipeline stages are stopped, FIG. 1 2 For example, since inst4 in 4 clock cycle because the pipeSTOP signal is three clock cycles high level is performed, after all the instructions inst1~5 is WB, DC, EX, RF,
The internal state of each stage of the IF is maintained for three clock cycles.

Referring to FIG. 13 showing a timing chart when a data write to the external main memory is generated by a store instruction, a write bus cycle to the external main memory is controlled by a control output from the bus interface unit 17. The bus cycle is terminated when a signal is notified to the outside and the data can be received outside.

Therefore, only during the write bus cycle period from the start of the write bus cycle by the microprocessor 1a to the end of the data strobe, pip
The pipeline can be stopped by activating the eSTOP signal. At this time, the write address is output to the address bus instead of the instruction inst4, and the write data is output to the data bus while the data strobe signal is at the low level.

Next, referring to FIG. 14, which shows a configuration diagram of a microprocessor 1b according to a second embodiment of the present invention,
The configuration is the same as that of the first embodiment except that the pipeSTOP signal described in the second embodiment is generated in the bus interface unit. Is omitted.

FIG. 1 showing the configuration of the bus interface unit
Referring to FIG. 5, the bus interface unit of FIG. 6 used in the first embodiment differs from the bus interface unit of FIG.
The difference is that a TOP signal generation circuit is added. Since the other components are the same, the same reference numerals are given and the description of the configuration is omitted.

The bus interface unit 17 receives a bus hold request inside the sequencer 175 and
When the LDAK signal is activated, the HLD
The pipeSTOP signal generated by inverting the AK signal is activated. Further, during the write bus cycle period, the pipeline is stopped by taking the logical product of the bus cycle start signal and the data strobe signal, taking the logical sum of the inverted signal and the pipeSTOP signal, and activating the pipeSTOP signal. It is possible to do.

In the first and second embodiments described above, a microprocessor having a built-in cache memory has been described as an example. However, the present invention can be applied to a single-chip microcomputer having a built-in memory for storing instructions. Clearly there is.

[0090]

As described above, the microprocessor of the present invention comprises a bus selection means for outputting internal circuit information to an external bus when there is no memory access or bus hold request and no external bus is used; If an external bus is used, the pipeline operation is stopped and the output of the internal circuit information is suspended. Even if there is, the configuration is such that instruction tracing can be performed from the outside, so that the following effects are obtained as compared with the conventional technology. (1) Complete instruction tracing can be performed while using the built-in memory. If the internal memory is a cache memory, assuming that it takes 5 cycles to access the external main memory at the time of an instruction cache miss, as compared to the case where the use is prohibited, one instruction can be reduced by 4 cycles, and the entire instruction trace time is about It can be reduced by 80%. (2) When data write occurs and internal information cannot be output to the external bus, the internal pipeline can be stopped and the internal information can be held. (3) If the internal information cannot be output to the external bus due to the bus hold request, the internal pipeline is stopped,
The internal state can be kept. (4) By outputting internal information not only in the case of a branch but also in all instructions, instruction tracing can be performed in any instruction sequence.

The present invention can be applied not only to a case where a cache memory is built-in, but also to a single-chip microcomputer having a built-in instruction storage memory.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a first embodiment of a microprocessor of the present invention.

FIG. 3 is a configuration diagram of an instruction cache unit.

FIG. 4 is a configuration diagram of a data cache unit.

FIG. 5 is a configuration diagram of a program counter unit.

FIG. 6 is a configuration diagram of a branch address generation unit.

FIG. 7 is a configuration diagram of a bus interface unit.

FIG. 8 is a configuration diagram of a control unit.

FIG. 9 is a diagram illustrating an example of an instruction code of an add instruction.

FIG. 10 is a timing chart for explaining a pipeOK signal.

FIG. 11 is a timing chart showing a state where the pipeline is clogged when a cache hit → miss occurs.

FIG. 12 is a timing chart at the time of bus hold.

FIG. 13 is a timing chart of a write bus cycle.

FIG. 14 is a configuration diagram showing a second embodiment of the microprocessor of the present invention.

FIG. 15 is a configuration diagram of a bus interface unit.

FIG. 16 is a configuration diagram of a conventional microprocessor.

FIG. 17 is a timing chart of the microprocessor of FIG. 16;

FIG. 18 is another configuration diagram of a conventional microprocessor.

FIG. 19 is a timing chart of the microprocessor of FIG. 18;

20 is a timing chart of the microprocessor of FIG. 18 in a write bus cycle.

21 is a timing chart at the time of bus hold of the microprocessor of FIG. 18;

FIG. 22 is a diagram showing an example of an instruction sequence of the microprocessor of FIG. 18;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Memory controller 3 Main memory 4,146 Inverter 5 External address bus 6 External data bus 11,182 Instruction cache part 12 Data cache part 13 Register file part 14,185 Operation execution part 15 Program counter part 16 Branch address generation part 17, 181 bus interface unit 18 control unit 19 to 22, 186 to 189 terminal 101, 107, 127, 129, 147 selection circuit 102 to 104, 106, 108, 111, 168 to 1
73 Latch 111 ALU 112,166 Decoder 113 Tag section 114 Data section 115 Comparator 116,156,157 Input buffer 117,143,149,153,154 Output buffer 118 Input / output buffer 119,121-123,134,135,142 , 1
43, 145, 163, 164 AND circuit 124-125 Register 128, 131, 133 Adder 136, 144, 167, 176, 177 OR circuit 141, 175 Sequencer 148 Read address buffer 150 Write buffer 151 Write address buffer 152 Write data buffer 161 Combination circuit 165 Latch group 183 Instruction prefetch unit 184 Instruction decoder / address calculation unit

Claims (6)

(57) [Claims] 1. In response to a clock signal, every one clock
Program counter that updates and outputs the execution instruction address
And the execution instruction address in response to the clock signal.
When a cache hit occurs, the corresponding instruction code is
On output to a mishit and a cache memory for instruction storage for outputting a mishit signal, said receiving said instruction code
An instruction execution system that executes the instruction in response to a clock signal
Control means and the external instruction bus for holding the execution instruction address.
Connected bus interface and the program
And the clock signal to the instruction execution control means.
Generates a pipeline operation enable signal that permits supply of data
Pipeline execution means, and the execution instruction address
Update, output of the instruction code, and execution of the instruction
In a microprocessor which performs a pipeline operation in units of one clock, the pipeline stop means generates the mishit signal.
Deactivates the pipeline operation enable signal when
The supply of the clock signal is stopped as a
The interface indicates that the mishit signal has occurred.
Or the microprocessor is in debug mode
Output the execution instruction address to the external bus when
Microprocessor, characterized in that that. Wherein said pipeline stopping means, before you and circuit combination Suhitto inputting the signal, inverting the first control signal for the stop of the operation of the pipeline input from the output signal and the outside of the combination circuit and a first aND circuit for inputting a signal, to the logic circuit which is clocked pipeline control means the output of the first aND circuit as the <br/> pipeline operation permission signal And masking the output of the clock signal of the logic circuit by deactivating the pipeline operation permission signal at the output of the first AND circuit when the first control signal is activated. The pipeline operation is forcibly stopped by the program counter and the instruction execution control.
2. The microprocessor according to claim 1, wherein the control means is configured to hold the internal state at this time. Wherein said pipeline control means for the pipeline operation permission signal is supplied, calibration for the instruction storage
Generating a predetermined control signal and the branch instruction from the decode result of the latch means for receiving an address latch means and the data cache memory receiving an address of Mesh memory the flop <br/> program counter address updating means and the instruction code and instruction decoder 3. A microprocessor according to claim 2, wherein said microprocessor is a logic circuit for masking a clock signal supplied to each of said latch means of said instruction execution control means . 4. The microprocessor according to claim 2, wherein the first control signal is a signal obtained by inverting a reception notification signal of a bus hold signal output from an internal circuit to an externally connected memory controller. 5. The pipeline stopping means uses a second control signal generated by an internal circuit in place of the first control signal input from the outside, and the second control signal is A second AND circuit which takes the logical product of the bus cycle start signal and the data strobe signal generated by the circuit, and an inverted output of the second AND circuit and an inverted signal of the reception notification signal of the bus hold signal. A logical sum circuit that outputs a logical sum of the second control signal,
3. The microprocessor according to claim 2, wherein the pipeline control is forcibly stopped by activating the second control signal during bus hold, and the internal state at this time is maintained. 6. The microprocessor of claim 5 wherein the configured halting forcibly said pipeline operation by activating the at write cycle the second control signal.