JP2872767B2 - Contention control method - Google Patents

Description

The present invention relates to an apparatus for transmitting data in a predetermined form from a plurality of transmitting means connected to a common transmission path, for example, a contention suitable for use in a packet switch. Related to the control method.

(Prior Art) As is well known, in a packet switch, data continuously transmitted from a terminal or the like is divided into predetermined lengths,
Packetize and transmit. In this packet switch, a plurality of packet transmission circuits for transmitting packetized data for each packet are connected to a bus line as a common transmission path, and each of the transmission circuits independently transmits a packet. In such a packet switch, when a packet transmission request is simultaneously transmitted from the packet transmission circuit, the packet transmission circuit that has transmitted the packet data having the highest priority obtains the right to transmit the packet to the bus line. The priority of the packet data is determined by the priority correction data added to the head of each packet data.

In this case, when transmitting the packet data, each transmission circuit takes in the packet data transmitted on the bus line, and sequentially checks the transmitted packet data one bit at a time. As a result of the comparison, if they match, it is determined that there is no conflict, or that the priority of the packet of the other transmitting circuit in conflict is lower than that of the own transmitting circuit, and the transmission of the packet is continued. . Further, if a mismatch is detected between the two, it is assumed that a packet having a higher priority has been transmitted from the other transmission circuit, and transmission of the packet from its own transmission circuit is stopped at the time when the mismatch is detected. When the transmission of the packet is stopped, the priority of the priority correction data is increased, and when the bus line becomes free, the packet data with the priority correction data with the increased priority added to the head is transmitted again.

Conventionally, as a contention control system applied to such a packet switch, there is, for example, a system disclosed in Japanese Patent Laid-Open No. 57-87645. In this method, the first priority correction data is randomly generated, the transmission right is given to each transmission circuit with an equal probability, and when the transmission is not possible due to the competition, weighting is performed and the priority is given. In this case, the transmission right is almost equally obtained for each transmission circuit.

(Problems to be Solved by the Invention) By the way, data to be packetized includes various media such as voice, image, facsimile, and the like, and terminals handling these media have transmission forms at various bit rates. . When various kinds of media having different bit rates are packetized and multiplexed and transmitted through a common transmission path, the amount of data input to each packet transmission circuit greatly differs depending on the media handled.

However, in the prior art, when competing,
The right to transmit a packet is obtained on an average basis for each circuit, and when the amount of packets input to each packet transmission circuit is significantly different as described above, the characteristics of the transmission waiting time in each packet transmission circuit However, there was a disadvantage that it was not uniform. For this reason, in the conventional technology, in a packet transmission circuit having a large amount of input data, competition is likely to occur due to the large number of packet transmissions. Since the transmission right is obtained with the same probability as that of the transmission circuit, there is a problem that the transmission waiting time increases as compared with the packet transmission circuit having a small amount of data, and the subsequent data has a problem that the delay time increases.

The present invention solves such disadvantages of the prior art, and when packetizing media of various bit rates and multiplexing them on a common transmission line, the amount of data input to each packet transmission circuit is reduced. Even when the response differs depending on the correspondence, it is possible to make the characteristics of the transmission waiting time in each packet transmission circuit uniform, and therefore, a contention control method for preventing an increase in the delay time in the transmission circuit having a large amount of input data. The purpose is to provide.

(Means for Solving the Problems) In order to solve the above-described problems, the present invention is configured such that a plurality of transmitting means for transmitting input data in a predetermined form are connected to a common transmission path, and these transmitting means A plurality of buffers for sequentially storing input data in a predetermined form in each of transmission means, and a data input to these buffers, in a contention control system for performing contention control when data is simultaneously transmitted from a transmission line to a transmission line. Counting means for counting the amount, and control means for controlling transmission of the data stored in the buffer to the transmission line while monitoring the transmission state of the transmission line. In the case of contention with the data transmission from another transmitting means, the data amount at the time of contention accumulated in the buffer is determined based on the transmitted data amount and the count result of the counting means. When the data amount at the time of contention accumulated by the means is larger than the other transmitting means competing, the data is transmitted with priority.
Data transmission is stopped when the amount of data stored in another transmitting unit is larger than the amount of data stored in the own transmitting unit.

(Operation) According to the competition control system of the present invention, input data is sequentially accumulated in a plurality of buffers in a predetermined form while counting the amount of data to be input by the respective transmission means by the counting means. On the other hand, when the data is stored in the buffer in a predetermined form, the control means performs control to sequentially transmit the data from the stored buffer to the transmission path while monitoring the transmission path. In this case, when the data transmitted from the other transmitting means and the data transmission of the own transmitting means compete with each other, the control means accumulates at the time of the competition from the count result of the counting means and the data amount transmitted so far. When the amount of data being transmitted is larger than that of other transmitting means, data transmission is performed with priority over the data transmission of other transmitting circuits, and when the amount of data stored in the own transmitting means is smaller than that of other transmitting means. To stop sending competing data. When the transmission of data is stopped after losing the competition, if there is data to be input continuously, the count value in the counting means is advanced and the priority rises, and when the other transmission means sends a predetermined amount of data, Is controlled so that the data with the increased priority is transmitted with higher priority than other transmission means.

(Embodiment) Next, an embodiment of a contention control system according to the present invention will be described with reference to the accompanying drawings.

In the contention control system according to this embodiment, as shown in FIG. 1, N packet transmission circuits 1 to N are connected to a bus line B, which is a common transmission path, and each packet transmission circuit 1 to N The transmitted packet data Dp is the bus line B
The present invention is applied to a packet multiplexing apparatus that performs multiplex transmission.

Each of the packet transmission circuits 1 to N receives input data Di sent out in synchronization with a synchronization signal Fc having a predetermined speed from a preceding circuit (not shown), and inputs the input data Di to a predetermined length. , And sequentially transmits the packetized data Dp to the bus line B. The packet transmission circuits 1 to N are connected to the monitoring line A and the synchronization clock line C on the bus line B side, and read the monitoring data Da synchronized with the synchronization clock CK transmitted to the synchronization clock line C. The transmission of the stored packet data Pd is performed while monitoring the transmission of data from other transmission circuits on the bus line B.

The internal configuration of these packet transmission circuits 1 to N will be described using the packet transmission circuit 1 as an example.

The packet transmission circuit 1 accommodates a data line 100 to which input data Di is transmitted in an input selector 10 and outputs a synchronization signal Fc
Is accommodated in the packet counter 20.

Each time the packet counter 20 counts the synchronization signal Fc and counts the synchronization signal Fc for one packet, the packet counter 20 outputs the packet count signal H to the input selector 10 and each unit described later.
Are respectively sent out. Input selector 10
Is a selection circuit having a plurality of output lines 120, to which packet buffers 11 to 1m are connected, respectively, and to sequentially switch the output destination of the input data Di every time the packet count signal H is input.

The packet buffers 11 to 1m are storage circuits for sequentially storing data Di input via the input selector 10 in packet format, and perform data writing and reading under the control of the plane switching control unit 22.

In response to the synchronization signal Fc input via the packet counter 20, the plane switching control unit 22 sends the write signal W to predetermined empty packet buffers 11 to 1m, and outputs the packet count signal H sent from the packet counter 20. Is a control circuit for sequentially switching the packet buffers 11 to 1m each time the data Di is received and sequentially accumulating the data Di for each packet. Further, when the plane switching control unit 22 receives the data transmission signal So from the competition control unit 24, which will be described later, the plane switching control unit 22 transmits the read signal R to the predetermined packet buffers 11 to 1m storing the data Di. A selection signal G is sent to the output selector 26 so as to select the output line 130 of ~ 1 m. This output selector 26
Is a selection circuit for serially sending output data read from each of the packet buffers 11 to 1m to the open collector gate 28.

On the other hand, the packet transmission circuit 1 is a control circuit for performing control for turning on the open collector gate 28 and transmitting the packet data Dp to the bus line B, and includes a contention control unit 24 for performing contention control at the time of the transmission. Have.

The contention control unit 24 has a function of calculating the packet storage amount stored in its own transmission circuit from the packet count signal H transmitted from the packet counter 20 and the data transmission signal So transmitted to the plane switching control unit 22. Have. In this embodiment, the priority of packet data Dp transmission is determined when the amount of accumulated packets conflicts. This conflict control unit 24
Transmits the monitoring data Da including the calculated packet storage amount and the circuit number to the monitoring line A via the open collector gate 30 when transmitting the packet data Dp, and simultaneously transmits the monitoring line A via the reading line 140 Monitor. The readout line 140 is wired OR-connected to the output line 30a of the open collector gate 30, and the conflict control unit 24 has the sent out monitoring data Da and the monitoring data from another circuit sent out on the monitoring line A. Logical OR (OR) with Da is input.

The conflict control unit 24 has a function of collating the monitoring data read from the read line 140 with the transmitted monitoring data Da for each bit. Monitoring data sent as a result of verification
If Da and all the bits match, the surface switching control circuit 22
And the input terminal of the open collector gate 28 is set to the “High” level to transmit the packet data Pd. When the mismatch of the monitoring data Da is detected, the sending of the monitoring data Da is stopped, and the input terminal of the open collector gate 28 is held at the “Low” level.
After a predetermined time, for example, after inputting the packet count signal H, the monitoring data Da is transmitted again.

In this embodiment, the monitoring data Da
The packet storage amount sent as
Has a number of digits represented by a binary number corresponding to a number of 11 to 1 m,
As shown in FIG. 2, the data is sequentially transmitted from the upper digit.
Similarly, the circuit number is represented by a binary number corresponding to the number of the packet transmission circuits 1 to N, and is transmitted from the upper digit following the packet storage amount.

The circuit number register 32 stores this circuit number, and is read from the contention control unit 24 following the packet storage amount and sent out when the monitoring data Da is output. If the packet storage amounts are the same, the one with the larger circuit number transmits data preferentially.

Next, the contention control operation in this embodiment will be described with reference to FIGS.

To each of the packet transmission circuits 1 to N, input data Di is serially input from the preceding stage circuit every time data is generated. The input data Di is first transmitted to the packet buffer 11 via the input selector 10. At this time, the plane switching control unit 22 sends out the write signal W to the packet buffer 11 in response to the synchronization signal Fc input via the packet counter 20. Thus, the packet buffer 11 stores the input data Di in a predetermined packet format. Meanwhile, the counter
20 counts the synchronization signal Fc for each bit, and when the synchronization signal Fc for one packet is counted, sends the packet count signal H to the selector 10, the plane switching control unit 22, and the competition control unit 24.

The selector 10 that has received the packet count signal H switches the destination of the input data Di from the packet buffer 11 to the packet buffer 12. At the same time, the plane switching control unit 22 that has received the packet count signal H outputs the synchronization signal Fc
The write signal W is sent to the packet buffer 12 in synchronization with. As a result, data is accumulated in the packet buffer 12 in a packet format. Similarly, the packet counter 20
When the synchronization signal Fc is counted in step (1) and the packet count signal H is transmitted to each unit for each packet, the input data Di is accumulated in the order of the packet buffers 13, 14,.

On the other hand, the contention control circuit 24 to which the packet count signal H has been input outputs the monitoring data every time the packet count signal H is input.
The packet accumulation amount of Da is incremented, and the accumulation amount data and the circuit number are transmitted to the monitoring line A as the monitoring data Da.

When the packet storage amount is represented by, for example, 4 bits, the contention control unit 24 advances to “0000”, “0001”,.... This signal is transmitted one bit at a time for each input of the synchronous clock CK in order from the upper digit, and at the same time, the monitor data Da transmitted from the readout line 140 to the monitor line A in synchronization with the synchronous clock CK is taken in.

For example, as shown in FIG. 2, when the packet storage amount of the own circuit is the storage amount of 11 packets, a signal "1011" is sequentially transmitted to the monitoring line A from the upper digit in synchronization with the synchronization clock CK. At this time, if another circuit having a storage amount of 10 packets simultaneously sends monitoring data, that circuit sends out a signal of “1010”, and from the read line 140,
The logical sum "1011" is obtained in order from the upper digit. For other circuits, input “1011” in the same manner.
The transmission of the circuit numbers after the bit is stopped.

As described above, when a conflict occurs, a circuit having a large amount of stored packets at that time preferentially transmits data. Also, when data is not transmitted from another circuit, or when the amount of packets is equal, since the data so far matches, the circuit number is successively transmitted. Bit by bit,
Data with a higher circuit number is transmitted with priority.

When all the bits match, the conflict control unit 24 sends the data sending signal So to the plane switching control unit 22, and sets the input terminal of the open collector gate 28 to "High" level. As a result, the plane switching control unit 22 sends out the read signal R to the packet buffer 11 and sends out the selection signal G for selecting the output line of the packet buffer 11 to the output selector 26. As a result, the packet data Dp is read out serially from the packet buffer 11 and sent out to the bus line B. The contention control unit 24 subtracts the packet storage amount when the data transmission signal So is transmitted to the plane switching control unit 22.

When detecting a data mismatch when sending the monitoring data Da, the conflict control unit 24 stops sending the monitoring data Da, waits for the sending period of the packet data Dp of the other circuit, and again sends the monitoring data Da. Is sent. During this time, the input data Di is accumulated and the packet count signal H is changed to the contention control unit.
When the packet is transmitted to 24, the packet storage amount is increased, and the priority becomes higher.

As described above, in the contention control method according to the present embodiment, a plurality of packet buffers 11 to 1m are provided in each of the packet transmission circuits 1 to N, and contention is performed in accordance with the amount of packets stored in these packet buffers 11 to 1m. When the input data Di is large, even if it competes with other circuits with a small amount of data, the priority is high and the latency characteristics of all circuits are uniform. Can be set to Further, it is possible to reduce a delay time generated when there is a large amount of input data.

In this embodiment, the packet storage amount and the circuit number are each represented by a 4-digit binary number. However, the packet storage amount is determined according to the number of packet buffers, and the circuit number is determined by the packet transmission circuit. It may be determined according to the number of. Also, a packet transmission circuit may be provided for each medium, and the number of packet buffers may be determined as appropriate according to, for example, a packet transmission circuit having a large amount of input data.

(Effect of the Invention) As described above, according to the contention control method according to the present invention, a plurality of buffers and a data amount to be input to these buffers are assigned to each of a plurality of transmission means connected to a common transmission path. Counting means for counting, and control means for controlling transmission of the data stored in the buffer to the transmission line while monitoring the transmission state of the transmission line are provided. When there is contention with the data transmission from the transmitting means, the data amount at the time of contention stored in the buffer is calculated from the data transmission amount and the count result of the counting means. When the number is larger, data transmission is performed with priority over other competing transmission means, and the amount of data stored in the other transmission means is stored in the own transmission means. Since the data transmission is stopped when the data amount is larger than the data amount, the waiting time characteristics in all the transmission means can be set uniformly. Further, it is possible to reduce a delay time generated when there is a large amount of input data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a conflict control system according to the present invention, and FIG. 2 is a time chart for explaining the operation of the conflict control in the embodiment. Description of Signs of Main Parts 1 to N Packet Transmitter 10 Input Selector 11 to 1m Packet Buffer 20 Packet Counter 22 Surface Switching Controller 24 Competition Controller 26 Output Selector 28,30 Open Collector Gate 32 ... Circuit number register A ... Monitor line B ... Bus line C ... Synchronous clock line

Claims (2)

(57) [Claims] A plurality of transmission means for transmitting input data in a predetermined form are connected to a common transmission path, and when transmitting data from these transmission means to the transmission path, contention control is performed. In the competition control method, a plurality of buffers for sequentially accumulating input data in a predetermined form in each of the transmitting means, and a counting means for counting a data amount of data input to these buffers,
Control means for controlling transmission of data accumulated in the buffer to the transmission line while monitoring the transmission state of the transmission line, the control means comprising: Information is sent to the monitoring line, and the logical sum of the competing data amount information of the other transmitting means and the data amount information of the own transmitting means is taken in from the monitoring line, and the data amount information of the own transmitting means and the upper digit are taken. Are sequentially compared with each other, and when all digits match, data transmission is performed with priority over other competing transmission means. When a non-matching digit appears, transmission of the data amount information of the own transmission means is stopped immediately. And the data transmission is stopped. 2. A plurality of transmission means for transmitting input data in a predetermined form to a common transmission path, and when transmitting data from these transmission means to the transmission path, the contention control is performed. In the competition control method, a plurality of buffers for sequentially accumulating input data in a predetermined form in each of the transmitting means, and a counting means for counting a data amount of data input to these buffers,
Control means for controlling transmission of data accumulated in the buffer to the transmission line while monitoring the transmission state of the transmission line, the control means comprising: The information and the circuit number information of the own transmitting means obtained by converting a predetermined circuit number into a binary number are sent to the monitoring line, and the data amount information and the circuit number information of the competing other transmitting means and the data amount of the own transmitting means are transmitted. The logical sum of the information and the circuit number information is fetched from the monitoring line, and the data amount information and the circuit number information of the own transmitting means are sequentially compared with the higher order digits. Data transmission with higher priority than before, and immediately stops sending data amount information and circuit number information of the own transmission means and stops data transmission when a digit that does not match is found. A conflict control method characterized by causing a conflict.