JP2872882B2 - Video tape recorder power-on reset method and circuit, and video tape recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder power-on reset method and circuit, and a video tape recorder, and more particularly to a reset method and circuit using a color signal processing circuit.

[0002]

2. Description of the Related Art A recording / reproducing system of a video tape recorder (hereinafter, referred to as VTR) is divided into a luminance signal processing system and a chrominance signal processing system.
Frequency conversion is performed to reduce the frequency from Hz to about 630 kHz, and at the time of reproduction, color signal processing for inversely converting the frequency is performed. For frequency conversion, a PLL in which a voltage controlled oscillator VCO and a phase comparator are combined is used.

Here, since various noises are mixed when the power of the VTR is turned on, if the PLL is operated at the same time when the power is turned on, a normal operation cannot be performed due to the mixed noise. Time is this P
It is necessary to stop the operation of the LL. A circuit for this purpose is a so-called power-on reset circuit.

FIG. 5 shows an example of a conventional power-on reset circuit. The power supply voltage Vcc is connected to the collector terminal of the transistor 10 via the resistor R2, and the emitter terminal is grounded. An external capacitor 12 is connected to the base terminal, and a power supply voltage Vcc is connected through a resistor R1. Then, the reset terminal Reset is connected to the collector terminal of the transistor 10.

FIG. 6 is a timing chart of the power-on reset circuit shown in FIG.
(A) is a timing chart of the power supply voltage Vcc, FIG.
(B) is a timing chart of the external capacitor 12,
FIG. 6C shows a timing chart of the reset terminal Reset. When power is turned on, Vcc becomes 0
From V to 5V, and the reset terminal Res
et also changes to a predetermined potential. Further, the external capacitor 12 is charged by this Vcc, and the terminal voltage thereof gradually increases. Then, the charging of the external capacitor 12 is completed, and the terminal voltage thereof becomes a predetermined potential (in this embodiment, FIG.
When the voltage reaches 0.7 V as shown in FIG. 3B, the transistor 10 is turned on, so that the reset terminal Reset falls to almost 0 V. Therefore, a reset pulse is output from the reset terminal Reset for the charging time T of the external capacitor 12, and the operation is stopped by supplying the reset pulse to the PLL circuit.

[0006]

However, in order to completely eliminate the influence of noise mixed in when the power is turned on, it is necessary to make the reset pulse width of the reset signal as long as possible. As described above, since the reset pulse depends on the capacitance of the capacitor 12, the pulse width T
In order to increase the capacitance, the capacity of the capacitor 12 must be increased, and thus there is a problem that the capacitor 12 has to be externally connected. Of course, the reset pulse width T is T = R
· The pulse width T is determined by C · 0.7 / Vcc.
Although it is possible to increase R by changing R and Vcc, it is difficult to make R with built-in IC high resistance and Vcc is almost determined by the specifications of VTR. Have difficulty.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and it is an object of the present invention to eliminate the necessity of increasing the number of terminals and adding an external capacitor as in the prior art, and to reduce the power-on reset time. Another object of the present invention is to provide a power-on reset method and circuit capable of increasing the power-on reset, and a VTR provided with the power-on reset circuit.

[0008]

According to a first aspect of the present invention, there is provided a power-on reset method for generating a reset signal using a charging time of a capacitor provided in an ACC circuit of a color signal processing circuit. It is characterized by doing.

According to another aspect of the present invention, there is provided a power-on reset circuit according to claim 2, wherein a signal corresponding to the amplitude of the color burst signal output from the ACC circuit of the color signal processing circuit is transmitted via the first switch. A buffer circuit to be input to the input terminal, a differential terminal having one end of an input terminal connected to a DC power supply of a predetermined voltage, the other end connected to a constant current source via a second switch, and connected to a capacitor of the ACC circuit. And an amplifier, wherein when the power is turned on, the first switch is controlled to be open and the second switch is controlled to be closed to output a reset signal from the differential amplifier.

According to another aspect of the present invention, there is provided a video tape recorder, wherein an AC signal corresponding to the amplitude of a color burst signal output from an ACC circuit of a color signal processing circuit is transmitted via a first switch. A buffer circuit to be input to the input terminal, a differential terminal having one end of an input terminal connected to a DC power supply of a predetermined voltage, the other end connected to a constant current source via a second switch, and connected to a capacitor of the ACC circuit. And a power-on reset circuit that controls the first switch to open and the second switch to close when power is turned on and outputs a reset signal from the differential amplifier.

[0011]

An ACC (Automatic Chroma Control) circuit for adjusting the amplitude of the color subcarrier is used in the color signal processing circuit of the VTR. This ACC circuit has several tens of microfarads for detection.
Is used. The present invention uses this AC
Focusing on the capacitor of the C circuit, a power-on reset signal is generated using the charging time of the capacitor.

That is, the buffer circuit and the differential amplifier are connected to the capacitor of the ACC circuit, and when the power is turned on, the first switch in the buffer circuit is controlled to open to stop the operation of the buffer circuit and the second switch is controlled to close. Then, the capacitor of the ACC circuit is charged by the differential amplifier to generate a power-on reset signal.

When a desired power-on reset signal is obtained, the second switch is controlled to open to stop the operation of the differential amplifier, and the first switch is controlled to close to operate the buffer circuit, and the capacitor is operated. Operate as a detection capacitor of the ACC circuit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a power-on reset method and circuit of the present invention and a VTR provided with the power-on reset circuit will be described below with reference to the drawings.

FIG. 1 shows an ACC circuit section of a color signal processing circuit of a VTR in this embodiment. As described above, the ACC circuit detects the amplitude of the color burst signal by ACC detection, and limits the gain of the amplifier by a DC voltage generated based on the detected signal. In FIG. 1, a color burst signal is input to the base of the transistor Q3. When the amplitude of the color burst signal changes, the emitter current of the transistor Q2 changes accordingly, and an AC signal corresponding to the amplitude of the color burst signal is output from the emitter of the transistor Q2. Then, by integrating the AC signal with the capacitor 16, a DC voltage signal corresponding to the amplitude of the color burst signal can be obtained. Then, the DC voltage signal (ACC detection voltage) is amplified by the amplifier 18 and then output to the amplifier circuit to obtain a constant level color signal.

The power-on reset circuit of the present embodiment makes use of such a configuration of the ACC circuit and obtains a power-on reset signal using the capacitor 16 for ACC detection. Therefore, the power-on reset circuit 20 of this embodiment is connected between the emitter terminal of the transistor Q2 of the ACC circuit and the capacitor 16 and between the capacitor 16 and the amplifier 18 as shown in FIG.

FIG. 2 shows a circuit configuration of the power-on reset circuit 20 of this embodiment. The power-on reset circuit 20 according to this embodiment includes a buffer circuit, a differential amplifier, and a constant current source. The buffer circuit includes transistors Q5 and Q6, a constant current source I0, and a switch SW1, and the constant current source I0 and the emitter of the transistor Q5 are connected via a switch SW1. The base of the transistor Q6 is connected to the emitter of the transistor Q5, and the base of the transistor Q5 receives an AC signal corresponding to the amplitude of the color burst signal output from the emitter of the transistor Q2 of the ACC circuit. .

On the other hand, the differential amplifier is composed of an OP amplifier 20a, a predetermined DC power supply Va is input to a non-inverting input terminal of the OP amplifier 20a, and a constant current source I0 is connected to an inverting input terminal via a switch SW2. Connected and AC
The C detection capacitor 16 is connected. As shown by a broken line in FIG. 2, the output of the OP amplifier 20a and the switches SW1 and SW2 are linked, and when the output of the OP amplifier 20a is equal to or more than a predetermined value, SW1 is turned off.
When SW2 is turned on and the output of the OP amplifier 20a falls below a predetermined value, SW1 is turned on and SW2 is turned off.

FIG. 3 is a timing chart of the power-on reset circuit 20 of this embodiment.
(A) is a timing chart of the power supply voltage Vcc, FIG.
3B is a timing chart of the terminal voltage of the ACC detection capacitor 16, and FIG. 3C is a timing chart of the output of the OP amplifier 20a, that is, the timing chart of the reset terminal Reset. When the power is turned on, the power supply voltage Vcc rises from 0V to 5V. At this time, the output of the OP amplifier 20a becomes a predetermined value or more because the predetermined DC power supply voltage Va is applied to the non-inverting input terminal, and the switch SW1 is turned off,
SW2 is turned on. Then, the ACC detection capacitor 16 is charged from the constant current source I0 via the switch SW2, and its terminal voltage rises as shown in FIG. On the other hand, the output of the OP amplifier 20a becomes equal to or more than a predetermined value, and a reset signal is output.

When the ACC detection capacitor 16 is charged and its terminal voltage reaches Va, the OP amplifier 20a
Is 0, and the reset signal falls to 0V again. Therefore, the capacitor 16 is charged to the predetermined voltage Va.
Reset pulse T = C.
Va / I0 will be output. On the other hand, when the differential output of the OP amplifier 20a becomes 0 V, the switch SW1 is turned on and the switch SW2 is turned off. Then, both the transistors Q5 and Q6 of the buffer circuit are turned on, the capacitor 16 is charged / discharged by the output signal from the emitter of the transistor Q6, the ACC detection voltage similar to the conventional one is output to the amplifier 18, and the ACC detection is performed.

FIG. 4 shows an example of a more specific circuit configuration of the power-on reset circuit shown in FIG.
The buffer circuit includes transistors Q11, Q12, Q13,
Q15 and transistors Q12 and Q15
Constitute a constant current source. On the other hand, transistor Q1
6, Q17 and Q18 constitute a differential amplifier, and transistors Q14 and Q19 constitute a constant current source for supplying a constant current to the differential amplifier. In the initial state, the transistors Q11, Q12, Q13, Q15, Q16 are off, and the transistors Q14, Q17, Q18, Q1
9, Q20, Q21 and Q22 are turned on. Therefore, the reset pulse is output by the current flowing through the transistor Q22, and the ACC detection capacitor 16 is charged by the current flowing through the transistor Q14. As charging is performed, the potential at point Q in the figure gradually increases,
When the potential reaches the same potential as the base potential Va of the transistor Q17, the transistor Q16 turns on. Then, the transistor Q17 changes from on to off.

As a result, the transistors Q14, Q19,
Q22 is also turned off, the output of the reset pulse is stopped, and the transistors Q11, Q12, Q13, Q1
5 change from off to on, a signal corresponding to the amplitude of the color burst signal applied to the base of the transistor Q11 is detected by the ACC detection capacitor 16, and amplified and output by the amplifier 18.

Therefore, the circuit configuration shown in FIG. 4 is equivalent to the circuit configuration shown in FIG. 2, and the charging time of the ACC detection capacitor 16 (the time until reaching the predetermined potential Va).
It is understood that only the reset pulse is output.

As described above, the present embodiment focuses on the detection capacitor of the ACC circuit, and can generate the reset signal for power-on reset without newly adding an external capacitor. The VTR can be stopped and the operation of the VTR can be started normally.

FIG. 7 shows a video signal processing block diagram of a VTR provided with the power-on reset circuit of this embodiment. In the recording system, a luminance signal (Y signal) and a chrominance signal (C signal) are separated by a Y / C separation circuit 100 such as a comb filter, and the Y signal recording processing circuits 102 and C
The signal is supplied to the signal recording processing circuit 104. The Y signal recording processing circuit 102 performs FM modulation after clamping the leading end of the synchronization and performs pre-emphasis, and the C signal recording processing circuit 104 maintains the color signal amplitude constant by the ACC circuit as described later, and performs frequency conversion by the heterodyne method. I do. Then, the processed Y signal and C signal are converted to a Y / C mixer 10.
6 and the video head 1 via the recording amplifier 108.
Supply 10

In the reproducing system, the video head 1
After amplifying the reproduction signal from 10 by the reproduction amplifier 112,
The signal is separated into a Y signal and a C signal by a Y / C separator 100, and a Y signal reproduction processing circuit 116 and a C signal reproduction processing circuit 11, respectively.
8 In the Y signal reproduction processing circuit 116, the Y signal is FM-demodulated and then de-emphasized, and in the C signal reproduction processing circuit 118, the frequency is converted after the amplitude is adjusted by the ACC circuit as described later. Then, the reproduced Y signal and C
The signal is supplied to a Y / C mixer 120, where the Y signal and the C signal are mixed to produce a video output.

FIG. 8 is a block diagram showing the configuration of the color signal processing system of the VTR of this embodiment. As described above, in the recording system, the ACC circuit 104a makes the amplitude constant, performs the frequency conversion to reduce the frequency to 630 kHz by the frequency converter, and outputs the signal through the low-pass filter 104c. On the other hand, in the reproduction system, the ACC circuit 118a makes the amplitude constant, and the frequency converter 118b makes the frequency 3.5.
The frequency is returned to 8 MHz, and the reproduced output is output via the BPF 118c. The power-on reset circuit 20 of this embodiment is provided in the ACC circuits 104a and 104b, and outputs a reset signal at power-on.

[0028]

As described above, the VT according to the present invention is used.
According to the power-on reset method and circuit of R, a power-on reset signal can be generated for a sufficient time without newly increasing the number of connection pins and adding an external capacitor.

The provision of such a power-on reset circuit assures the normal operation of the PLL.
A highly reliable VTR can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a color signal processing system using a power-on reset circuit of the present invention.

FIG. 2 is a circuit diagram of a power-on reset circuit in the same embodiment.

FIG. 3 is a timing chart showing an operation of the power-on reset circuit in the embodiment.

FIG. 4 is a circuit diagram of a power-on reset circuit according to the same embodiment.

FIG. 5 is a circuit diagram of a conventional circuit.

FIG. 6 is a timing chart illustrating the operation of a conventional circuit.

FIG. 7 is a block diagram of a video signal processing circuit of a VTR according to the present embodiment.

FIG. 8 is a block diagram of a color signal processing circuit of a VTR according to the present embodiment.

[Explanation of symbols]

 16 ACC detection capacitor 18 Amplifier 20 Power-on reset circuit

Claims (3)

(57) [Claims] 1. A video tape recorder power-on reset method for outputting a reset signal when the power of a video tape recorder is turned on, wherein the reset signal is generated by using a charging time of a capacitor provided in an ACC circuit of a color signal processing circuit. A power-on reset method for a video tape recorder, comprising: 2. A power-on reset circuit of a video tape recorder which outputs a reset signal when the power of the video tape recorder is turned on, wherein an AC signal corresponding to the amplitude of a color burst signal output from an ACC circuit of a color signal processing circuit is output. A buffer circuit input through one switch, one end of an input terminal is connected to a DC power supply of a predetermined voltage, and the other end is connected to a constant current source through a second switch and to a capacitor of the ACC circuit; A differential amplifier that controls opening of the first switch and closing of the second switch when the power is turned on, and outputs a reset signal from the differential amplifier. Power-on reset circuit. 3. An AC signal according to the amplitude of a color burst signal output from an ACC circuit of a color signal processing circuit is output from a first AC signal.
A buffer circuit input through a switch, one end of an input terminal is connected to a DC power supply of a predetermined voltage, and the other end is connected to a constant current source through a second switch and to a capacitor of the ACC circuit. And a power-on reset circuit that controls the first switch to open and the second switch to close when power is turned on and outputs a reset signal from the differential amplifier. Video tape recorder.