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JP2873508B2 - FM demodulation circuit - Google Patents
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JP2873508B2 - FM demodulation circuit - Google Patents

FM demodulation circuit

Info

Publication number
JP2873508B2
JP2873508B2 JP3003736A JP373691A JP2873508B2 JP 2873508 B2 JP2873508 B2 JP 2873508B2 JP 3003736 A JP3003736 A JP 3003736A JP 373691 A JP373691 A JP 373691A JP 2873508 B2 JP2873508 B2 JP 2873508B2
Authority
JP
Japan
Prior art keywords
phase
output
signal
input
demodulation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3003736A
Other languages
Japanese (ja)
Other versions
JPH05175735A (en
Inventor
▲高▼晴 佐伯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3003736A priority Critical patent/JP2873508B2/en
Publication of JPH05175735A publication Critical patent/JPH05175735A/en
Application granted granted Critical
Publication of JP2873508B2 publication Critical patent/JP2873508B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、ハイファイVTRなど
の、FM変調記録機器のFM復調回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM demodulation circuit for an FM modulation recording device such as a Hi-Fi VTR.

【0002】[0002]

【従来の技術】従来の、ハイファイVTRなど音声信号
のFM変調記録機器の再生には、電圧制御発振器と位相
比較器と低域ろ波器からなるフェーズロックドループ
(PLL)復調回路が用いられ、再生時は、テープ上のド
ロップアウト等による再生FM信号の乱れが発生し、そ
れにより大きな雑音がでるためホールド等の手段によ
り、その雑音が出力されないようにする必要がある。こ
の再生FM信号の乱れは入力FM信号を検波して検出
し、FM信号が小さいとき上記ホールドをかけるものが
一般的である。
2. Description of the Related Art A conventional phase locked loop composed of a voltage controlled oscillator, a phase comparator and a low-pass filter is used for reproduction of a conventional FM modulation recording device for an audio signal such as a Hi-Fi VTR.
A (PLL) demodulation circuit is used. At the time of reproduction, disturbance of the reproduced FM signal due to dropout on the tape occurs, and a large noise is generated. Therefore, the noise is prevented from being output by means such as a hold. There is a need. The disturbance of the reproduced FM signal is generally detected by detecting the input FM signal, and when the FM signal is small, the above hold is generally applied.

【0003】図2は、そのような従来のFM復調回路の
機能ブロック図を示しており、1は入力端子、2は出力
端子、3は入力のFM変調信号を増幅するとともに、振
幅を制限して矩形波信号を形成するリミッタ(LIM)、
4は位相比較器(PC)、5は電圧制御発振器(VCO)、
6はローパスフィルタ(LPF)、7'はホールド回路(H
OLD)、8はドロップアウト検波器(DET)であり、
入力されるFM変調信号が小さい時、ホールド回路7'
にホールド信号を出力する。
FIG. 2 is a functional block diagram of such a conventional FM demodulation circuit, wherein 1 is an input terminal, 2 is an output terminal, and 3 is an amplifier for amplifying an input FM modulation signal and limiting the amplitude. Limiter (LIM) for forming a square wave signal
4 is a phase comparator (PC), 5 is a voltage controlled oscillator (VCO),
6 is a low-pass filter (LPF), 7 'is a hold circuit (H
OLD), 8 is a dropout detector (DET),
When the input FM modulation signal is small, the hold circuit 7 '
Output the hold signal.

【0004】この回路は入力端子1から入力されるFM
変調信号を、位相比較器4、電圧制御発振器5、および
LPFからなるPLL復調回路によって復調するが、復
調するテープにドロップアウト等があって再生FM信号
に乱れを生じ、雑音を発生するのを防止するため、入力
のFM変調信号を検波し、その出力レベルが小さい場
合、ホールド回路7'にホールドさせるものである。
This circuit uses an FM signal input from an input terminal 1.
The modulated signal is demodulated by a PLL demodulation circuit including a phase comparator 4, a voltage controlled oscillator 5, and an LPF. The reproduced FM signal may be disturbed due to a dropout or the like in a demodulated tape, and noise may be generated. To prevent this, an input FM modulation signal is detected, and when the output level is low, the hold circuit 7 'holds the signal.

【0005】[0005]

【発明が解決しようとする課題】従来のドロップアウト
検出回路では、入力FM信号の大きさのみで、ホールド
回路7'のオン/オフを判断しているため、信号の大き
さはそれほど小さくなくても位相が不連続でFM変調信
号に大きな雑音がでる場合、あるいは、入力FM信号に
大きな雑音が重畳して入力信号のS/Nが極端に劣化す
るような場合、ホールドが不能で、その結果、大きな雑
音が出力されてしまう欠点があった。
In the conventional dropout detection circuit, since the ON / OFF of the hold circuit 7 'is determined only by the magnitude of the input FM signal, the magnitude of the signal is not so small. In the case where the phase modulation is discontinuous and large noise appears in the FM modulation signal, or when large noise is superimposed on the input FM signal and the S / N of the input signal is extremely deteriorated, the hold cannot be performed. However, there is a disadvantage that a large noise is output.

【0006】本発明は、上述のような欠点を排除するF
M復調回路の提供を目的とする。
SUMMARY OF THE INVENTION The present invention provides an F
It is intended to provide an M demodulation circuit.

【0007】[0007]

【課題を解決するための手段】電圧制御発振器の出力を
互いに90度位相のずれた2つの出力に分け、一方を用い
てPLL復調するとともに、他方を用いて平衡変調する
ことにより、入力信号の大きさだけでなく位相情報をも
含めたサンプルホールド回路を有するFM復調回路によ
って解決する。
Means for Solving the Problems The output of a voltage controlled oscillator is divided into two outputs having a phase shift of 90 degrees from each other, and PLL demodulation is performed by using one of the outputs and balanced modulation is performed by using the other to obtain an input signal. The problem is solved by an FM demodulation circuit having a sample and hold circuit including not only the size but also the phase information.

【0008】[0008]

【作用】平衡変調器のクロック入力のフェイズシフタの
第2出力は、PLL復調用の位相比較器のクロック入力
となるフェイズシフタの第1出力と位相が90度ずれてお
り、一方、PLL回路がロックした状態では、位相比較
器のクロック入力とFM変調信号入力とは位相が90度ず
れているため、通常、平衡変調器のクロック入力とFM
変調信号入力とは同位相であり、そのとき、平衡変調器
の出力は最大である。いま、入力のFM変調信号の位相
が不連続に変化した場合、平衡変調器のクロック入力の
位相は急には応動しないため平衡変調器の出力が小さく
なり、位相の不連続性が検出でき、それによってホール
ドがかけられることになる。なお、入力FM変調信号の
大きさが小さくなった場合にも、平衡変調器の出力が小
さくなるから、従来同様ドロップアウトが検出でき、ホ
ールドがかけられるから雑音の発生を防止できる。
The second output of the phase shifter at the clock input of the balanced modulator is 90 degrees out of phase with the first output of the phase shifter at the clock input of the phase comparator for PLL demodulation. In the locked state, the clock input of the phase comparator and the FM modulation signal input are 90 degrees out of phase.
The modulating signal input is in phase, at which time the output of the balanced modulator is at a maximum. Now, when the phase of the input FM modulation signal changes discontinuously, the phase of the clock input of the balanced modulator does not respond suddenly, so the output of the balanced modulator becomes small, and the discontinuity of the phase can be detected. This will result in a hold. In addition, even when the magnitude of the input FM modulation signal becomes small, the output of the balanced modulator becomes small, so that the dropout can be detected as in the conventional case, and the hold can be applied, thereby preventing the generation of noise.

【0009】[0009]

【実施例】以下、本発明の実施例を図面を用いて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

【0010】図1は本発明の一実施例のFM復調回路の
ブロック図で、9はフェイズシフタ(PS)、10は平衡変
調器(BM)であり、その他の符号は図2の説明を援用す
る。
FIG. 1 is a block diagram of an FM demodulation circuit according to an embodiment of the present invention, wherein 9 is a phase shifter (PS), 10 is a balanced modulator (BM), and other symbols are the same as those in FIG. I do.

【0011】この構成で、位相比較器4、電圧制御発振
器5、ローパスフィルタ6はPLL復調回路を構成して
おり、そのロック状態では位相比較器4の2つの入力
イ、ロは周波数は同じで、90度位相がずれた状態となっ
ている。一方、フェイズシフタ9の2つの出力ロ、ハ
は、互いに位相が90度ずれているため、平衡変調器10の
クロック入力ハとFM変調信号入力ニとは同位相となっ
ており、このとき、平衡変調器10の出力は最大となって
いる。いま、入力FM変調信号の位相が不連続に変化し
た場合、平衡変調器10のクロック入力の位相は急には変
化しないため、平衡変調器10の2入力ハ、ニに位相差が
生じ、出力が小さくなる。したがって、平衡変調器10の
出力が小さいとき、ホールドをかけるようにすれば、入
力FM信号ニの位相が不連続な場合でも雑音の出力を防
ぐことができる。また、ドロップアウトなどにより、入
力FM信号が小さくなった場合にも、平衡変調器10の出
力は小さくなるため、ホールドは従来同様にかけること
ができる。
In this configuration, the phase comparator 4, the voltage controlled oscillator 5, and the low-pass filter 6 constitute a PLL demodulation circuit. In the locked state, the two inputs A and B of the phase comparator 4 have the same frequency. , 90 degrees out of phase. On the other hand, since the two outputs B and C of the phase shifter 9 are out of phase with each other by 90 degrees, the clock input C of the balanced modulator 10 and the FM modulation signal input D have the same phase. The output of the balanced modulator 10 is at a maximum. Now, when the phase of the input FM modulation signal changes discontinuously, the phase of the clock input of the balanced modulator 10 does not change suddenly. Becomes smaller. Therefore, when the output of the balanced modulator 10 is small, if the hold is applied, the output of noise can be prevented even when the phase of the input FM signal is discontinuous. Further, even when the input FM signal becomes small due to dropout or the like, the output of the balanced modulator 10 becomes small, so that the hold can be performed as in the related art.

【0012】以上、本発明を説明したが、入力FM信号
の大きさがあまり変化せず、位相の変化のみが大きい場
合にもホールドをかけることができるため、FM記録し
たテープの再生機器のヘッド切り換え時のスイッチング
によるノイズの発生対策のサンプルホールド回路として
も使用できる。
The present invention has been described above. However, since the hold can be performed even when the magnitude of the input FM signal does not change much and only the phase change is large, the head of the tape-recording tape reproducing apparatus can be used. It can also be used as a sample-and-hold circuit for countermeasures against noise generation due to switching during switching.

【0013】[0013]

【発明の効果】以上、説明して明らかなように本発明
は、入力FM信号の欠落した場合のみでなく、位相の不
連続な場合にも有効な雑音除去が可能であるから、優れ
たFM復調回路が構成できる効果がある。
As described above, the present invention can effectively remove noise not only when the input FM signal is lost but also when the phase is discontinuous. There is an effect that a demodulation circuit can be configured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例のFM復調回路のブロック図
である。
FIG. 1 is a block diagram of an FM demodulation circuit according to one embodiment of the present invention.

【図2】従来のFM復調回路のブロック図である。FIG. 2 is a block diagram of a conventional FM demodulation circuit.

【符号の説明】[Explanation of symbols]

3…リミッタアンプ、 4…位相比較器、 5…電圧制
御発振器、 7…サンプルホールド回路、 8…ドロッ
プアウト検波器、 9…フェイズシフタ、 10…平衡変
調器。
3: Limiter amplifier, 4: Phase comparator, 5: Voltage controlled oscillator, 7: Sample and hold circuit, 8: Dropout detector, 9: Phase shifter, 10: Balanced modulator.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電圧制御発振器と、その出力を互いに90
度の位相差を有する第1、第2の出力に形成するフェイ
ズシフタと、前記第1の出力と復調すべきFM変調信号
の位相を比較して、位相差に応じた電圧を取り出す位相
比較器と、その出力をローパスフィルタを介して上記電
圧制御発振器に入力してなるPLL復調回路と、及び上
記フェイズシフタの第2の出力をクロック入力とし、F
M変調信号を信号入力とする平衡変調器と、上記ローパ
スフィルタの出力を前記、平衡変調器の出力に応じてサ
ンプルとホールド動作をするサンプルホールド回路とを
有し、上記位相比較器から入力されたFM変調信号を復
調信号として前記サンプルホールド回路から取り出すこ
とを特徴とするFM復調回路。
1. A voltage controlled oscillator and its output are connected to each other by 90
A phase shifter formed at first and second outputs having a phase difference of degree, and a phase comparator for comparing the phase of the first output with the FM modulation signal to be demodulated and extracting a voltage corresponding to the phase difference A PLL demodulation circuit having its output input to the voltage controlled oscillator via a low-pass filter, and a second output of the phase shifter as a clock input;
A balanced modulator having an M-modulated signal as a signal input; and a sample-and-hold circuit for performing a sample and hold operation on the output of the low-pass filter in accordance with the output of the balanced modulator. An FM demodulation circuit for extracting the FM modulated signal from the sample hold circuit as a demodulated signal.
JP3003736A 1991-01-17 1991-01-17 FM demodulation circuit Expired - Fee Related JP2873508B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3003736A JP2873508B2 (en) 1991-01-17 1991-01-17 FM demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3003736A JP2873508B2 (en) 1991-01-17 1991-01-17 FM demodulation circuit

Publications (2)

Publication Number Publication Date
JPH05175735A JPH05175735A (en) 1993-07-13
JP2873508B2 true JP2873508B2 (en) 1999-03-24

Family

ID=11565521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3003736A Expired - Fee Related JP2873508B2 (en) 1991-01-17 1991-01-17 FM demodulation circuit

Country Status (1)

Country Link
JP (1) JP2873508B2 (en)

Also Published As

Publication number Publication date
JPH05175735A (en) 1993-07-13

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