JP2873533B2 - ATMHEC synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM HEC (Asynchrono) for realizing a cell synchronization system with a distributed sample scrambler used for a cell-based ATM interface.
us TransferMode Header Error Control) Related to a synchronous circuit.

[0002]

2. Description of the Related Art Conventionally, a cell synchronization system of a cell-based ATM interface has been described in CCITT I.C. 432B-ISDN
A distributed sample scrambler and a cell synchronization mechanism are recommended in the user / network interface physical layer recommendation. In this recommendation, a distributed sample scrambling mechanism and a cell synchronization mechanism are recommended. According to this, the cell synchronization is established in the receiving-side HEC synchronization circuit using the header error control code (HEC code) assigned to the fifth byte of the cell header. In this process, a hunting state and a pre-synchronization state are reached depending on the number of synchronization continuation cells to reach a synchronization establishment state. In this process, in the hunting state and the pre-synchronization state, the cell synchronization operation is performed using the lower 6 bits among all 8 bits of the HEC code. Thereafter, a result in which the synchronization state has continued for a prescribed number of times or more is detected, and the state enters the synchronization establishment state. In the state of synchronization establishment, all 8 HEC codes
Using the bits, cell synchronization is maintained, one-bit error correction of header part data, or multiple-bit error detection is performed (FIG. 5). Here, the hunting state is a state in which a cell boundary is searched in an out-of-synchronization state, and the pre-synchronization state is a state in which it is checked for each bit whether a header error control code rule applies to an assumed header area. Say.

The code synchronization operation between transmission and reception of the distributed sample scrambler is performed in a cyclic local PRBS generation circuit on the receiving side. This synchronization establishing operation is performed in parallel with the cell synchronization operation, and is started from a point in time when the cell synchronization is in the pre-synchronization state. The synchronization establishment operation of the cyclic local PRBS generation circuit is such that when the cell synchronization is in the pre-synchronization state, the upper two bits of the HEC code (HEC7, HEC7,
8) and modulo addition of the upper 2 bits of the HEC code resulting from the operation from the received 4 bytes of header part data.
As a result, the source PRBS (Pseudo Random Bit)
Sequence), and compares the extracted transmission bits with the sample bits of the local PRBS on the receiving side at a cell half cycle interval. The result of the comparison is stored in the cyclic local P
Apply to the feedforward tap of the RBS generation circuit. The code synchronization state of the recursive local PRBS generation circuit is transition-managed and established by the applied number of times, including a synchronization pull-in state, a confirmation state for checking the number of code matches after pull-in, and a stable state.

[0004] Through such a process, after the cell synchronization is in a synchronization established state and the code synchronization of the cyclic PRBS generating circuit is in a stable state, the cell synchronization operation is performed in the upper two bits of the descrambled HEC code. Is performed with all the 8 bits of the HEC code including. Error detection of 2 bits or more and 1
The error correction of the header portion of the bit is performed, and the H of the cell header portion is corrected.
The received cell data excluding the EC code is descrambled and sent to the next processing step.

(Description of Cell Synchronization Circuit for Cell-based ATM Interface with Distributed Sample Scrambler)
Conventional cell-based ATM with distributed sample scrambler
The cell synchronization circuit for the interface is shown in FIG.
This will be specifically described with reference to the time chart of FIG. The received cell data (A) is input to a CRC (Cyclic Redundancy Check) operation circuit 1a. The HEC operation circuit 1 receives the serial data stream and generates a multi-formula (X ⁸ + X
² + X + 1) to perform an input cancellation CRC remainder operation.
As a result of the calculation, six bits are output to the syndrome zero detection circuit 2 and two bits are output to the transmission bit comparison circuit 5 at the timing shown in FIG. The lower 6 bits of the syndrome are "0" in the syndrome zero detection circuit 2.
Is detected, it is determined that cell synchronization has been achieved,
The resulting synchronization signal is sent to the synchronization management circuit 4 as shown in FIG.
Is output at the timing of. The synchronization management circuit 4 determines whether the cell synchronization state is hunting, pre-synchronization,
And the synchronization establishment state.

When the cell synchronization state becomes the pre-synchronization state, the transmission bit collation circuit 5 is enabled by the output of the synchronization management circuit 4. The transmission bit collation circuit 5 transmits the transmission source PRBS transmission bits (Ut _-211 and Ut _-211 ) extracted by the syndrome generation matrix circuit 1e at the timing shown in FIG.
_{t + 1} ) and the predicted value (F) (V _t−211 and V _{t + 1} ) of the local PRBS on the receiving side generated by the cyclic local PRBS generating circuit 7 are added by modulo 2. If synchronization is not established, a mismatch detection signal between the transmission-side PRBS transmission bit and the reception-side local PRBS predicted value is obtained as an addition result.
This addition result is output to the cyclic local PRBS every half cell cycle.
By applying a specified number of times to the feedback tap of the generation circuit 7, the transmission source PRBS and the reception local PRB are applied.
S can be synchronized. In the synchronized state, the source PR
The code phase between the BS and the local PRBS on the receiving side is shown in FIG.
And (F). Also, the transmission bit collation circuit 5 receives the local PRBS on the receiving side at the timing shown in FIG.
(V _t−211 and V _{t + 1} ) are extracted and the upper 2 bits of the syndrome in the cell synchronization established state (equivalent to HEC7 and HEC8)
Do a descrambling.

[0007]

However, the upper two syndromes descrambled at the timing shown in FIG.
The timing of determining the syndrome of the bit is as shown in FIG. 4G, which is shifted from the timing of detecting the coincidence of the 6-bit syndrome in the timing of FIG. 4D. Therefore, syndrome match detection of all 8 bits cannot be performed. Therefore, an error correction operation requiring all 8-bit syndromes at the same timing cannot be performed normally. The present invention has been made in view of such circumstances, and it is an object of the present invention to provide an ATMHEC synchronous circuit that can perform an error correction operation normally.

[0008]

In order to solve the above-mentioned problems, the ATMHEC synchronous circuit according to the first aspect of the present invention provides an ATM HEC synchronous circuit.
An HEC operation circuit that performs a CRC operation on a header length of 40 bits for each bit of received cell data for detecting synchronization, and verifies the lower 6 bits of the operation result to verify whether the syndrome is "0" And a synchronization management circuit for monitoring a cell synchronization state, and a cell time slot (cell T) synchronized with the verification result.
S) for generating a cell TS, a timing generation circuit for generating timing for extracting a transmission bit, and a transmission bit for comparing a transmission source PRBS transmission bit with a reception local PRBS prediction value to detect a mismatch. A matching circuit, a cyclic local PRBS generating circuit for generating a receiving-side local PRBS for descrambling the scrambled received cell data, and matching the phases of the output code of the cyclic descramble circuit and the received cell data. Adjustment circuit and recursive local PRB
Local PRB for monitoring the synchronization status of the S generator
S state management circuit (confidence counter), error correction circuit for displaying 1-bit error correction of cell header portion and error detection of 2 or more bits, descrambling circuit for descrambling received cell data, and reception syndrome And a syndrome combining circuit for combining the upper two bits of the descrambled syndrome with the lower six bits of the syndrome.

Further, the ATMHEC synchronous circuit according to the second aspect does not include a syndrome delay circuit for adjusting the output of the reception syndrome and the operation timing of the error correction circuit according to the first aspect. Instead, HEC
A bit extraction circuit for extracting the upper 2 bits of the HEC code from a matrix for performing a CRC operation on a header length of 40 bits for each 1 bit of received cell data for detecting synchronization, and all 8 bits or lower 6 bits of the operation result And a syndrome coupling circuit that outputs the result to a syndrome zero detection circuit.

[0010]

According to the ATMHEC synchronizing circuit configured as described above, all the 8-bit syndromes have the same timing, and the error correction operation can be performed normally.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of the first embodiment, and FIG. 4 is a time chart of each point in the block diagram.
The HEC operation circuit 1 generates a generator formula (X ⁸ + X ² + X +
CRC operation circuit (X ⁸ + X ² + X + 1 remainder operation circuit) 1a for performing input cancellation type CRC remainder operation in 1), 32-bit delay circuit 1b, input data reproduction circuit 1c, 8-bit delay circuit 1d, and 40 bits before A matrix circuit 1e is provided for canceling the input data, newly inputting 1 bit, and generating a syndrome of a CRC operation result every clock. The HEC operation circuit 1 receives the serial data stream, and outputs a syndrome generated as an HEC operation result for the input data stream to the next stage.

(HEC Synchronous Operation) In the HEC synchronous operation, the syndrome zero detection circuit 2 detects whether the syndrome output from the HEC arithmetic circuit 1 has become zero (divisible) (synchronization pattern detection), and has detected zero. It is determined that synchronization has been achieved at this point. Once it is determined that synchronization has been achieved, the synchronization management circuit 4 that manages the synchronization state assumes that the cell synchronization state has transitioned from the hunting state to the previous synchronization state. In the pre-synchronization state, the cell TS generation circuit 3 that generates one cell length (424 bits) is activated from the first detection of the syndrome zero in the hunting state, and the count result is given to the synchronization management circuit 4. In the synchronization management circuit 4, the syndrome zero detection circuit 2
From the output result and the cell TS generation circuit, it is verified whether zero can be detected again at a signal position one cell length after the position where zero was previously detected. When a syndrome zero is detected β times consecutively at one cell interval, the synchronization state is managed as having transitioned from the previous synchronization state to the synchronization established state. Conversely, when the syndrome zero is not detected continuously α times at one cell interval from the synchronization established state, the synchronization management circuit 4 determines that the synchronization has been lost and returns the synchronization state to the hunting state.

The cell synchronization establishing operation differs depending on the synchronization state of the cyclic local PRBS generating circuit 7 described below. When the synchronization state of the cyclic local PRBS generating circuit 7 is in a state other than the synchronization stable state, the synchronization establishment operation is performed with the lower 6 bits out of all 8 bits of the HEC code. In the synchronization stable state, the synchronization establishing operation is performed with all 8 bits. The 6-bit and 8-bit switching is performed by the local PRBS state management circuit 8.
Is performed by the syndrome combining circuit 11 based on the output of

(Synchronous Operation of Recursive Local PRBS Generation Circuit 7) When the HEC synchronization state becomes the pre-synchronization state or later, the HEC arithmetic circuit 1 changes the upper 2 bits (7, 8 bits) of the HEC code from the received HEC code. Is extracted. 8 bits and 7 bits of the extracted HEC code are the source P
It is scrambled by Rt Ut _-211 and _{Ut + 1} .
The synchronous operation of the recursive local PRBS generation circuit 7 is based on the transmission sample bits (U _t−211 and U _{t + 1} ) of the transmission source PRBS and the predicted values (V _t−211 and V _{t− 2} ) of the reception local PRBS transmission sample bits. _{t + 1} ) and modulo addition,
It is connected to a transmission bit matching circuit 5 for comparison and matching. The addition result of the transmission bit collation circuit 5 is applied to the feedforward tap of the cyclic local PRBS generation circuit 7 at the timing of the half cell cycle generated from the cell counter value in the cell synchronization timing generation circuit 6. Will be

The synchronization state of the cyclic local PRBS generation circuit 7 is managed by the local PRBS state management circuit 8 based on the number of times the addition result from the transmission bit collation circuit 5 is applied. The comparison result of the transmission source source PRBS transmission sample bits and the reception side local PRBS transmission sample bits for 31 bits of the transmission sample bits without error in the 6 bits of the HEC is applied to the feedforward tap of the cyclic local PRBS generation circuit 7. After that, it is managed that the cyclic local PRBS generation circuit 7 has transitioned to the synchronization verification state. In the synchronous verification state, verification is performed by confirming that the predicted values of the transmission-side source PRBS transmission sample bits and the reception-side local PRBS transmission sample bits continuously match. In this state, since the transmission sample bits of the transmitting source PRBS and the predicted value of the cyclic local PRBS generating circuit 7 already match, the generated code sequence of the cyclic local PRBS generating circuit 7 changes the signal sequence according to the comparison result. Not done.

In the verifying state, 16 consecutive transmission source PRBS transmission sample bits and the reception local PRBS are transmitted.
When the coincidence of the transmitted sample bits is detected, the cyclic local PRBS generating circuit 7 shifts to the synchronous stable state. When the cyclic local PRBS generation circuit 7 is in the stable synchronization state, the upper two bits of the HEC code (HEC8, HEC7)
Are descrambled by the receiving local PRBS synchronized with the transmitting source PRBS in the transmission bit matching circuit 5. Further, the upper 2 bits of the HEC code and the lower 6 bits of the HEC code are combined by the syndrome combining circuit 11 and used as an 8-bit HEC code in the error correction circuit 9 which performs error detection and error correction of 2 or more bits of the header. .

However, as shown in FIGS. 4D and 4E, there is a 4-byte shift between the output timing of the lower 6 bits of the HEC (synchronization establishment timing) from the syndrome matrix and the timing of the upper 2 bits of the syndrome confirmation. This causes a problem that the syndrome connection is not performed normally. In order to solve this, the syndrome delay circuit 10 delays the upper 6 bits of the HEC code by 4 bytes, and the syndrome coupling circuit 11 adjusts the timing of all 8 bits of the HEC code and inputs the same to the error correction circuit 9 to input the HEC code.
In the synchronous stable state, error correction is performed using all 8 bits of the HEC code.

Since the cyclic local PRBS generating circuit 7 descrambles the received cell data in a stable state of synchronization, the transmission side source P due to the passage through the error correction circuit 9 or the like.
Correct the code position of the RBS and the receiving side local PRBS. For this purpose, a phase adjustment delay circuit 12 is connected to the output of the cyclic local PRBS generation circuit 7. The received cell data output from the error correction circuit 9 includes a descrambling circuit 13 for descrambling the scrambled received cell data. The descrambled received cell data is output to the next stage as output data of the ATMHEC synchronization circuit.

[Second Embodiment] FIG. 2 is a block diagram of a second embodiment. In the first embodiment, at the 6-bit synchronization pattern detection timing, H
The circuit has been realized by a method of extracting the upper two bits (7 and 8 bits) of the EC code. In the second embodiment, the upper two bits of the HEC code are extracted from the middle of the syndrome generation matrix circuit 1e by providing the bit extraction circuit 1f. That is, the extraction timing is extracted from 4 bits before the synchronization pattern detection timing, and the cyclic local PRBS generation circuit 7 performs the synchronization operation. After the recursive local PRBS generating circuit 7 is in the stable synchronization state, the transmission bit collating circuit 5 descrambles the extracted upper two bits (HEC8, 7), and a syndrome zero detecting circuit for detecting cell synchronization. 2, and the error correction circuit 9.

In the first embodiment, the lower 6 bits of the syndrome from the HEC operation circuit 1 are adjusted in timing by the syndrome delay circuit 10 and then combined with the upper 2 bits of the descrambled syndrome from the transmission bit comparison circuit. Then, an 8-bit syndrome was formed and output to the error correction circuit 9. On the other hand, in the second embodiment, the upper two bits of the descrambled syndrome are output from the transmission bit comparison circuit 5 at a timing coincident with the lower six bits of the syndrome from the HEC operation circuit 1. Therefore, the syndrome delay circuit 10 required in the first embodiment becomes unnecessary. All the 8-bit syndromes are combined by the syndrome combining circuit 11 and input to the error correction circuit 9.

[0021]

As described above, the ATMHE of the present invention is used.
According to the first aspect of the C synchronous circuit, the syndrome delay circuit 10 for adjusting the output of the reception syndrome and the operation timing of the error correction circuit 9 and the upper two bits of the descrambled syndrome are combined with the lower six bits of the syndrome. And a syndrome coupling circuit 11. According to the second aspect, a bit extraction circuit 1f for extracting the upper 2 bits of the HEC code from the matrix for performing the CRC operation, and verifying by switching all the 8 bits or the lower 6 bits of the operation result, and And a syndrome coupling circuit 11 for outputting to the detection circuit 2. for that reason,
An error correction operation requiring all 8-bit syndromes at the same timing can be performed normally.

[Brief description of the drawings]

FIG. 1 shows a configuration diagram of a first embodiment of the present invention.

FIG. 2 shows a configuration diagram of a second embodiment of the present invention.

FIG. 3 shows a configuration diagram of a conventional example.

FIG. 4 shows a time chart of each point in the configuration diagram.

FIG. 5 shows a cell synchronization probability state transition diagram.

[Explanation of symbols]

1 HEC arithmetic circuit, 2 syndrome zero detection circuit, 3
... Cell TS generation circuit, 4 ... Synchronization management circuit, 5 ... Transmission bit verification circuit, 6 ... Timing generation circuit, 7 ... Circulating local PRBS generation circuit, 8 ... Local PRBS state management circuit, 9 ... Error correction circuit, 10 ... Syndrome delay circuit, 11: syndrome coupling circuit, 12: phase adjustment circuit, 13: descrambling circuit, 1f: bit extraction circuit.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-311121 (JP, A) JP-A-4-334234 (JP, A) JP-A-4-180432 (JP, A) JP-A-6-180432 164624 (JP, A) JP-A-6-164630 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56 H04L 7/00 H04L 7/08

Claims (2)

(57) [Claims] 1. An HEC operation circuit (1) for performing a CRC operation on received cell data (A) for detecting HEC synchronization, and a lower 6 bits of an operation result (B) of the HEC operation circuit.
A syndrome zero detection circuit (2) for verifying whether or not the syndrome is "0" by verifying a bit, and a synchronization management circuit (4) for monitoring a cell synchronization state using the verification result of the syndrome zero detection circuit A cell TS generating circuit (3) for generating a cell time slot synchronized with the verification result;
A timing generation circuit (6) for generating a timing (C) for extracting a transmission source PRBS transmission bit in the cell;
And the transmission source PRBS transmission bit and the reception local PRB at the timing generated by the timing generation circuit.
A transmission bit collating circuit (5) for comparing the S prediction value and detecting a mismatch, and a receiving side local PRBS (S) for synchronizing with the mismatch signal of the transmission bit collating circuit and descrambling the scrambled received cell data. F) and a local PRBS state for monitoring the synchronization state of the cyclic local PRBS generation circuit by combining a mismatch signal of the transmission bit collation circuit and a verification signal whose syndrome is "0". A management circuit (8), an error correction circuit (9) for displaying one-bit error correction or error detection of two or more bits in a cell header portion of the received cell data reproduced by the HEC operation circuit, and an output of the error correction circuit. A descrambling circuit (13) for descrambling received cell data;
A phase adjustment circuit (12) for adjusting the phase of the BS to the phase of the received cell data output from the error correction circuit;
A syndrome delay circuit (10) for adjusting the timing of the output of the received syndrome from the HEC arithmetic circuit, the upper 2 bits of the descrambled syndrome output from the transmission bit comparison circuit, and the lower 6 bits of the syndrome adjusted for timing An ATMHEC synchronization circuit including a syndrome coupling circuit (11). 2. An HEC operation circuit (1) for performing a CRC operation on received cell data (A) for detecting HEC synchronization, and a lower 6 bits of an operation result (B) of the HEC operation circuit.
A syndrome zero detection circuit (2) for verifying whether or not the syndrome is "0" by verifying a bit, and a synchronization management circuit (4) for monitoring a cell synchronization state using the verification result of the syndrome zero detection circuit A cell TS generating circuit (3) for generating a cell time slot synchronized with the verification result;
A timing generation circuit (6) for generating a timing (C) for extracting a transmission source PRBS transmission bit in the cell;
And the transmission source PRBS transmission bit and the reception local PRB at the timing generated by the timing generation circuit.
A transmission bit collating circuit (5) for comparing S prediction values to detect non-coincidence, and a receiving side local PRBS (S) for synchronizing with the non-coincidence signal of the transmission bit collating circuit to descramble scrambled received cell data F) and a local PRBS state for monitoring the synchronization state of the cyclic local PRBS generation circuit by combining a mismatch signal of the transmission bit collation circuit and a verification signal whose syndrome is "0". A management circuit (8), an error correction circuit (9) for displaying one-bit error correction or error detection of two or more bits in a cell header portion of the received cell data reproduced by the HEC operation circuit, and an output from the error correction circuit. A descrambling circuit (13) for descrambling received cell data;
A phase adjustment circuit (12) for adjusting the phase of the RBS to the phase of the received cell data output from the error correction circuit (12)
And a bit extraction circuit (1f) for extracting the upper 2 bits of the HEC code from the matrix for performing the CRC operation of the HEC operation circuit, and verifying the operation result by switching all 8 bits or lower 6 bits of the operation result. An ATMHEC synchronization circuit comprising a syndrome coupling circuit (11) for outputting to a zero detection circuit.