JP2874271B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Prior art] Insulating amorphous substrates such as glass and quartz, SiO ₂ , Si ₃ N ₄
Attempts have been made to form a high-performance semiconductor element on an insulating amorphous material such as an insulating amorphous layer.

In recent years, as the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, three-dimensional ICs, and the like has increased, the performance of semiconductor elements formed on insulating materials as described above has increased, It is essential to increase the area and reduce the cost.

In particular, in the case of large-sized liquid crystal display panels and the like, forming a thin film transistor (TFT) on an inexpensive glass substrate is becoming an essential requirement in order to satisfy the requirement of low cost. (Solid State Electronics Vol.32 (5) p.39
1 (1989), IEEE Electron Device Letters Vol.10
(3) p.123 (1989), IEEE Transactions on Electro
n Devices, Vol. 36 (3) p. 529 (1989)) To improve the performance of TFTs, poly-Si (polycrystalline silicon) was used rather than a-Si (amorphous silicon). Although it is more advantageous, a large number of dangling bonds are present at the crystal grain boundaries and the like, and serve as trap levels for carriers and act as barriers for carrier conduction. (JYWSeto, JA
ppl.Phys., 46, p5247 (1975)). Therefore, in order to improve the performance of the polycrystalline silicon thin film transistor, it is necessary to reduce the defects. (J. Appl. Phys., 53 (2),
p1193 (1982)). For this reason, the above-mentioned defects are terminated with hydrogen. As such a hydrogenation method, a hydrogen plasma treatment method, a hydrogen ion implantation method, a method of diffusing hydrogen from a plasma nitride film, and the like are known. ing.

[Problems to be Solved by the Invention] However, the conventional hydrogenation method has the following disadvantages. (1) The hydrogen ion implantation method has a drawback that an expensive apparatus called an ion implantation apparatus is required, and it is difficult to implant hydrogen into a polycrystalline silicon layer of about several hundreds of square meters with good controllability. (2) In the method of diffusing hydrogen from a plasma nitride film, there is a drawback that characteristics are not sufficiently improved as compared with the hydrogen plasma treatment due to insufficient supply of hydrogen. (3) In the hydrogen plasma processing method,
Although it is excellent in terms of improvement in characteristics, it has disadvantages such as a frequent occurrence of defects such as gate breakdown voltage failure and threshold voltage (Vth) shift due to plasma damage.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which solves the above-mentioned problem while securing the effect of improving TFT characteristics by hydrogenation.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention has the following features.

The method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a gate electrode, a gate insulating film, a non-single-crystal silicon layer serving as a channel region, and a non-single-crystal semiconductor layer doped with impurities serving as source / drain regions on a substrate. Are formed in this order, and a heat treatment is performed by forming a cap layer on the non-single-crystal semiconductor layer to prevent diffusion of hydrogen, so that the non-single-crystal silicon layer is formed by hydrogen released from the non-single-crystal semiconductor layer. Is characterized by performing hydrogenation.

Embodiment An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a manufacturing process diagram of a semiconductor device according to the present invention.

FIG. 1A shows an insulating amorphous substrate such as glass or quartz, an insulating amorphous material layer such as SiO ₂ or Si ₃ N ₄ , or a sapphire substrate (Al ₂ O ₃ ) or MgO. Al ₂ O ₃ , B
This is a step of forming a gate electrode 102 on an insulating material 101 such as an insulating crystal substrate such as P or CaF ₂ . Specifically, (1) the a-Si layer doped with impurities such as boron is removed by a method such as a plasma CVD method, an ECR-PCVD method, a sputtering method, or a Si ion implantation method into a polycrystalline Si thin film. 3000 ~
There is a method of forming 7000 ° and polycrystallizing by a solid phase growth method or a laser annealing method, and (2) a method of forming a high melting point metal such as Mo, Cr, and Ta by a sputtering method or the like. In this embodiment, a case where an a-Si layer formed by a plasma CVD method is polycrystallized by a solid phase growth method will be described as an example. The plasma CVD method uses SiH ₄ and H ₂ gases as the deposition gas, and B ₂ H _{6 as the} doping gas.
Gas was used. Substrate temperature is 150 ~ 250 ℃, internal pressure is 0.8Torr
A 13.56 MHz rf power source was used. The flow ratio of B ₂ H ₆ and SiH ₄ was set so that [B ₂ H ₆ ] / [SiH ₄ ] = about 3 × 10 ^{−3 to} 5 × 10 ⁻² . The concentration of boron contained in the formed a-Si layer substantially corresponds to the above-mentioned gas mixture ratio. Subsequently, the a-Si layer is solid-phase grown and patterned in the shape of the gate electrode 102. The solid phase growth may be performed after the pattern formation. Next, the annealing conditions for solid phase growth will be described. First, hydrogen contained in the a-Si layer is desorbed by pre-annealing at 450 ° C. in a 30 min. N ₂ atmosphere. this is,
When the solid phase growth annealing is performed while hydrogen is contained in a-Si, the portion from which hydrogen has escaped becomes a hole, and the purpose is to prevent a porous film from being formed. In the case of using the plasma CVD method, if dilution is performed using He gas as a film forming gas, a
-It is more desirable because there is an advantage that the amount of hydrogen taken into the Si layer can be reduced. Thereafter, the process proceeds to a solid phase growth annealing step. ₂ gas annealing conditions are N, 550 to 650
It is about 4 to 72 hours at a temperature of ° C. By this solid phase growth annealing, the a-Si layer is polycrystallized and the Si in the gate electrode is
The average grain size is up to about 1 to 3 μm, and many grains having a grain size of 5 μm or more appear. Annealing is N ₂
Not limited to annealing, laser beam annealing,
Halogen lamp annealing may be used. At the time of this annealing step, boron atoms mixed during the formation of the a-Si layer are also activated at the same time. As a result, the resistivity of the polycrystalline silicon gate electrode (p + poly-Si) 106 is 1-3 × 10 ⁻³ Ω · cm.
The resistivity of an n-type doped gate electrode using polycrystalline Si formed by ordinary LPCVD and having an average particle diameter of 3000 ° or less and containing no crystal grains having a particle diameter of 1 μm or more is 2.5 × 10 ⁻³ Ω · cm.
, Almost the same efficiency can be obtained. The solid growth annealing of the gate electrode can be performed in a solid phase growth annealing step of the channel region and the source / drain region performed in the step shown in FIG. That is, it is also possible to perform the process up to the pattern formation of the gate electrode and to perform the solid phase growth in the step (c), thereby shortening the process.

FIG. 1B shows a gate insulating film 103 formed by a plasma CVD method, an ECR-PCVD method, a CVD method, a sputtering method, or the like.
This is a step of forming a SiO ₂ layer of about 300 to 2000 °. When polycrystalline silicon is used for the gate electrode,
There is also a method of oxidizing the polycrystalline silicon by a thermal oxidation method to form an SiO ₂ layer. Also, as the gate insulating film, SiO ₂
In addition, Si _1-x O _x (0 <x <1), Si _1-x N _x (0 <x <
1), an insulating film such as Si _1-xy O _x Ny (0 <x <1, 0 <y <1) may be used. Plasma CVD of Si _1-x N _x (0 <x <1)
In the case of forming by the method, for example, Si is used as a film forming gas.
H _4, NH _3, using N _2, keeping the substrate temperature at about 300 ° C. to 400 ° C., by decomposing the gas to apply the rf power Si _1-x N
_x (0 <x <1) layers can be formed.

FIG. 1C shows that a non-single-crystal silicon layer 104 such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon forming a channel region is
In this step, the non-single-crystal silicon layer is crystal-grown by heat treatment or the like to form a polycrystal.

As a method for forming the non-single-crystal silicon layer, there is a method described below.

(1) A polycrystalline silicon thin film is deposited at about 580 ° C. to 650 ° C. by a low pressure CVD method.

(2) After depositing an amorphous silicon thin film by EB (Electron Beam) evaporation method, sputtering method, plasma CVD method, etc.
A solid phase growth anneal (some methods such as a laser anneal method to polycrystallize in a short time) is performed at about 0 ° C. for about 2 to 70 hours to form a polycrystalline silicon thin film having a large grain size of 1 to 2 μm or more. Form.

(3) After depositing a polycrystalline silicon thin film by a low-pressure CVD method or the like, implanting Si or the like by an ion implantation method to amorphize the polycrystalline silicon thin film, and then perform solid phase growth annealing at about 550 ° C. to 650 ° C. (There is also a method of polycrystallizing in a short time by a laser annealing method or the like) to form a large-diameter polycrystalline silicon thin film having a particle diameter of about 1 to 2 μm.

Note that when polycrystalline silicon is formed by the above-described method, the crystallinity is close to 100%, literally polycrystalline silicon, and the polycrystalline silicon has a crystallinity of about 50% to about 90%. There are cases. In this case, the latter may be more appropriate to be called microcrystalline silicon than polycrystalline silicon, but in this patent, unless otherwise specified,
Both of them will be referred to as polycrystalline silicon. Also,
As the non-single-crystal silicon thin film, microcrystalline silicon or amorphous silicon thin film may be used in addition to the above-described polycrystalline silicon thin film.

An example of the film forming conditions is described below. The substrate temperature is maintained at about room temperature to about 600 ° C. by plasma CVD, and monosilane or a gas obtained by diluting monosilane with hydrogen, argon, helium, or the like is introduced into the reaction chamber, and high-frequency energy is applied to decompose the gas to obtain a desired substrate. A silicon layer on top is 100 mm thick
Formed about 2000 mm. In addition, the gate insulating film is plasma CV
In the case of forming by the D method, the gate insulating film and the amorphous silicon layer can be continuously formed without breaking the vacuum in exactly the same manner as in the manufacturing process of the a-Si TFT, and the interface state between the gate insulating film and the silicon layer can be formed. This has the effect of reducing the noise and improving the reproducibility.

Subsequently, the non-single-crystal silicon layer 104 is polycrystallized by crystal growth by heat treatment or the like. The optimum conditions for the heat treatment differ depending on the method of forming the non-single-crystal silicon layer. Taking a case where the film is formed by the plasma CVD method as an example, there are the following differences depending on the substrate temperature during the film formation.

(1) A film formed by plasma CVD at a relatively low substrate temperature of about room temperature to about 150 ° C becomes amorphous silicon containing a large amount of hydrogen in the film, but is formed at about 200 to 300 ° C. Hydrogen in the film can be removed by a heat treatment at a lower temperature than that of the formed film. An example of the heat treatment condition is described below. After the film is formed by the plasma CVD method, the amorphous silicon film is annealed before breaking the vacuum. Since an amorphous silicon film having a low film formation temperature is a porous film, if the film is taken out to the atmosphere as it is after film formation, oxygen and the like are easily taken into the film, which causes a deterioration in film quality. When a proper heat treatment is performed, the film is not densified, and the incorporation of oxygen and the like is prevented. The heat treatment temperature is
300 ° C. or higher is desirable, and increasing the temperature to about 400 to 500 ° C. is particularly effective. Even if the heat treatment temperature is lower than 300 ° C., there is an effect of densification of the film by the heat treatment. However,
When annealing is performed continuously without breaking the vacuum, the annealing can be omitted.

Subsequently, the amorphous silicon film is solid-phase grown by heat treatment or the like. When a relatively low-temperature heat treatment at about 550 ° C. to 650 ° C. is performed for several hours to about 20 hours, desorption of hydrogen and crystal growth occur in an amorphous silicon film formed at a low film formation temperature, and a crystal grain size of 1 Polycrystalline silicon containing crystal grains having a large grain size of about 2 μm or more is formed. In addition, it is not preferable that both the annealing for densification and the annealing during solid phase growth rapidly increase the temperature in a short time when the temperature is increased to a predetermined annealing temperature. The reason is that as the temperature is increased (especially when the temperature exceeds 300 ° C.), hydrogen in the film is desorbed, and when the rate of temperature rise is rapid, defects are easily formed in the film. In some cases, pinholes are formed or the film is peeled off. 20 at least at temperatures above 300 ° C
When the temperature is gradually increased at a temperature rising rate lower than 5 ° C./min (a temperature rising rate lower than 5 ° C./min is particularly desirable), the number of defects in the film decreases.

(2) A film formed at a substrate temperature of about 150 ° C. to 300 ° C. by a plasma CVD method has a smaller amount of hydrogen in the film but has a smaller amount of hydrogen than an amorphous silicon film formed at a low temperature. The release temperature shifts to higher temperatures. However, since the film after film formation is denser than a film formed at a low temperature, arnyl for the above-described densification can be omitted. Solid phase growth conditions are as follows: When heat treatment at about 550 ° C. to 650 ° C. is performed for several hours to about 40 hours, desorption of hydrogen and crystal growth occur, and the crystal grain size is 1 to 2 hours.
Polycrystalline silicon containing crystal grains having a large grain size of about μm is formed. The method of raising the temperature from 550 ° C. to 650 ° C. is similar to the case of (1), in that at least at a temperature of 300 ° C. or more, the temperature is raised at a rate of 20 ° C./min (preferably 5 ° C./min). Is desirably gradually increased to reduce defects in the film.
The substrate temperature is preferably between 150 ° C. and 200 ° C., the crystal grain size is relatively large, and it is difficult to cause peeling of the film that occurs when the temperature is raised to a predetermined solid phase growth temperature during solid phase growth, which is particularly preferable. .

(3) When the substrate temperature exceeds 300 ° C., the amount of hydrogen in the film further decreases, but the annealing at about 550 ° C. to 650 ° C. makes it difficult for hydrogen to be desorbed. Heat treatment may be important.

FIG. 1D shows a case where a non-single-crystal semiconductor layer 105 doped with impurities forming a source / drain region is formed, and a cap layer 106 for preventing diffusion of hydrogen is formed on the non-single-crystal semiconductor layer. This is a step of annealing at about 600 ° C. to polycrystallize the non-single-crystal layer and hydrogenate the non-single-crystal silicon layer in the channel region with hydrogen released from the non-single-crystal layer.

In the case of an n-channel TFT, an n-type semiconductor layer is formed, and in the case of a p-channel TFT, a p-type semiconductor layer is formed. In this embodiment, a-S doped with an impurity formed by a plasma CVD method is used.
The case where the i-layer is polycrystallized by the solid phase growth method will be described as an example. As a film forming gas of the plasma CVD method, SiH ₄ and H ₂ gases were used, and as a doping gas, a B ₂ H ₆ gas (p channel) or a PH ₃ gas (n channel) was used. Substrate temperature is 150
250250 ° C., the internal pressure was 0.8 Torr, and a 13.56 MHz rf power source was used. The flow ratio of B ₂ H ₆ , PH ₃ and SiH ₄ is [B ₂ H ₆ ] / [SiH ₄ ] =
3 × 10 ^{−3 to} 5 × 10 ⁻² , [PH ₃ ] / [SiH ₄ ] = 3 × 10 ⁻³ to
It was set to be about 5 × 10 ^-2 . In addition, the formed a
-The concentration of impurities contained in the Si layer substantially corresponds to the gas mixture ratio described above. 10% in amorphous silicon thin film
Contains about hydrogen.

Subsequently, a cap layer 106 is formed on the non-single-crystal semiconductor layer 105, and annealing for hydrogenation and polycrystallization is performed at a temperature of about 300 ° C. to 650 ° C. The annealing time is about 1 hour to 20 hours. The purpose of this annealing is to crystallize the non-single-crystal semiconductor layer by heat treatment and polycrystallize it, and at the same time, desorb and diffuse hydrogen contained in the film to hydrogenate the polycrystalline silicon forming the channel region. is there. By this annealing, atomic hydrogen is desorbed and diffused from the impurity-doped a-Si: H to form dangling bonds existing at the crystal grain boundaries of the polycrystalline silicon forming the channel region and at the interface with the gate insulating film. Terminate. In addition, cap layer
As 106, a material that hardly diffuses hydrogen generated from a-Si: H is desirable. For example, (1) a method of forming a metal thin film of Ti, Cr, Mo, Al or the like to a thickness of about 300 to 1 μm by a sputtering method, a vapor deposition method, or the like; (2) amorphous silicon nitride (a-SiN _x )
For example, there is a method of forming about 00Å to about 1 μm. In particular, Ti, C
When r, Mo, or the like is used for the cap layer, there is no need to remove the cap layer entirely after the hydrogenation annealing, and leave the cap layer on the source / drain region, and form a source / drain electrode and a source / drain region formed of Al or the like. Can be used as it is as a buffer layer for ensuring good contact. The material of the cap layer is not limited to the above-mentioned material, but is preferably a material in which hydrogen is less likely to diffuse (has a smaller diffusion coefficient) than amorphous silicon dioxide (SiO ₂ ).

Subsequently, annealing conditions for hydrogenation and polycrystallization will be described. First, a method for raising the temperature to a predetermined annealing temperature will be described. In the present invention, since a cap layer for preventing hydrogen diffusion is formed on amorphous silicon, if the annealing method is not optimized, peeling of the amorphous silicon layer due to rapid desorption of hydrogen and Problems such as generation of defects such as holes occur. Therefore, conditions for the hydrogenation annealing, particularly, a method of raising the temperature to a predetermined hydrogenation annealing temperature are important.
The sample is inserted into an annealing furnace maintained at a predetermined temperature, and heated to a predetermined hydrogenation annealing temperature at a predetermined heating rate,
When annealing at a predetermined hydrogenation temperature, the heating rate is 5
It is desirable that the temperature be lower than ° C./min because the generation of defects and the peeling of the film due to the desorption of hydrogen are suppressed. It is to be noted that the heating rate does not need to be always constant, and may be changed within the above range. The annealing temperature has an optimum value between 300 ° C and 650 ° C. For polycrystallization, high-temperature annealing at about 550 ° C to 650 ° C is necessary, but at annealing temperatures above 450 ° C, desorption of hydrogen from amorphous silicon and diffusion of desorbed hydrogen Occurs efficiently, but the efficiency of hydrogen addition to dangling bonds in polycrystalline silicon decreases (because hydrogen addition and desorption occur simultaneously). Therefore,
Once the temperature is raised to about 550 ° C to 650 ° C, annealing is performed for about 20 minutes to 1 hour to promote polycrystallization and desorption and diffusion of hydrogen. An annealing method of performing annealing for promoting the addition of hydrogen to defects such as dangling bonds for about 30 minutes to 2 hours is extremely effective.

As a non-single-crystal silicon layer doped with impurities,
A method of forming microcrystalline silicon instead of amorphous silicon by a plasma CVD method or the like is also effective. When microcrystalline silicon is formed by plasma CVD, it can be easily formed by increasing the substrate temperature to about 350 ° C. to 400 ° C., lowering the SiH ₄ / H ₂ flow rate ratio, and increasing the rf power. In the case where microcrystalline silicon is used for the semiconductor layer, even if it is not polycrystallized, the resistivity is sufficiently low.
It is also possible to omit annealing at a high temperature of about ° C. Therefore, sufficient hydrogenation can be achieved only by performing annealing at about 300 ° C. to 450 ° C. for about 30 minutes to 2 hours.

FIG. 1 (e) shows a non-single-crystal silicon layer 104 forming a channel region, a non-single-crystal silicon layer 105 forming a source / drain region, and a cap layer 106 formed of Ti, Mo, Cr or the like.
Is etched into a predetermined pattern. Subsequently, a conductive film (Al, Cr, ITO, etc.) of a wiring material is formed to a thickness of about 1000 to 1 μm by a sputtering method or the like, and a source electrode 110 and a drain electrode 109 are formed. This is a step of patterning the layer 106 and the non-single-crystal layer 105 to form the source region 108 and the drain region 107.

FIG. 1F shows a step of forming the passivation layer 111 by a CVD method, a plasma CVD method, a sputtering method, or the like. The passivation layer may be a silicon oxide film or the like in addition to the silicon nitride film. In addition, inorganic SOG such as silicate
(Spin-on-glass) or organic SOG such as silicone may be used. In particular, an organic SOG such as silicone generates a small amount of stress due to heat treatment after coating, and can form a high-quality passivation layer having no defects such as cracks over a large area.

The field-effect mobility of the poly-Si TFT formed by the manufacturing method shown in FIG. 1 is 80 to 100 cm ² / V · s (N channel),
~ 40cm ² / V · s (P channel)
FT could be formed on a glass substrate at low temperature.

Next, the problem of threshold voltage control accompanying hydrogenation will be described. When polycrystalline silicon TFT is hydrogenated, Nth transistor shifts Vth in depletion direction,
Although the P-channel transistor shifts in the enhancement direction, Vth can be controlled by doping the channel region with an impurity of about 10 ¹⁵ to 10 ¹⁹ / cm ³ . For example, in FIG. 1, (1) a method of implanting impurities such as B (boron) at a dose of about 10 ¹¹ to 10 ¹³ / cm ^{2 by} ion implantation or the like.

(2) A method of doping an impurity of about 10 ¹⁵ to 10 ¹⁹ / cm ³ when forming a non-single-crystal silicon layer forming a channel region.
(Taking a case where a film is formed by a plasma CVD method as an example, the film can be easily formed by using SiH4, H2, B2H6, or the like as a film forming gas). In particular, when the dose is about the above-described value, Vth can be controlled such that the off-state current of both the P-channel transistor and the N-channel transistor is minimized. Therefore, even when a CMOS type TFT element is formed, the entire surface can be channel-doped in the same step without selectively channel-doping Pch and Nch. Also, as described above, instead of using N ⁺ poly-Si by a conventional thermal diffusion method as a gate electrode, by using P ⁺ poly-Si formed by a solid phase growth method or the like, channel doping is not performed. Alternatively, Vth can be controlled.

Next, the reason why the failure due to the plasma damage frequently generated in the conventional hydrogen plasma processing does not occur at all in the hydrogenation of the present invention will be described.

Although the cause of the damage generated by the hydrogen plasma treatment is not clear at present, charge-up occurs due to immersion in a plasma atmosphere, and a voltage is applied to the gate film. In addition, a relatively high substrate temperature of about 300 ° C. applies a kind of BT (Bias-Temperature) stress, and the hydrogen plasma time is as long as about 1 to 2 hours. Is explained well.

On the other hand, in the hydrogenation method of the present invention, amorphous silicon is formed by a plasma CVD method, and hydrogenation is performed using hydrogen atoms released from the amorphous silicon by annealing. Therefore, if the BT stress as described above is not applied during the formation of the amorphous silicon, no damage occurs.
Actually, the BT stress as described above was hardly applied only by forming the amorphous silicon film by the plasma CVD method, and the TFT formed by the present invention was able to eliminate defects caused by damage. The following two points can be considered as the reason.

(1) In hydrogen plasma treatment and amorphous silicon film formation,
Since the high-frequency power is different by about one digit (hydrogen plasma processing with electrode size of 20 cm diameter: 100 to 200 W, amorphous silicon film formation: 10 to 20 W), charge-up is less likely to occur as compared with hydrogen plasma processing.

(2) In the hydrogen plasma treatment, it is necessary to diffuse hydrogen atoms to the polycrystalline silicon layer by thermal diffusion while decomposing hydrogen gas and supplying atomic hydrogen. Therefore, unless the substrate temperature is maintained at a high temperature of about 250 ° C. to 350 ° C., the effect of hydrogenation is drastically reduced. On the other hand, in the present invention, the supply of atomic hydrogen and the hydrogenation by thermal diffusion thereof are performed not in the amorphous silicon film formation but in a separate annealing step. The substrate temperature can be lowered. In addition, since hydrogen is easily desorbed at a low temperature when the substrate temperature is lowered (for example, 200 ° C. or lower), it is preferable in the present invention to lower the film formation temperature of amorphous silicon. Therefore, in the present invention, BT stress is further reduced.

As described above, by applying the present invention, a thin-film transistor having a large ON current, a small OFF current, a steep rise of a sub-threshold region, and excellent reliability can be manufactured without any defects such as plasma damage. It becomes possible. Further, according to the present invention, there is a great advantage that hydrogenation of a large-area substrate is easy and mass productivity is improved.

As an application of the present invention, for example, a liquid crystal display panel configured by TFT using non-single-crystal silicon as an element material,
A contact-type image sensor, a thermal head with a built-in driver, an optical writing element and a display element with a built-in driver using an organic EL as a light emitting element, a three-dimensional IC, and the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Further, as described in the embodiment, by applying the present invention to a low-temperature process of about 600 ° C. or less, a large-area, high-performance semiconductor device using inexpensive glass as a substrate can be realized.

Furthermore, at least a non-single-crystal silicon layer forming a channel region with a gate insulating film is continuously formed without breaking a vacuum by a plasma CVD method or the like, solid-phase growth annealing is performed, and hydrogenation is performed by the method according to the present invention. A poly-Si TFT having a low / SiO ₂ interface state density (about 1 to 3 × 10 ¹¹ cm ⁻² ) can be formed with good reproducibility.

In addition, the present invention basically provides a high-performance poly-Si TFT by simply adding solid phase growth annealing to the a-Si TFT manufacturing process.
It has an extremely large feature that a TFT can be formed. Therefore, it has a great effect on the enlargement of the substrate (for example, 35 cm square or more) and the reduction of the manufacturing cost.
The poly-Si TFT can be formed by also using the above-mentioned line, and there is an advantage that there is no need for a huge new investment for establishing a new production line.

The present invention is not limited to the embodiment shown in FIG. 1, but is effective for all insulated gate field effect transistors in which at least a part of the channel region is polycrystalline. The present invention is also effective in a transistor in which at least a part of a channel region is microcrystalline or a transistor in which an amorphous semiconductor which is insufficiently hydrogenated and formed by a sputtering method, an evaporation method, or the like forms a part of a channel region. It is. In addition to the inverted stagger type TFT, a top gate type TFT
The present invention is also effective against the above. Further, the present invention is effective not only in a low-temperature process but also in, for example, a high-temperature process using a quartz substrate or a three-dimensional IC.

Further, even when the channel region is a single crystal, when an element is formed in a recrystallized or solid phase grown silicon layer, defects such as sub-grain boundaries are easily generated in the crystal. In that case, when the termination of the defect is performed in the method of manufacturing a semiconductor device according to the present invention, there is an effect of improving the characteristics.

Further, the present invention is also effective for reducing the defect density at the interface of a heterojunction such as HBT (hetero bipolar transistor). In particular, when at least one of the two semiconductor layers forming a heterojunction is formed of a non-single-crystal semiconductor, the plasma treatment according to the present invention can reduce defects in the film and at the interface at the same time.

In addition, the present invention can be widely applied to all semiconductor processes, including solar cells and optical sensors, bipolar transistors, and electrostatic induction transistors using a non-single-crystal semiconductor as an element material.

[Effects of the Invention] As described above, according to the present invention, the performance of an insulated gate field effect transistor in which at least a part of a channel region such as a poly-Si TFT is made of a non-single-crystal semiconductor is improved by plasma damage or the like. It can be realized by a simple manufacturing process without defects. Further, the present invention can be widely applied not only to the insulated gate field effect transistor but also to all semiconductor processes, and the effect is extremely large.

According to the present invention, a high-performance poly-Si TFT having a high field-effect mobility, a low interface state density, and a low-temperature process is provided.
Can be formed on a large area substrate (for example, 35 cm square) with good reproducibility.

Therefore, when the present invention is applied to a contact type image sensor in which a scanning circuit and a photoelectric conversion element are integrated on the same substrate, it is effective to increase the length of the contact type image sensor. Conventionally, a plurality of chips are connected in-line. For example, A3 can be formed by one chip. Furthermore, there is a great effect on increasing the reading speed, high resolution field, and high gradation.

Also, when the present invention is applied to a liquid crystal display panel, the area can be increased, the cost can be reduced, and the built-in driver and the high resolution can be realized with the improvement of the field effect mobility.

Also, by using polycrystalline silicon having a large crystal grain size for the gate wiring, the gate wiring resistance can be reduced,
This has a great effect on increasing the size of liquid crystal display panels and image sensors.

In addition, the present invention is also applicable to a TFT drive liquid crystal shutter array, a TFT drive thermal head, and the like. The present invention is effective not only for application to TFTs but also for applications to three-dimensional ICs and the like.

[Brief description of the drawings]

1 (a) to 1 (f) are manufacturing process diagrams of a semiconductor device according to the present invention. 101 insulating material 102 gate electrode 103 gate insulating film 104 non-single-crystal silicon layer 105 non-single-crystal silicon layer doped with impurities 106 cap layer 107 drain region 108 source Region 109 Drain electrode 110 Source electrode 111 Passivation layer

Claims (1)

(57) [Claims] A gate electrode, a gate insulating film,
A non-single-crystal silicon layer serving as a channel region and a source /
Forming a non-single-crystal semiconductor layer doped with an impurity to be a drain region in this order; forming a cap layer on the non-single-crystal semiconductor layer to prevent diffusion of hydrogen; A method for manufacturing a semiconductor device, comprising hydrogenating the non-single-crystal silicon layer with hydrogen released from a crystalline semiconductor layer.