JP2877183B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device,
In particular, the present invention relates to a charge transfer device that converts a signal charge amount into a potential change using a floating gate.

[0002]

2. Description of the Related Art A so-called FGA (Floating Gate Amplifier) for detecting a signal charge amount by a floating gate.
The charge transfer device employing the r) method has a feature that a signal can be detected nondestructively and with low noise. When the charge transfer device is used for a solid-state imaging device, there is a growing demand for higher sensitivity of the charge detection unit due to the recent tendency to increase the number of pixels and miniaturization.

FIG. 2A is a plan view showing a configuration of an output section of a conventional charge transfer device, and FIG.
It is sectional drawing which follows the A 'line. This conventional example relates to a charge transfer device of a buried channel type two-phase drive system.
In FIG. 2, reference numeral 1 denotes a charge transfer unit, and 2 denotes a charge detection unit. As shown in FIG. 1, first layer transfer electrodes 6, 8, 10 and second layer, which are insulated and separated from each other via an insulating film 5, are formed on the surface of an n-type impurity layer 4 formed on a p-type silicon substrate 3. Transfer electrodes 7, 9, a first output gate 11, a second output gate 12, a floating gate 13, and a reset gate 14 are formed.

[0004] directly below the second layer transfer electrodes 7 and 9 of the surface of the n-type impurity layer 4 of the charge transfer section 1, a potential barrier to realizing the charge transfer due to the two-phase clock pulse n ^- -type impurity A region 15 is formed. In the charge transfer unit 1,
Adjacent first-layer transfer electrodes and second-layer transfer electrodes are paired, and clocks φ ₁ and φ ₂ having opposite phases are alternately applied to control the depth of the potential well below the transfer electrodes, thereby forming a signal. The electric charges are transferred to the electric charge detection unit 2.

The charge detection unit 2 includes a first output gate 11 fixed to the potential V ₁ adjacent to the last stage of the charge transfer unit 1;
A second output gate 12 fixed to the potential V ₂ is provided, and a floating gate 13 for converting the transferred signal charges into a voltage at the subsequent stage and a potential under the floating gate are periodically reset to a reset potential. Reset gate 14 is provided. Further, an n ⁺ -type impurity layer 16 fixed to a fixed reset potential V ₃ is provided adjacent to the reset gate at the end of the n-type impurity layer 4 serving as a charge transfer region. An output transistor 17 for outputting the potential change of this electrode to the outside is connected to the floating gate 13 by the conductive line
8 are connected.

Next, the operation of the conventional charge transfer device will be described with reference to FIG. After applying a high-level voltage to the reset gate 14 to set the potential of the n-type impurity layer 4 under the floating gate 13 to the reset potential V ₃ , the voltage applied to the reset gate 14 is set to a low level and the floating gate 13 Lower n-type impurity layer 4
And the n ⁺ -type impurity layer 16 are electrically separated. FIG. 3 shows the potential distribution in the cross section of FIG.
(A). At this time, the clock φ ₁ is at the high level,
φ ₂ is in a low level state, and the signal charge transferred from the left in FIG. 3A is a final transfer electrode.
It is accumulated in a potential well below the first layer transfer electrode 10 to which the clock φ ₁ is applied.

Next, φ ₁ switches to a low level and φ ₂ switches to a high level. The potential distribution at this time is shown in FIG. The signal charge stored in the potential well below the first layer transfer electrode 10 to which φ ₁ is applied passes through the semiconductor surface below the first output gate 11 and the second output gate 12 and passes through the semiconductor surface under the floating gate 13 to the n-type. Transferred to impurity layer 4. As a result, the potential of the n-type impurity layer 4 below the floating gate fluctuates, and the potential of the floating gate 13 capacitively coupled to the impurity layer 4 fluctuates.

Here, n below the floating gate 13
Assuming that the capacitance of the impurity layer 4 is C _J , the gate capacitance of the floating gate is C _G , and the ground capacitance of the conductive line 18 is C _L , an electrical equivalent circuit at the output portion is as shown in FIG. Can be shown. Now, if the amount of signal charge has been transferred to is Q, the potential change Δv in n-type impurity layer 4, the total volume of the n-type impurity layer 4 as C _T, is given by the following equation. _{Δv = Q / C T C T} = C J + (C G · C L) / (C G + C L) The potential change [Delta] V 'is, [Delta] V' of the floating gate 13 = Δv · (1 / C L) / [(1 / C _G ) + (1 /
Since given by C _L)], the potential change [Delta] V of the floating gate 13 ', [Delta] V' obtained as = Q / C 'C' = C J + C L + (C J · C L) / C G. Here, the capacitance C 'expressed in the above equation is referred to as a charge detection capacitance. This potential change ΔV ′ is output to the outside via the output transistor 17.

[0009]

In a solid-state imaging device which is one of the applied devices of the charge transfer device, the area of a unit pixel has been reduced as the number of pixels has increased in recent years, and as a result, the signal charge amount has been reduced. As a result, lower noise and higher sensitivity of the charge detection unit are increasingly required. Thus, in the above-described conventional charge transfer device, the magnitude of the output voltage corresponding to the signal charge amount is determined by the charge detection capacitance C ′, and the magnitude of the output voltage corresponding to the constant signal charge amount is The smaller the detection capacity C ', the larger the detection capacity. Therefore, to detect charges with high sensitivity, C _J
And small comb and C _L, but it is sufficient to increase the C _G, also have manufacturing limits trying reduce the area of the charge detection part in order to reduce the C _J and C _L, the larger area Increasing _CG also has a necessary upper limit to maintain the performance of the charge transfer unit. Therefore, in the charge transfer device by the conventional FGA method, it is difficult to increase the sensitivity, and the characteristic of the low noise charge detection of this method is reduced.

[0010]

According to the present invention, there is provided a charge transfer region provided in a surface region of a semiconductor substrate and a charge transfer region formed on the charge transfer region. A charge transfer electrode (6 to 10), a floating gate (13) provided at a subsequent stage of the charge transfer electrode on the charge transfer region, and a transistor (17) connected to the floating gate. A charge transfer device for detecting transfer charge by an amplifying method , wherein a capacitor electrode (19) having the same potential as the charge transfer region is provided on the floating gate. Is done.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing one embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line AA '. In FIG. 1, the same portions as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals, and thus the duplicated description will be omitted. The present embodiment differs from the conventional example shown in FIG. 2 in that a shield electrode 19 is formed on the floating gate 13 with the insulating film 5 interposed therebetween. This shield electrode 19 is connected to the n-type impurity layer 4.

The operation of the present embodiment is the same as that of the conventional example shown in FIG. 3. If the amount of signal charges transferred to the charge detection section 2 is Q and the charge detection capacitance is C, the floating gate The potential change ΔV of No. 13 is represented by ΔV = Q / C. Charge detection capacitance C, the capacitance C _J of the floating gate 13 under the n-type impurity layer 4, and the gate capacitance C _G of the floating gate 13, and the earth capacitance C _L of the conductive wire 18, the shield electrode 19 and the floating gate from the inter-electrode capacitance C _P between _{13, C = C J + C} L + (C J · C L) / (C G + C P) and it can be calculated.

In this embodiment, since C _P is connected in parallel with C _G , the charge detection capacitance C is smaller than C ′ in the conventional example, and therefore, the potential change ΔV
Is larger than that of the conventional example. Shield electrode 1
9 can be formed simultaneously with the second-layer transfer electrodes 7 and 9. For example, if the electrode area is 8 μm × 10 μm and the oxide film thickness between the shield electrode 19 and the floating gate 13 is 0.2 μm, the charge detection is performed. The capacity can be reduced by about 10%.

Although the preferred embodiment has been described above,
The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention. For example, in the embodiment, the insulating film between the floating gate and the shield electrode is a silicon oxide film, but another insulating film such as a silicon nitride film can be used here. In the embodiment, the buried channel type two-phase driving method has been described. However, the present invention is applicable to a surface channel type and a device using a transfer clock of three or more phases. It is a good thing. Further, instead of the embodiment using only one floating gate, a so-called DFGA (Distributed Floa) in which floating gates are arranged in multiple stages and each output signal is added.
(ting Gate Amplifier) method may be adopted.

[0015]

As described above, the charge transfer device according to the present invention adds an additional capacitance to the floating gate in a charge transfer device that detects signal charges by the FDA method. For example, the effective capacitance of the floating gate can be increased, and the charge detection capacitance can be reduced. Therefore, according to the present invention, in an FDA type charge transfer device capable of performing charge conversion with low noise, a large output voltage can be taken out by highly efficient charge conversion. Therefore, high-quality image data can be obtained by applying the charge transfer device according to the present invention to a solid-state imaging device.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of an embodiment of the present invention.

FIG. 2 is a plan view, a cross-sectional view, and an equivalent circuit diagram of an output unit of a conventional example.

FIG. 3 is a potential distribution diagram for explaining the operation of the conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 charge transfer unit 2 charge detection unit 3 p-type silicon substrate 4 n-type impurity layer 5 insulating film 6, 8, 10 first layer transfer electrode 7, 9 second layer transfer electrode 11 first output gate 12 second output gate 13 Floating gate 14 Reset gate 15 n ^- type impurity region 16 n ⁺ type impurity layer 17 Output transistor 18 Conductive line 19 Shield electrode

Claims (3)

(57) [Claims] A charge transfer region provided in a surface region of the semiconductor substrate; a charge transfer electrode formed on the charge transfer region; and a charge transfer electrode provided on the charge transfer region after the charge transfer electrode. A charge transfer device including a floating gate and a transistor connected to the floating gate , wherein a capacitance electrode having the same potential as the charge transfer region is provided on the floating gate. . Wherein said floating gate is formed by first polysilicon layer, according to claim 1, wherein the capacitor electrode is characterized in that it is formed by the second polysilicon layer
A charge transfer device according to claim 1. 3. A reset gate is provided on the charge transfer region subsequent to the floating gate, and a reset drain is provided downstream of the reset gate adjacent to the charge transfer region. The charge transfer device according to claim 1.