JP2879894B2 - Semiconductor integrated circuit device having antifuse element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having an antifuse element and a method of manufacturing the same, and more particularly, to a field programmable gate array (F).
PGA), programmable read only memory (PR
The present invention relates to a semiconductor integrated circuit device having an antifuse element which is suitable for use in OM, has high reliability, and can operate at high speed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a gate array, a semiconductor integrated circuit device such as an FPGA or a PROM which can be programmed by a user on site is generally provided with an interlayer on a semiconductor substrate 10 such as a silicon substrate as shown in FIG. A first (metal) wiring layer (lower wiring layer) 14 formed via the insulating film 12 and a second (metal) wiring layer (formed on the first wiring layer 14 via the interlayer insulating film 18); Upper wiring layer) 20,
For example, a plurality of first (metal) wirings 16 are formed in the first wiring layer 14 in a direction parallel to the paper surface, and a plurality of second (metal) wirings 16 are formed in the second wiring layer 20 in a direction perpendicular to the paper surface, for example. A (metal) wiring 22 is formed. The first wiring 16 and the second wiring 22
Is electrically separated by the interlayer insulating film 18. Further, the first wiring 16 and the second wiring 22 are electrically connected via a connection hole 24 formed in the interlayer insulating film 18.

[0003] This type of semiconductor integrated circuit device,
PCT / US92 / 0391 as an antifuse element for electrically turning off / on the connection according to the circuit.
Structures such as 9 have been proposed. In this structure, the first
When a conductive plug 26 is formed by burying conductive tungsten W up to a connection hole 24 formed by opening an interlayer insulating film 18 formed on the wiring layer 14 and providing conductivity thereon. Film 2 for antifuse to be destroyed
An amorphous silicon film is formed as 8 and the second wiring 22 is formed thereon to form an antifuse element 30.

In FIG. 1, reference numeral 34 denotes a passivation (protection) film formed so as to cover the second wiring 22.

When writing an actual program,
A voltage of about 10 V is applied between the first wiring 16 and the second wiring 22 to destroy the antifuse insulating film 28. Then, as shown in FIG. 2, the antifuse insulating film 28 formed between the first wiring 16 and the second wiring 22 in the connection hole 24 is broken, and at the same time, the conductive plug 26
The molten metal diffuses from the upper surface of the second wiring 22 and the lower surface of the second wiring 22, and the filament 3
2 are formed, and the wires are electrically connected. Therefore,
In order to increase the speed of the circuit, it is required that the connected antifuse element 30 has a low resistance.

[0006]

SUMMARY OF THE INVENTION However, PCT
/ US92 / 03919, the conductive plug 26 is formed only of tungsten, and the titanium tungsten TiW is formed between the antifuse insulating film 28 and the second wiring 22. 1 wiring 16
A voltage of about 10 V is applied between the first wiring 22 and the second wiring 22 to break the insulating film 28 for antifuse, and a filament 32 formed by metal diffusion from the upper surface of the conductive plug 26 and the lower surface of the second wiring 22. Is formed of titanium and tungsten and has a problem of high resistance.

The antifuse insulating film 28 is formed on the surface of the first wiring 16 in the connection hole 24. If the conductive plug 26 is formed of metal, the surface of the conductive plug 26 is formed. Then, irregularities due to crystal grains as shown in FIG. 3 are formed. Since these irregularities include those having a sharp shape, when the insulating film 28 for antifuse formed on the surface of the conductive plug 26 is
A weak breakdown electric field is applied to the anti-fuse insulating film 28 formed on the smooth portion, and a strong strong breakdown electric field is applied to the anti-fuse insulating film 28 formed on the sharp portion. Is done. Therefore, the breakdown voltage becomes extremely small, and the antifuse insulating film 28 may be broken by noise when actually used, which causes a problem of low reliability.

Further, since the amorphous silicon film generally used as the antifuse insulating film 28 has low insulating properties, it must be thickened in order to enhance the insulating properties. In PCT / US92 / 03919, 160 nm
It is described. Accordingly, as shown in FIG. 2, the filament 32 formed by breaking the amorphous silicon film becomes longer, so that it is difficult to form the filament 32 with a uniform thickness, and the central portion of the filament 32 becomes thinner. It becomes easy to cut by Joule heat by energizing the state,
FIG. 4 illustrates a voltage-current curve of an antifuse element using a 160-nm-thick amorphous silicon as an antifuse insulating film. As shown in FIG. There is also.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to increase the reliability of an antifuse element, reduce the resistance, and increase the speed of a circuit.

[0010]

According to the present invention, there is provided a semiconductor device, comprising: a first wiring disposed on a first wiring layer formed on a semiconductor substrate; and a first wiring formed on the first wiring layer via an interlayer insulating film. A second wiring disposed in a second wiring layer, a connection hole formed in the interlayer insulating film, and a conductive plug disposed in the connection hole for connecting the first wiring and the second wiring; And a semiconductor integrated circuit device including an antifuse element having an antifuse insulating film formed on the conductive plug, wherein an upper layer of the conductive plug is formed of an amorphous metal,
This problem has been solved by forming the lower layer of a low-resistance metal.

As described above, by forming the upper layer of the conductive plug connecting the first wiring and the second wiring with an amorphous metal and forming the lower layer with a low-resistance metal, as shown in FIG. Since the insulating film for use 28 is formed on an amorphous metal (for example, tungsten silicide), which does not include crystals and has very small irregularities, which constitutes the surface of the conductive plug 26, the insulating film for antifuse at the time of writing Is no longer extremely reduced, and a highly reliable antifuse element can be provided. Further, by forming the lower layer of the conductive plug with a low-resistance metal, the insulating film for antifuse is broken, and the low-resistance metal can be contained in a filament formed by diffusing the lower-layer metal of the conductive plug. The circuit speed can be increased by lowering the resistance of the antifuse element.

When the lower resistance metal or the lowermost layer of the second wiring, which is in contact with the insulating film for antifuse, is made of aluminum or copper, or an alloy containing any one of these, the formation of the filament is difficult. Since the low resistance aluminum and copper are more easily contained in the filament, the resistance of the antifuse element can be further reduced.

In the case where the insulating film for antifuse is a single layer film of a silicon nitride film, a silicon oxide film or a tantalum oxide film having a high insulating property, or a composite laminated film, the insulating film for antifuse is formed of, for example, It can be as thin as 5-20 nm. Therefore, as shown in FIG. 6, the length of the filament 32 can be reduced to, for example, 1/20 or less, and it is easy to form the filament 32 into a uniform thickness. The filament does not break due to Joule heat.

According to the present invention, in a method of manufacturing a semiconductor integrated circuit device having an antifuse element, a step of forming a first wiring layer on a semiconductor substrate, and forming a first wiring in the first wiring layer. Forming an interlayer insulating film covering the first wiring, forming a connection hole in the interlayer insulating film on the first wiring, forming a low-resistance metal on the first wiring in the connection hole. Forming a lower layer of a conductive plug with the step of: forming an upper layer of a conductive plug with an amorphous metal on the lower layer of the conductive plug in the connection hole; The object has been achieved by including a step of forming a film and a step of forming a second wiring layer on the interlayer insulating film and the antifuse insulating film.

Further, the reliability is further improved by flattening the surface of the upper layer of the conductive plug before forming the antifuse insulating film.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 7 is a sectional view of a main part showing a wiring layer of a semiconductor integrated circuit device provided with an antifuse element according to an embodiment of the present invention.

As shown in FIG. 7, the antifuse element 3
In a semiconductor integrated circuit device provided with 0, a wiring layer is formed on a semiconductor substrate 10. As the semiconductor substrate 10, for example, a single crystal silicon substrate is used, and although not shown, semiconductor elements such as MISFETs and MOSFETs constituting an FPGA or a PROM are arranged on the main surface of the semiconductor substrate 10.

In the present embodiment, the wiring layer is a first layer.
It is composed of a two-layer wiring layer including a wiring layer (lower wiring layer) 14 and a second wiring layer (upper wiring layer) 20 disposed on the first wiring layer 14. The first wiring layer 14 is formed on the interlayer insulating film 12 covering the semiconductor element, and a plurality of first wirings 16 are arranged on the first wiring layer 14, for example, in a direction parallel to the paper. . The second wiring layer 20 is formed on the interlayer insulating film 18 covering the first wiring 16, and the second wiring layer 20 has a plurality of second wirings 22, for example, in a direction perpendicular to the paper surface. Be placed.

The space between the first wiring 16 and the second wiring 22 is
Connection hole (through hole) 2 formed in interlayer insulating film 18
4 are connected. In the connection hole 24, a lower plug 42 formed on the first wiring 16 and the lower plug 4
A conductive plug 40 having a two-layer structure including an upper plug 44 formed on the second plug 2 is formed. The upper plug 4
4 and the second wiring 22, an antifuse insulating film 2
8, there is no electrical connection, and no current flows. That is, in FPGA,
The program is not being executed and the PROM
Is in a state where data writing is not performed.

FIG. 8 shows a cross section of the main part of the wiring layer after a part of the antifuse insulating film 28 is broken and the filament 32 is formed between the upper plug 44 and the second wiring 22. is there. That is, in the FPGA, the program has been performed, and in the PROM, the data has been written.

Next, a method for manufacturing a semiconductor integrated circuit device provided with the antifuse element, in particular, a wiring layer will be described. 9 to 14 are main-portion cross-sectional views of the semiconductor integrated circuit device shown in each manufacturing process.

First, in a first step, as shown in FIG. 9, a plurality of first wirings 16 of a first wiring layer 14 are formed on an interlayer insulating film 12 on a semiconductor substrate 10 by a conventional method. I do. The first wiring layer 14 is made of, for example, titanium (thickness: 50 nm), titanium nitride (thickness: 100 nm) from below.
m), aluminum (thickness: 500 nm), and titanium nitride (thickness: 23 nm). This laminated film is formed by a commonly used sputtering method or CVD (C
Chemical Vapor Deposition). This laminated film is patterned by a commonly used photolithography technique and etching technique, and the first wiring 16 is formed.

In the second step, as shown in FIG. 10, an interlayer insulating film 18 is formed on the first wiring 16 in the same manner as in the prior art. A connection hole 24 is formed in 18. The interlayer insulating film 1
8 is formed of, for example, a silicon oxide film having a thickness of 1000 nm. The connection hole 24 is formed by a commonly used photolithography technique and etching technique, and has an opening diameter of, for example, 1.0 μm.

Next, in the third step according to the present invention,
As shown in FIG. 11, for example, Takeya
se et al. Ext. Abst. SSDM. , Pp-180 (199
With the selective Al-CVD technique as disclosed in 3),
The lower plug 42 is formed. The lower plug 42
May be formed by a Cu-CVD method or a blanket W-CVD method. Alternatively, after a film is formed by a blanket Al-CVD method or a blanket Cu-CVD method, the film can be formed by an ordinary etch-back process. Or A
After the film is formed by the 1 reflow method or the Cu reflow method, the film can be formed by an etch back process.

Next, in the fourth step according to the present invention,
As shown in FIG. 12, to form the upper plug 44,
For example, by a sputtering method or a CVD method, an amorphous metal film,
For example, a tungsten silicide film is formed on the entire surface. As the amorphous metal film for forming the upper plug 44, a metal silicide film other than tungsten silicide or a metal film having a melting point of 1200 ° C. or less can be used. This amorphous metal film is formed to have a thickness of, for example, 150 to 250 nm so that the components of the plug penetrate into the filament. In the present embodiment, for comparison, the thickness is 0n.
A tungsten silicide film of m, 75 nm, 100 nm, 150 nm, and 200 nm is formed.

In a fifth step similar to the conventional one, following the fourth step, as shown in FIG.
The surface of the upper plug 44 and the surface of the interlayer insulating film 18 are flattened by a mechanical polishing method.

In the subsequent sixth step, the surface of the upper plug 44 is wet-processed to be flattened. This wet treatment removes at least an oxide or nitride formed on the film surface by a silicidation treatment or the like, and removes a part of a surface layer portion having a thickness from the surface of the silicide film in a depth direction. Is performed to planarize the surface. In the present embodiment, in the wet treatment, aqueous ammoniacal hydrogen peroxide (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5,
(70 ° C.), for example, an ADMcleaning treatment for 5 minutes is performed. By this wet treatment, oxides having poor film quality or nitrides having sharp protrusions are removed, and further, by removing a part of the surface of the silicide film, sharp protrusions generated on the surface of the silicide film are removed. Thus, flattening of the surface of the upper plug 44 is promoted.

Next, in a seventh step similar to the conventional one,
As shown in FIG. 14, an antifuse insulating film 28 is formed at least on the connection hole 24. In the present embodiment, the antifuse insulating film 28 is formed not only on the surface of the connection hole 24 but also on the entire surface including the surface of the interlayer insulating film 18. As the antifuse insulating film 28,
In this embodiment, a silicon nitride film having a high insulating property is used. This silicon nitride film is, for example, silane,
The film is deposited by a plasma CVD method using a gas phase reaction of ammonia and a nitriding gas, and can have a thickness of, for example, 5 to 20 nm. In this embodiment, the nitriding gas 21 is used.
00 sccm, silane gas 100 sccm, ammonia gas 30
Using a 50 kHz high frequency 1 kW plasma at sccm,
The silicon nitride film having a thickness of 10 nm was formed by performing the treatment at an atmosphere pressure of 0.35 torr and a substrate temperature of 350 ° C. for 30 seconds. Since the antifuse insulating film 28 is formed on the surface of the upper plug 44 in which sharp protrusions on the surface are reduced and flatness is promoted, the defect density is reduced, and uniform and good film quality is obtained. Can be The antifuse insulating film 28 includes, in addition to the silicon nitride film, a single-layer film of a silicon oxide film or a tantalum oxide film, or any one of a silicon nitride film, a silicon oxide film, and a tantalum oxide film, and is superposed. Composite membranes can be used.

Next, as shown in FIG. 14, a plurality of second wirings 22 of the second wiring layer 20 are formed on the interlayer insulating film 18. In the present embodiment, since the antifuse insulating film 28 is formed on the entire surface on the interlayer insulating film 18, the second wiring 22 is formed on the antifuse insulating film 28. The second wiring 22 has a thickness of, for example, 100 n.
m, an aluminum alloy film having a thickness of 100 nm, an aluminum alloy film having a thickness of 600 nm, and a thickness of 23 n
The structure can be a structure in which m titanium nitride films are sequentially stacked. Conventionally, a titanium tungsten film is also formed in the lowermost layer in order to improve the familiarity with the tungsten plug, but in the present embodiment, the titanium tungsten film is unnecessary. Photolithography technology and etching technology are used for patterning.

Next, a passivation film 34 is formed on the upper surface of the second wiring 22 and the antifuse insulating film 28, and the structure shown in FIG. 7 is obtained.

In the above embodiment, the number of wiring layers is two, that is, the first wiring and the second wiring. However, the number of wiring layers is not limited to two. Is similarly applicable.

The conductive plug is not limited to the two-layer structure of the lower plug and the upper plug, but may have a multilayer structure of three or more layers.

[0034]

FIG. 15 shows the number of antifuse elements having a leakage current value of 1 μA or more when a voltage of 3.3 V is applied to 60 unwritten antifuse elements (area 100,000 μm ² ). An example of the relationship between the resistance value of the written antifuse element (via diameter 1.0 μm □) and the thickness of the tungsten silicide WSi on the plug is shown below. A 10-nm-thick silicon nitride film is used as the antifuse insulating film. The anti-fuse element is
Usually, a voltage of 5 to 20 V is applied, and writing is performed at a constant current of 1 to 20 mA for 5 to 100 msec. In this embodiment, 1
Writing was performed for 10 msec at 1 V and 10 mA. As the thickness of tungsten silicide increases from 0 nm to 200 nm, the number of antifuse elements whose leak current value becomes larger than 1 μA decreases. Since the thickness of tungsten silicide becomes 0 when the thickness is 100 nm or more, it is preferable that the thickness of tungsten silicide be 100 nm or more. On the other hand, the resistance value of the written antifuse element decreases as the thickness of tungsten silicide decreases. When the thickness of the tungsten silicide was 100 nm when the thickness was 200 nm, it becomes 5.3 Ω when the tungsten silicide is eliminated. Therefore, a two-layer structure of an amorphous metal such as tungsten silicide for the upper layer and a low-resistance metal such as aluminum or copper, or an alloy containing either aluminum or copper for the lower layer, as compared with the case where the plug is entirely filled with tungsten silicide. It is desirable to lower the resistance value by mixing lower layer aluminum or copper into the filament at the time of writing.

FIG. 16 shows that the thickness of the tungsten silicide constituting the upper plug is 200 nm, and the thickness of the titanium tungsten under the second wiring is 0 (Example of the present invention) or 200 nm (Comparative example close to the conventional example). 3 shows a resistance value in a state where writing is performed on the antifuse element. The lowermost layer of the second wiring in the example of the present invention without titanium tungsten or the upper layer of titanium tungsten of the second wiring in the comparative example is an aluminum alloy film having a thickness of 100 nm. The writing condition is 10 at 11 V and 10 mA.
msec. In the embodiment of the present invention, when the aluminum alloy film is formed directly on the silicon nitride film, the resistance value is 100Ω, but titanium tungsten is formed under the aluminum alloy film as in the conventional example. In this case, the resistance value is as high as 220Ω. Therefore, as in the embodiment of the present invention, it is possible to reduce the resistance value by stopping titanium tungsten in the lowermost layer of the second wiring and using aluminum or copper, or an alloy containing either copper or aluminum. it can.

FIG. 17 shows a voltage-current curve of an antifuse element according to an embodiment of the present invention using a silicon nitride film having a thickness of 10 nm as an antifuse insulating film for comparison with the conventional example shown in FIG. Is shown. For measurement, 11V10
An antifuse element written under a condition of 10 msec at mA was used. In the embodiment of the present invention, in the antifuse element using the silicon nitride film having a thickness of 10 nm, the current value increases without breaking the filament even when the voltage is applied up to 6 V. And thickness 1
In an antifuse element using an amorphous silicon film of 60 nm, as shown in FIG. 4, the filament is cut off at about 4 V and no current flows. As described above, when the silicon nitride film is used, since the resistance value is high, the insulating film for antifuse can be made thin, and an extremely reliable antifuse element can be provided. Instead of the silicon nitride film, a single layer film of a silicon oxide film or a tantalum oxide film may be used, or a composite film of these may be used.

[0037]

According to the present invention, it is possible to provide a highly reliable antifuse element having a low resistance value and a filament that is not easily broken.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure around a conventional antifuse element shown in PCT / US92 / 03919.

FIG. 2 is a sectional view showing a shape of a filament formed in a conventional antifuse insulating film.

FIG. 3 is a cross-sectional view showing an example of the surface properties of a conventional conductive plug.

FIG. 4 is a diagram showing an example of voltage-current characteristics of a conventional antifuse element using amorphous silicon having a thickness of 160 nm as an antifuse insulating film.

FIG. 5 is a cross-sectional view illustrating an example of the surface properties of the conductive plug according to the present invention for describing the effect of the present invention;

FIG. 6 is a sectional view showing an example of the shape of a filament in the insulating film for antifuse.

FIG. 7 is a sectional view showing a configuration around an antifuse element according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a state after the filament is formed.

FIG. 9 is a sectional view showing a first step for forming the structure of FIG. 7;

FIG. 10 is a sectional view showing a second step in the same manner.

FIG. 11 is a sectional view showing a third step in the same manner.

FIG. 12 is a sectional view showing a fourth step in the same manner.

FIG. 13 is a sectional view showing a fifth step in the same manner.

FIG. 14 is a sectional view showing a seventh step in the same manner.

FIG. 15 compares the thickness of the tungsten silicide constituting the upper plug, the number of antifuse elements having a leak current value exceeding 1 μA, and the resistance value of the written antifuse element for explaining the effect of the present invention. Diagram showing

FIG. 16 is a diagram showing an example of the relationship between the thickness of titanium tungsten formed under the second wiring and the resistance value of the written antifuse element.

FIG. 17 shows a film having a thickness of 10
diagram showing an example of voltage-current characteristics of an antifuse element using a silicon nitride film having a thickness of 10 nm.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12, 18 ... Interlayer insulating film 14 ... 1st wiring layer 16 ... 1st wiring 20 ... 2nd wiring layer 22 ... 2nd wiring 24 ... Connection hole 28 ... Insulating film for antifuse 30 ... Untuse element 32 ... Filament 35 Passivation film 40 Conductive plug 42 Lower plug 44 Upper plug

Claims (7)

(57) [Claims] A first wiring provided on a first wiring layer formed on a semiconductor substrate; and a second wiring formed on the first wiring layer with an interlayer insulating film interposed therebetween. A second wiring, a connection hole formed in the interlayer insulating film, a conductive plug arranged in the connection hole for connecting the first wiring and the second wiring, and a conductive plug on the conductive plug. In a semiconductor integrated circuit device provided with an antifuse element having a formed antifuse insulating film, an upper layer of the conductive plug is formed of an amorphous metal, and a lower layer is formed of a low resistance metal. A semiconductor integrated circuit device provided with an antifuse element. 2. The semiconductor integrated circuit device having an antifuse element according to claim 1, wherein said amorphous metal is tungsten silicide. 3. The semiconductor integrated circuit device according to claim 1, wherein said low-resistance metal is aluminum or copper, or an alloy containing any one of them. 4. A semiconductor device according to claim 1, wherein a lowermost layer of said second wiring in contact with said antifuse insulating film is made of aluminum, copper, or an alloy containing any one of them. A semiconductor integrated circuit device having a fuse element. 5. The antifuse element according to claim 1, wherein said antifuse insulating film is a single layer film of a silicon nitride film, a silicon oxide film or a tantalum oxide film, or a composite laminated film. Semiconductor integrated circuit device provided. 6. A method for manufacturing a semiconductor integrated circuit device having an antifuse element, comprising: forming a first wiring layer on a semiconductor substrate; forming a first wiring on the first wiring layer; A step of forming an interlayer insulating film covering the first wiring, a step of forming a connection hole in the interlayer insulating film on the first wiring, and a conductive plug made of a low-resistance metal on the first wiring in the connection hole. Forming an upper layer of a conductive plug of amorphous metal on a lower layer of the conductive plug in the connection hole; forming an insulating film for antifuse on the conductive plug. A method for manufacturing a semiconductor integrated circuit device having an antifuse element, comprising: a step of forming a second wiring layer on the interlayer insulating film and the antifuse insulating film. 7. A method of manufacturing a semiconductor integrated circuit device having an antifuse element according to claim 6, wherein a surface of a conductive plug upper layer is planarized before forming said antifuse insulating film. .