JP2880422B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit used for analog signal processing.

[0002]

2. Description of the Related Art FIG. 8 shows a main configuration of a conventional sample-hold circuit suitable for high-speed sampling of an analog signal. This sample and hold circuit is an analog switch 1
01, the hold capacitor 102, and the operational amplifier 10
3 is provided. The analog switch 101 supplies the sampling clock CL to the gate electrode via the control line 110.
N-channel MOS (metal oxide semico) supplied with K
nductor) transistor and a p-channel MOS transistor to which a complementary sampling clock XCLK is supplied via another control line 111. The analog switch 101 has two terminals, one terminal connected to the signal input line, the input voltage V _in is supplied to the signal input line. Input voltage V _in, the power supply voltage V _DD and the ground voltage V _SS
It changes rapidly within the range between Operational amplifier 103
Has a non-inverting input line and an inverting input line, and has two inputs M
It has a well-known internal structure having a differential amplifier stage composed of OS transistors. In the operational amplifier 103, the output voltage _Vout of the operational amplifier 103 is fed back to the inverting input line so as to form a voltage follower having a high input impedance and a low output impedance. The other terminal of the analog switch 101 is connected to a non-inverting input line of the operational amplifier 103. Hold capacitor 102, a non-inverting input line of the operational amplifier 103 is inserted between the constant potential line having a ground voltage V _SS.

[0003] According to the configuration of FIG. 8, during the sampling period, the analog switch 101 is turned on, charging and discharging are made to hold capacitor 102 in response to the input voltage V _in.
During the hold period, the analog switch 101 is turned off,
An operational amplifier 103 of a voltage follower type outputs an output voltage V corresponding to the charge stored in the hold capacitor 102.
Hold _out .

[0004]

In the above-mentioned conventional sample and hold circuit, ringing occurs in the output voltage _Vout mainly due to the parasitic capacitance 120 existing between the non-inverting input line and the inverting input line of the operational amplifier 103. However, as a result, there is a problem that desired output accuracy cannot be obtained. The gate-to-substrate capacitance of each of the two input MOS transistors constituting the differential amplification stage of the operational amplifier 103 is the parasitic capacitance 1
20 causes. In order to improve the frequency characteristics of the sample and hold circuit and reduce noise, it is necessary to increase the gate width of both input MOS transistors.
There is a situation that the gate-substrate capacitance of the OS transistor is inevitably increased.

The transfer function G of the sample and hold circuit shown in FIG.
_{(S) = V out / V} in is as _{G (s) = ω t /} {R on (C s + C p) s 2 + (R on C s ω t +1) s + ω t} (1) . Here, R _on: on-resistance C _s of the analog switch 101: capacitance value of the hold capacitor 102 C _p: capacitance value of the parasitic capacitance 120 ω _t = 2πf _t: at the angular frequency corresponding to the GB product f _t of the operational amplifier 103 is there.

For example, in the case of a sample and hold circuit for a baseband processing unit of a digital communication modem circuit, analog signal frequency = 100 kHz sampling frequency = 2 to 4 MHz R _on = 10 kΩ C _s = C _p = 1 pF (= C ₀ ) It is set as f _t = 10 to 20 MHz. Here, for simplicity, it is assumed that f _t = 1 / (2πR _on C ₀ ) = 15.9 MHz.

When an approximate expression of the transfer function G (s) expressed by the equation (1) is obtained, G (s) = ω _t / [2R _on C ₀ ｛s ² + (1 / R _on C ₀ ) _{s + (1 / R on C} 0) 2/2}] = ω t / {2R on C 0 (s + α / R on C 0) (s + β / R on C 0)} to become like (2). Here, α = (1 + j) / 2 β = (1-j) / 2 j: imaginary unit.

[0008] The transfer function G (s) in equation (2) has complex conjugate poles whose real part is negative. This is the output voltage V of the sample and hold circuit of FIG.
_This means that damped oscillation, that is, ringing occurs in _out . Due to this ringing, the output voltage _Vout is not stabilized during the sampling period, and the accuracy of the output voltage is reduced. When the sampling frequency is high and thus the sampling period is short, the accuracy of the output voltage is significantly deteriorated.

[0009] If the if GB product f _t is infinite operational amplifier 103, the ringing problem is solved. However, GB product f _t of the actual operational amplifier 103 is finite, also an increase in the GB product f _t, the operational amplifier 103
Power consumption increases.

A main object of the present invention is to provide a high-speed, high-accuracy, low-power consumption sample-and-hold circuit.

[0011]

In order to solve the above problems, a sample and hold circuit according to the present invention is provided between a non-inverting input line and a constant potential line of a voltage follower type operational amplifier in parallel with a hold capacitor. , Analog switch
Operational amplifier during switch on period (sampling period)
In order to suppress the ringing of the output voltage, a ringing cancel circuit formed by connecting a resistor and a capacitor in series is inserted.

[0012]

The transfer function of the sample-and-hold circuit having the ringing cancel circuit can have negative real poles instead of complex conjugate poles. this is,
The output voltage of the sample-and-hold circuit attenuates exponentially even if a parasitic capacitance exists between the non-inverting input line and the inverting input line of the operational amplifier and the GB product of the operational amplifier is not made too large. Means That is, the output voltage is stabilized within a short sampling period.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a sample and hold circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a main configuration of a sample and hold circuit according to a first embodiment of the present invention. This sample-and-hold circuit has the configuration of FIG.
And a ringing cancel circuit 107 formed by connecting a capacitor 106 and a capacitor 106 in series. Resistance 105
Is connected to the non-inverting input line of the operational amplifier 103,
The other end of the resistor 105 is connected via a capacitor 106 to a constant potential line having a ground voltage V _SS . Resistance 105
May be an ordinary passive element or an active element such as a MOS transistor. Hold capacitor 1
02 and the capacitor 106 of the ringing cancel circuit are formed using, for example, an interlayer insulating film interposed between two wiring layers.

The transfer function G of the sample and hold circuit shown in FIG.
_{(S) = V out / V} in is, G (s) = {ω t (R c C c s + 1)} / F (s) (3) F (s) = R on R c (C s + C p) ^{_{C c s 3 + {R on}} (C s + C p + C c) + R c C c + ω t R on R c C c C s} s 2 + {ω t (R on C s + R on C c + R c C c ) +1｝ s + ω _t (4) Here, R _on : on-resistance of the analog switch 101 R _c : resistance value of the resistor 105 C _s : capacitance value of the hold capacitor 102 C _p : capacitance value of the parasitic capacitance 120 C _c : capacitance value of the capacitor 106 ω _t = 2πf _t: is the angular frequency corresponding to the GB product f _t of the operational amplifier 103.

For example, in the case of a sample and hold circuit for a baseband processing section of a digital communication modem circuit, analog signal frequency = 100 kHz sampling frequency = 2-4 MHz R _on = R _c = 10 kΩ (= R ₀ ) C _s = C _p = C _c = 1 pF (= C ₀ ) f _t = 10 to 20 MHz Here, for simplicity, it is assumed that f _t = 1 / (2πR ₀ C ₀ ) = 15.9 MHz.

The denominator F of the transfer function represented by equation (4)
When an approximate expression of the (s), so that the F (s) = 2 (R 0 C 0) 2 s 3 +5 (R 0 C 0) s 2 + 4s + 1 / R 0 C 0 (5).

Furthermore, when obtaining an approximate expression of the equation (3) and (5) from the transfer function G (s), G (s ) = R 0 C 0 ω t (R 0 C 0 s + 1) / {2 ( _{^{R 0 C 0) 3 s 3}} +5 (R 0 C 0) 2 s 2 +4 (R 0 C 0) s + 1} = R 0 C 0 ω t (R 0 C 0 s + 1) / [{2 (R 0 C 0 ) S + 1｝ (R ₀ C ₀ s + 1) ² ] = ω _t (s + 1 / R ₀ C ₀ ) / [2R ₀ C ₀ ｛s + ／ (R ₀ C ₀ )｝ (s + 1 / R ₀ C ₀ ) ² ] = Ω _t / [2R ₀ C ₀ {s + 1/2 (R ₀ C ₀ )} (s + 1 / R ₀ C ₀ )] (6)

The transfer function G (s) in the equation (6) has negative real two poles. This means that the output voltage _Vout of the sample and hold circuit in FIG. 1 converges to a constant voltage while attenuating exponentially. That is, even if the parasitic capacitance 120 exists between the non-inverting input line and the inverting input line of the operational
Even if the product _ft is not made too large, the output voltage _Vout is stabilized within a short sampling period, and as a result, output accuracy is improved.

FIGS. 2A to 2C show the step response of the sample and hold circuit shown in FIG. The input voltage Vin is shown _in FIG.
As shown in (a), the voltage rapidly changes from the low voltage V _IL to the high voltage V _IH . The sampling clock CLK is shown in FIG.
As shown in the _figure , the voltage becomes the high voltage V _DD during the sampling period ts. At this time, the output voltage V _out of the sample and hold circuit of FIG. 1 becomes the low voltage V _out as shown by the solid line in FIG.
It reaches from the _OL to the high voltage V _OH at time t _n without ringing. Here, t _n <t _s . On the other hand, under the same conditions, ringing occurs in the output voltage V _out of the sample and hold circuit in FIG. 8 as shown by a dashed line in FIG.
It takes time t _c to reach from the low voltage V _OL to the high voltage V _OH. Here, t _c > t _s .

As described above, according to the first embodiment, the configuration in which the ringing cancel circuit 107 in which the resistor 105 and the capacitor 106 are connected in series is added to the configuration of FIG. In addition, a sample and hold circuit with low power consumption can be realized.

(Second Embodiment) FIG. 3 shows a main configuration of a sample and hold circuit according to a second embodiment of the present invention. This sample and hold circuit includes a hold capacitor 301
And the capacitor 302 of the ringing cancel circuit.
Two MIS (metal insula) connected in anti-parallel to each other
tor semiconductor) These are composed of capacitors. In addition, one end of the hold capacitor 301 and one end of the capacitor 302 of the ringing cancel circuit are connected to a constant potential line having a voltage half of the power supply voltage _VDD . Other configurations are the same as those in FIG.

FIG. 4 shows a sectional structure of the hold capacitor 301. The hold capacitor 301 includes first and second MIS capacitors 401 and 402.
The first MIS capacitor 401 is a p-type semiconductor substrate 40
5, an n-well 411 formed on the surface of
A thin p-type semiconductor layer 412 formed on the surface of the p-type semiconductor layer 412;
A gate electrode 414 formed on the insulating layer 413;
Lead electrodes 415 and 416 formed on exposed portions of the p-type semiconductor layer 412 are provided. The second MIS capacitor 402 includes an n-well 421 formed on the surface of the p-type semiconductor substrate 405, a p-type semiconductor layer 422 formed on the surface of the n-well 421, and the p-type semiconductor layer 422.
A thin insulating layer 423 formed thereon, and the insulating layer 423
A gate electrode 424 formed on the p-type semiconductor layer 4
The extraction electrodes 425 and 425 formed on the exposed portions
426. The gate electrode 414 of the first MIS capacitor and the extraction electrodes 425 and 426 of the second MIS capacitor are connected to the first extraction wiring 403 of the hold capacitor 301 and the extraction electrodes 415 and 416 of the first MIS capacitor and the second The gate electrode 424 of the MIS capacitor is connected to the second lead wire 404 of the hold capacitor 301. P-type semiconductor layers 412 and 42 of the first and second MIS capacitors
Of the two, portions immediately below the insulating layers 413 and 423 each function as a channel region. The cross-sectional structure of the capacitor 302 of the ringing cancel circuit is the same as that of FIG.

The first and second MIS capacitors 401,
In the case of 402, since the thin insulating layers 413 and 423 are used as a dielectric, a large capacitance value can be obtained with a small area. However, the voltage dependency of the capacitance value of the first MIS capacitor 401 depends on the gate electrode 414 and the p-type semiconductor layer 4.
12 is different depending on whether the applied voltage is positive or negative. The voltage dependency of the capacitance value of the second MIS capacitor 402 differs between a case where the applied voltage between the gate electrode 424 and the p-type semiconductor layer 422 is positive and a case where the applied voltage is negative. Therefore, the two MIS capacitors 401 and 402 are connected in anti-parallel with each other as shown in FIG. As a result, the voltage dependence of the capacitance value of the hold capacitor 301 becomes symmetric with respect to the case where the applied voltage is zero. Moreover, the voltage dependency of the capacitance value is small near the applied voltage of 0. On the other hand, the input voltage V _in of the sample and hold circuit of FIG. 3, varies within a range between the supply voltage V _DD and the ground voltage V _SS. One end of the hold capacitor 301 is connected to a constant potential line having a voltage half of the power supply voltage V _DD . Therefore, the applied voltage of the hold capacitor 301 is at most V _DD / 2, and the hold capacitor 301 is used in a voltage range having a small voltage dependency. The same applies to the capacitor 302 of the ringing cancel circuit.

As described above, according to the second embodiment, the hold capacitor 301 and the capacitor 302 of the ringing cancel circuit are respectively constituted by the two MIS capacitors connected in antiparallel to each other. Since the voltage at one end of each of the capacitors 302 is set to V _DD / 2, not only the area of the capacitors 301 and 302 can be reduced, but also the capacitors 301 and 302 can be used in a voltage range with small voltage dependency. . Note that the terminal voltage of both capacitors 301 and 302 is approximately V _DD / 2
Should be fine. Other effects are similar to those of the first embodiment.

(Third Embodiment) FIG. 5 shows a main configuration of a sample and hold circuit according to a third embodiment of the present invention. This sample-and-hold circuit has the configuration of FIG.
Ringing cancel circuit 503 formed by connecting a capacitor and capacitor 502 in series, and analog switch 504
And a second ringing cancel circuit 506 formed by connecting a capacitor and a capacitor 505 in series. One end of the resistor 501 of the first ringing cancel circuit is connected to the non-inverting input line of the operational amplifier 103,
The other end of 1 is connected via a capacitor 502 to a constant potential line having a ground voltage V _SS . The analog switch 504 of the second ringing cancel circuit includes an n-channel MOS transistor whose gate electrode is supplied with a sampling clock CLK via a control line 110 and another control line 1 like the analog switch 101 for sampling.
And a p-channel MOS transistor to which a complementary sampling clock XCLK is supplied via an output terminal 11.
Analog switch 504 of the second ringing cancel circuit has two terminals, one terminal connected to the signal input line, the input voltage V _in is supplied to the signal input line. The other terminal of the analog switch 504 is connected to a non-inverting input line of the operational amplifier 103 via a capacitor 505.

According to the configuration of FIG. 5, during the sampling period, the two analog switches 101 and 504 are turned on,
Charging and discharging are made to hold capacitor 102 in response to the input voltage V _in. During the hold period, both the analog switches 101 and 504 are turned off, and the operational amplifier 103 of the voltage follower type holds the output voltage _Vout according to the charge stored in the hold capacitor 102.

The transfer function G of the sample and hold circuit shown in FIG.
_{(S) = V out / V} in is, G (s) = [ω t (R c C c s + 1) {(R on + R d) C d s + 1}] / P (s) (7) P (s) = R _on [R _c C _c (C _s + C _p ) s ³ + (C _s + C _p + C _c + ω _t R _c C _c C _s ) s ² + ω _t (C _s + C _c ) s] (R _d C _d s + 1) + {(R on + R d) C d s + 1} (R c C c s + 1) (s + ω t) becomes as (8). Here, R _on : on resistance of the analog switch 101 R _c : resistance value of the resistor 501 R _d : on resistance of the analog switch 504 C _s : capacitance value of the hold capacitor 102 C _p : capacitance value of the parasitic capacitance 120 C _c : The capacitance value C _d of the capacitor 502: the capacitance value of the capacitor 505 ω _t = 2πf _t : an angular frequency corresponding to the GB product f _t of the operational amplifier 103.

For example, in the case of a sample-and-hold circuit for a baseband processing section of a digital communication modem circuit, analog signal frequency = 100 kHz sampling frequency = 2 to 4 MHz R _on = R _c = R _d = 10 kΩ (= R _{0) C s = C p =} C c = C d = 1pF (= C 0) is set as f _t = 10 to 20 MHz. Here, for simplicity, it is assumed that f _t = 1 / (2πR ₀ C ₀ ) = 15.9 MHz.

The denominator P of the transfer function represented by equation (8)
When an approximate expression of the (s), P (s) = {2 (R 0 C 0) 2 s 3 +6 (R 0 C 0) s 2 + 5s + 1 / R 0 C 0} (R 0 C 0 s + 1) (9)

Furthermore, when obtaining an approximate expression of the equation (7) and (9) from the transfer function G (s), G (s ) = R 0 C 0 ω t (2R 0 C 0 s + 1) (R 0 C _{0 s + 1) / [{} 2 (R 0 C 0) 3 s 3 +6 (R 0 C 0) 2 s 2 +5 (R 0 C 0) s + 1} (R 0 C 0 s + 1)] = R 0 C 0 ω t _{(2R 0 C 0 s + 1} ) (R 0 C 0 s + 1) / [{2 (R 0 C 0) 2 s 2 +4 (R 0 C 0) s + 1} × (R 0 C 0 s + 1) 2] = ω t ( s + 1 / 2R ₀ C ₀ ) (s + 1 / R ₀ C ₀ ) / {R ₀ C ₀ (s + γ / R ₀ C ₀ ) (s + δ / R ₀ C ₀ ) × (s + 1 / R ₀ C ₀ ) ² } = ω _{t (s + 1 / 2R 0} C 0) / {R 0 C 0 (s + γ / R 0 C 0) (s + δ / R 0 C 0) × (s + 1 / R 0 C 0)} is as (10). Here, γ = 1−2 ^−0.5 δ = 1 + 2 ^−0.5 .

The transfer function G (s) in equation (10) has negative real three poles. This means that the output voltage V _out of the sample and hold circuit of FIG. 5 converges to a constant voltage while attenuating exponentially. That is, even if the parasitic capacitance 120 exists between the non-inverting input line and the inverting input line of the operational amplifier 103, the G
Even if the B product _ft is not increased too much, the output voltage _Vout is stabilized within a short sampling period, and as a result, the output accuracy is improved.

FIG. 6 shows an application example of the sample and hold circuit shown in FIGS. 1, 3, 5 and 8. The example in FIG. 6 is a baseband processing unit of a digital communication modem circuit, and includes an analog signal source 601, a sample and hold circuit 602,
A low-pass filter 603 and an output load 604 are provided. The analog signal source 601 includes a digital circuit and a DA
(Digital-to-analog) an equivalent circuit to the converter,
This is a series circuit of an AC signal source that generates a sine wave voltage signal having _a frequency f _b (= 125 kHz) and an amplitude Va, and _a DC voltage source having a voltage V _DD / 2. Sample hold circuit 602
Has the configuration of FIG. 1, FIG. 3, FIG. 5, and FIG. The sampling frequency is 2 MHz. The low-pass filter 603 includes three resistors 611, 612, and 613.
Butterworth (Buttworth) comprising three capacitors 614, 615, 616 and one operational amplifier 617.
erworth) type filter with a cutoff frequency of 250 kHz. Input voltage V _in of the sample-and-hold circuit 602 is supplied from the analog signal source 601, the output voltage V _out of the sample and hold circuit 602 is supplied to a low pass filter 603. Low-pass filter 603
One end of each of the two capacitors 614 and 615 is connected to a constant potential line having a voltage V _DD / 2.
The output load 604 is an equivalent circuit of a circuit for modulating a carrier signal of frequency 200MHz in the output voltage V _L of the low-pass filter 603 is represented by impedance Z _L.

[0034] Among the output voltage V _L of the low-pass filter 603, the harmonic components other than the component of the frequency f _b is the distortion. FIG. 7 shows the result of the distortion analysis of the output voltage _VL . When the sample and hold circuits shown in FIGS. 1, 3 and 5 are used, an output voltage with lower distortion than the sample and hold circuit of FIG. 8 can be obtained. Also, comparing the sample and hold circuit of FIGS. 1 and 3 with the sample and hold circuit of FIG. 5, the use of the sample and hold circuit of FIG. 5 reduces the second and third harmonics, which are main components of distortion. It can be seen that the total harmonic distortion (THD) can be reduced.

In the sample and hold circuit of FIG. 5, the hold capacitor 102 and the capacitor 502 of the ringing cancel circuit are respectively constituted by two MIS capacitors connected in antiparallel to each other, and each of the capacitors 102 and 502 May be set to V _DD / 2.

[0036]

As described above, according to the present invention, a voltage follower type operational amplifier is connected in parallel with a hold capacitor between a non-inverting input line and a constant potential line.
During the analog switch ON period (sampling period)
Ringing of the output voltage of the operational amplifier
In this configuration, a ringing cancellation circuit formed by connecting a resistor and a capacitor in series is inserted, so that even if a parasitic capacitance exists between the non-inverting input line and the inverting input line of the operational amplifier, The output voltage of the sample-and-hold circuit is stabilized within a short sampling period even if the GB product is not so large. Therefore, there is an effect that a high-speed, high-accuracy, low-power-consumption sample-and-hold circuit can be realized. This sample and hold circuit is extremely useful as a sample and hold circuit used in a semiconductor integrated circuit for analog signal processing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sample and hold circuit according to a first embodiment of the present invention.

2 (a) is a waveform diagram of an input voltage of the circuit of FIG. 1 for examining a step response, and FIG. 2 (b) is an output voltage waveform of the circuit of FIG. 1 corresponding to the input voltage. FIG. 3C is a diagram showing the waveform of a sampling clock of the circuit of FIG. 1 together with a voltage waveform.

FIG. 3 is a circuit diagram of a sample and hold circuit according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a hold capacitor in FIG. 3;

FIG. 5 is a circuit diagram of a sample and hold circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an application example of the circuits shown in FIGS. 1, 3, 5, and 8;

FIG. 7 is a diagram illustrating a result of distortion analysis of an output voltage of a low-pass filter in the application example of FIG. 6;

FIG. 8 is a circuit diagram of a conventional sample and hold circuit.

[Explanation of symbols]

Reference Signs List 101 analog switch 102 hold capacitor 103 operational amplifier 105 resistance of ringing cancel circuit 106 capacitor of ringing cancel circuit 107 ringing cancel circuit 301 hold capacitor 302 capacitor of ringing cancel circuit 401 first MIS capacitor 402 second MIS capacitor 501 first Resistance of ringing cancel circuit 502 Capacitor of first ringing cancel circuit 503 First ringing cancel circuit 504 Analog switch of second ringing cancel circuit 505 Capacitor of second ringing cancel circuit 506 Second ringing cancel circuit 601 Analog signal Source 602 Sample hold circuit 603 Low pass filter 604 Output load

Claims (8)

(57) [Claims] 1. A voltage follower type operation having an analog switch having two terminals and one terminal connected to a signal input line, and a non-inverting input line connected to the other terminal of the analog switch. An amplifier, a hold capacitor inserted between the non-inverting input line and the constant potential line of the operational amplifier, and a ringing cancel circuit inserted between the non-inverting input line and the constant potential line of the operational amplifier. Sump with
A ring hold circuit , wherein the ringing cancel circuit includes the analog switch.
The output voltage of the operational amplifier during the ON period of the switch.
A sample-and-hold circuit comprising a resistor and a capacitor connected in series so as to suppress ging . 2. The sample and hold circuit according to claim 1, wherein said analog switch and said operational amplifier are each composed of a plurality of MOS transistors. 3. The sample and hold circuit according to claim 1, wherein said constant potential line has a ground voltage. 4. The sample and hold circuit according to claim 1, wherein the signal input line has a signal voltage range between a power supply voltage and a ground voltage, and the constant potential line is a half of the power supply voltage. A sample-and-hold circuit having a voltage. 5. The sample and hold circuit according to claim 4, wherein said hold capacitors are connected in antiparallel to each other.
A sample and hold circuit comprising: a plurality of MIS capacitors. 6. The sample and hold circuit according to claim 4, wherein a capacitor of said ringing cancel circuit is composed of two MIS capacitors connected in antiparallel to each other. 7. The sample and hold circuit according to claim 1, further comprising another ringing cancel circuit inserted between the signal input line and a non-inverting input line of the operational amplifier, wherein the other ringing cancel circuit is provided. Is a sample and hold circuit comprising an analog switch and a capacitor connected in series. 8. The sample and hold circuit according to claim 7, wherein an analog switch of said another ringing cancel circuit is constituted by a plurality of MOS transistors.