JP2881960B2 - Equalization method - Google Patents

Description

The present invention relates to an equalization method.

[Summary of the Invention]

The present invention provides an equalization in which an input signal is supplied to a series circuit of a plurality of delay means, and the input signal and a delay output signal of each delay means are multiplied by a coefficient and added to obtain an equalized output signal. In the method, an input signal is supplied to a series circuit of a plurality of delay means, transmitted in the series circuit in the forward direction and sequentially delayed, and then the input signal is transmitted in the reverse direction in the series circuit and sequentially delayed. After that, the input signal is transmitted in the positive direction in the serial circuit and is sequentially delayed, and the amplitude error of the output equalized signal is detected. According to the detected amplitude error, the amplitude error is minimized. In this way, the input signal and the delay output signal of each delay means are multiplied by the respective coefficients, the equalized output signal is subjected to phase synchronization processing, the phase error of the carrier is detected, and according to the detected phase error. , Input signal and equalized output signal To the signal held in the integration processing in the loop filtering processing of the phase synchronization processing, whether the input signal is transmitted in the positive direction in the serial circuit and sequentially delayed or transmitted in the reverse direction and sequentially delayed. Accordingly, by adding the positive and negative signs, the amplitude error of the output equalized signal and the phase error of the carrier of the input signal and the equalized output signal are simultaneously corrected to increase the equalization speed, and the input signal Even if the continuation signal is short or the input signal does not have a preamble, there is no fear of lack of a signal portion corresponding to the original signal portion of the input signal in the equalized output signal.

[Conventional technology]

One of the digital cellular communication systems that connects a base station (fixed station) and a mobile station (car phone) by radio waves is a time division multiple access system.
In this method, for each channel of the 900 MHz band, for example,
Six reception slots are provided, and a reception signal of one of the slots is received by 120 msac every 120 ms, and six transmission slots are similarly provided for each channel.
The transmission signal of one of the slots is transmitted. In this case, the reference reception carrier frequency and the reference transmission carrier frequency are different from each other.

[Problems to be solved by the invention]

By the way, in a base station or a mobile station, when trying to equalize a received signal using an equalizer, the duration of the received signal is extremely short (20 msec in the above case).
In the equalized output signal, there is a possibility that a signal portion corresponding to the original signal portion of the received signal is missing.

In view of the above, the present invention corrects the amplitude error of the output equalized signal and the phase error of the carrier of the input signal and the equalized output signal at the same time to increase the equalization speed and shorten the duration of the input signal. Another object of the present invention is to propose an equalization method that does not have a risk of lack of a signal portion corresponding to the original signal portion of the input signal in the equalized output signal even if the input signal has no preamble.

[Means and Actions for Solving the Problems]

The equalization method according to the present invention includes a plurality of n-stage delay units of a first stage to a last stage having a delay amount equal to one sampling period of an input signal from an input terminal, and an input signal and each output signal of the n-stage delay unit. (N + 1) coefficient multiplication means for multiplying the coefficient, addition means for adding the outputs of the (n + 1) coefficient multiplication means, and an output equalized signal based on the output equalized signal from the addition means Estimating means for estimating the amplitude error of each of the above, and based on the determination signal from the error estimating means, forming each of the different coefficient signals such that the amplitude error is minimized. The (n + 1) individual tap gain adjusting means to be supplied and the output equalized signal are subjected to phase synchronization processing to detect a carrier phase error, and the output equalized signal is converted according to the detected phase error. Phase synchronization processing to be normalized Means, integration processing means in the loop filtering processing means of the phase synchronization processing means, sign addition means for adding a plus or minus sign to the signal held by the integration processing means, first stage delay means and last stage delay means. Storage means for storing the respective sampling signals of the input signals which have protruded from each other is used.

Then, the continuous m pieces (where m
> N) is supplied to the input terminal, and the n-stage delay means are transmitted in the forward direction from the first-stage delay means to the last-stage delay means to be sequentially delayed, and then the n-stage delay means Are transmitted in the reverse direction from the last stage delay means to the first stage delay means and are sequentially delayed, and then the n stage delay means are transmitted in the forward direction from the first stage delay means to the last stage delay means. And the sign of the sign of the sign adding means is controlled in accordance with the direction of transmission of the m successive sampling signals constituting the input signal.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. This embodiment is based on the base station (fixed station) described above.
In a case where the present invention is applied to a digital communication system of a time division multiple access system connecting a mobile station (mobile telephone) and a mobile station (car telephone), for example, six reception slots are provided for each channel in the 900 MHz band. And one of them
The received signals of the 20 slots are received every 20 msec every 120 msec. Similarly, six transmission slots are provided for each channel, and the transmission signal of one of the slots is transmitted. ing. In this case, the reference reception carrier frequency and the reference transmission carrier frequency are different from each other.

FIG. 1 illustrates, in a circuit form, signal processing (arithmetic processing) by firmware of a digital signal processor in a transmitting / receiving apparatus of a mobile station (car phone), for example. Of course, it can be performed by the hardware (discrete circuit or IC) shown in FIG.

(12) is an equalization filter unit, and (11) is its input terminal. The input terminal (11) receives an input signal (duration: 20 ms
ec, a received signal of one slot) (input data signal).

The equalizing filter section (12) includes delay means D ₁ , D ₂ ,... Each having a delay amount equal to one sampling period Ts of the input signal.
.., a series circuit of Dm, an input signal and each delay means D ₁ ,
D _2, · · ·, coefficient multiplying means M ₀ for delayed output signal of Dm are respectively supplied, M _1, ····, and Mm, the coefficient multiplying means M _0,
M _1, · · ·, multiplying the output of Mm is respectively supplied, consists successively adding means A ₁ is cumulatively added, A _2, · ·, and Am,
The output of the adding means Am is used as the multiplying means (3
6), the multiplication calculation power is output from an output terminal (13) as an equalized output signal (equalized output data signal), and is also supplied to an error estimating unit (error estimating means) (14).

TG ₀ , TG ₁ , TG ₂ ,..., TGm are coefficient multiplying means.
Tap gain adjustment means provided separately for M ₀ , M ₁ ,..., Mm calculates each coefficient according to the amplitude error of the output equalized signal so that the amplitude error is minimized. Formed.

These tap gain adjusting means TG ₀ , TG ₁ , TG ₂ ,...
., TGm are similarly configured, and a complex conjugate signal forming means (33) for forming a complex conjugate signal of the input signal and the delayed output signal of each of the delay means D ₁ , D ₂ ,. A multiplying means (36) for multiplying the complex conjugate signal and an output signal of a coefficient multiplying means (18) described later, an adding means (34) for integrating the output signal of the multiplying means (36), and a delay amount of one sampling period Ts. .., Mm as the coefficient signal. The output of the integrating means is supplied to the corresponding coefficient multiplying means M ₀ , M ₁ ,..., Mm. ing.

In the following description, m and 2μ are used for convenience of explanation. μ
Is μ = 1, 2, 3,... Therefore, the coefficient multiplication means
The number of M ₀ , M ₁ , M ₂ ,..., Mm is 2μ + 1. or,
The coefficient signals supplied to the coefficient multiplying means M ₀ , M ₁ , M ₂ ,..., Mm are _denoted by C ₀ , C ₁ , C ₂ ,.

The reference signal r (n) is obtained from the error estimating unit (14) and supplied to the adding means (16), and the output of the multiplying means (36) is supplied to the adding means (16) so that the multiplying means (36) Is subtracted from the reference signal r (n) to obtain an estimated error signal e (n). The estimated error signal e (n) is represented by the following equation.

Assuming that the root-mean-square error is D, which is convex downward with respect to Cj, in order to minimize the root-mean-square error D, ΔD / ΔCj = 0 for all js. ∂D / ∂Cj is expressed by the following equation.

∂D / ∂Cj = E [Xn-j ・ e (n)] (2) Here, E [] represents an ensemble average. One of the solutions of this equation (2) is given by the following equation.

Cj (n + 1) = Cj (n) -α (∂D / ∂Cj) = Cj (n) -αE [Xn-j · e (n)] (3) where Cj (n) is Cj at t = nT Is a positive number sufficiently smaller than 1. This method is called a gradient method. Here, assuming that the ensemble average of the second term on the right side of Expression (3) is the average of the data at that time, the following expression is established.

Thus, the equation (3) is expressed as the following equation.

Cj (n + 1) = Cj (n) -αXn-je (n) (5) 1 ≦ K = 2μ + 1 (6) Next, the configuration of the PLL (phase synchronization processing means) (15) will be described. The PLL (15) includes a loop filter (loop filtering means) (21), a VCO (voltage controlled oscillator) (voltage controlled oscillator) (27), and the like.

The equalized output signal from the adding means Am is supplied to the multiplication means (36), and the output of the multiplication means (36) is multiplied by the multiplication means (19).
Supplied to Reference signal r from error estimator (14)
(N) is supplied to the multiplying means (19) through the complex conjugate signal generating means (20), and is multiplied by the equalized output signal.
(22).

The loop filter (21) includes the means (22) and the means (2
3) The adding means (24) to which the output of the means (23) is supplied and the output of the adding means (24) are supplied, and the output is supplied to the adding means (24). Integrating means comprising a delay means (25); and adding means (2) to which the output of the means (22) and the output of the adding means (24) are added.
6). The means (22) is composed of multiplying means for multiplying the input signal by the coefficient K and cascading means for multiplying the input signal by the sampling period Ts. Similarly, the means (23) adds the coefficient a to the input signal.
(= K / Z) and cascade means of multiplying means for multiplying the input signal by the sampling period Ts. The output of the adding means (26) is supplied to the adding means (28) of the VCO (27).

The VCO (27) includes an adding means (28) and an adding means (2
The output of (8) is supplied, and the output is supplied to the adding means (28).
9) and the phase shifting means (3
0) and a complex conjugate signal generating means (31) to which the output of the phase shifting means (30) is supplied.

Then, the output of the phase shifting means (30) is supplied to the multiplying means (36), and is multiplied by the output of the adding means Am. The output of the complex conjugate signal generating means (31) is supplied to the multiplying means (17) and multiplied by the error signal e (n) from the adding means (16), and the output is multiplied by a coefficient -α. Through the coefficient multiplying means (18), each of the tap gain adjusting means TG ₀ , T
G ₁ ,..., TGm are supplied to the multiplication means (32), respectively.

Thus, the input signal is divided into a plurality of delay means D ₁ , D ₂ ,.
・ Supply to the serial circuit of Dm, transmit in the serial circuit in the forward direction and delay sequentially, and then transmit the input signal in the reverse direction in the serial circuit and delay sequentially. This will be described in detail with reference to FIG. 2 in which the signal is transmitted in the forward direction in the serial circuit and is sequentially delayed.

Here, the input signal composed of the received signal of one slot is
Assume that the sampling signal is composed of a sequence of X ₀ , X ₁ , X ₂ ,..., Xn. Note that n is a number larger than m.

Although not shown, the sampling signals X ₀ , X ₁ , X ₂ ,..., Xn constituting the input signal are provided on the input terminal (11) side and the output side of the delay means Dm in the final stage. , Delay means D ₁ ,
Storage means of a predetermined capacity for storing sampling signals protruding from both sides of the series circuit of D ₂ ,..., Dm is provided.

First, this input signal is supplied to the input terminal (11) in the order of the sampling signals X ₀ , X ₁ , X ₂ ,..., Xn. Thus, at some point, as shown in FIG.
₋₁ , Dm− ₂ ,..., D ₂ , D ₁ are provided on the output side and the input terminal (11) with sampling signals X ₀ , X ₁ ,.
_-3 , Xm- ₂ , Xm- ₁ are output respectively, and finally, as shown in FIG. 2B, delay means Dm, Dm- ₁ ,.
D _2, to the output side and the input terminal of the D ₁ (11), respectively the sampling signal _{Xn-m, Xn-m +} 1, ···, Xn- 2, Xn
At the point when ₁ , Xn is output, the transmission direction of each sampling signal is reversed.

When Thus, at some later time, as shown in FIG. 2 C, delay means Dm, Dm- _1, · · · · · · ·, D _2, to the output side and the input terminal of the D ₁ (11) is , The sampling signal Xn−
m- ₂ , Xn-m- ₁ , ..., Xn- ₄ , Xn- ₃ , Xn
- ₂ is output, and finally, as shown in FIG. 2 D, and delay means Dm, Dm _1, · · · · ·, each of the output side and the input terminal of the _{D 2, D 1 (11)} , respectively sampled signal X ₀ , X ₁ , ..., Xm
- _2, xm- _1, when Xm is output, the transmission direction of each sampling signal is made to further reverse rotation.

When Thus, at some point, as shown in Fig. 2 E, delay means Dm, Dm- _1, · · · ·, to the output side and the input terminal of the D _2, D ₁ (11), the sampling signal X ₂ , X ₃ , ...
, Xm, Xm + ₁ and Xm + ₂ are output respectively, and finally the second
As shown in FIG. F, delay means Dm, Dm- ₁ ,...
The sampling signals Xn−m, Xn−m + ₁ ,..., Xn− ₂ , Xn are respectively applied to the output side of D ₂ and D ₁ and the input terminal (11).
- _1, equalization when Xn is output ends.

Then, the signal held by the integration means of the loop filter (21) of the PLL (15) is converted into an input signal from the input terminal (11) through a series circuit of delay means D ₁ , D ₂ ,. Positive and negative signs are assigned depending on whether the signals are transmitted in the positive direction and sequentially delayed or transmitted in the reverse direction and sequentially delayed.

In the above case, the input signal is delayed by the delay means D ₁ , D ₂ ,.
· · Dm- _1, Dm the series circuit from when one round trip, the equalized output signal, performs the risk-free equalization of lack of signal portions corresponding to the original signal portion of the input signal, the input signal The number of reciprocations may be two or more.

Next, referring to FIG. 3, π / 4 used in this embodiment will be described.
A modulation circuit of the shifted quadrature phase keying modulation method will be described. It should be noted that the present invention is not limited to such a modulation circuit, but the present invention can be applied irrespective of analog communication system or digital communication system.

Serial digital audio signal bm from input terminal (1)
Is supplied to a serial / parallel converter (2) and converted into 2-bit parallel digital signals Xk and Yk, and then supplied to a differential phase encoder (3).

Next, the encoding of the differential phase encoder (3) will be described with reference to FIG. As shown in FIG. 4I, points A (1,1), B (−1,1), C (−1,1) on the orthogonal I axis (real axis) and Q axis (imaginary axis) coordinates on the Z plane. 1) and D
Determine (1, -1). As shown in FIG. 4 II, the orthogonal I ′ axis (solid line) and Q ′ axis obtained by rotating the orthogonal I axis and Q axis coordinates on the Z plane of FIG. 4 by 90 ° (π / 4). Points on the (imaginary axis) coordinates a (1,1), b (-1,1), c (-1,1, -1) and d
Determine (1, -1). The coordinates of the orthogonal I ′ axis and the Q ′ axis are translated, and the orthogonal I axis and the Q ′
Overlay on axis coordinates. Thus, the coordinates of the points a, b, c and d on the orthogonal I ′ axis and Q ′ axis coordinates on the orthogonal I axis and Q axis coordinates are respectively It becomes.

Then, the encoded outputs Ik, Qk of the encoder (3)
Is a 2-bit output X of the serial / parallel conversion circuit (2) from one of points A to D on the orthogonal I-axis and Q-axis coordinates.
From the movement to any one of the points a to d according to k and Yk and from the one of the points a to d, according to the 2-bit output Xk and Yk of the serial / parallel conversion circuit (2), The movement to any one of the points A to D is shown. FIG. 3 shows the state of movement between any one of the points A to D and any one of the points a to d.
As shown in III, such a movement does not pass through the origin O.

The movement between any one of the points A to D and any one of the points a to d on the orthogonal I-axis and Q-axis coordinates is caused by a change (difference) ΔΦ in the direct angle connecting each point and the origin O. Can be represented by

Then, the relationship between Xk, Yk and ΔΦ is shown in the following truth table.

Then, Ik and Qk are represented by the following equations.

Ik = Ik− ₁ · cos [ΔΦ (Xk, Yk)] − Qk− ₁ · sin [ΔΦ (Xk, Yk)] Qk = Ik− ₁ · sin [ΔΦ (Xk, Yk)] + Qk− ₁ · cos [ΔΦ (Xk, Yk)] Then, the encode outputs Ik and Qk are passed through baseband filters (4a) and (4b), respectively, to a modulator (multiplier) (5
a) and (5b), which modulate (multiply with) the carrier from the carrier oscillator (6) and the carrier whose phase is shifted by 90 ° by the 90 ° phase shifter (7), and output each of them. Is added by the adder (8), and is output from the output terminal (9) as a digitally modulated signal.

〔The invention's effect〕

According to the equalization method of the present invention described above, a plurality of n-stage delay units of the first stage to the last stage having a delay amount equal to one sampling period of the input signal from the input terminal, and the input signal and the n-stage delay unit Multiply each output signal by a coefficient (n +
1) coefficient multiplying means, adding means for adding outputs of the (n + 1) coefficient multiplying means, and estimating an amplitude error of the output equalized signal based on an output equalized signal from the adding means. Based on the error estimating means, and the determination signal from the error estimating means, to form respective coefficient signals each having a minimum amplitude error and to supply them to the (n + 1) coefficient multiplying means, respectively (n + 1) ) Individual tap gain adjusting means and phase synchronization processing of the output equalized signal to detect a carrier phase error, and according to the detected phase error,
Phase synchronization processing means for normalizing the output equalized signal, integration processing means in the loop filtering processing means of the phase synchronization processing means, and sign addition means for adding a positive or negative sign to the signal held by the integration processing means, Using equalizing filter means including storage means for respectively storing sampling signals of the input signal protruding from the first-stage delay means and the last-stage delay means, and forming m continuous (where m> The sampling signal of n) is supplied to the input terminal, and the n-stage delay means is transmitted in the positive direction from the first-stage delay means to the last-stage delay means to be sequentially delayed. The signal is transmitted in the reverse direction from the last-stage delay means to the first-stage delay means and is sequentially delayed, and then the n-stage delay means is changed from the first-stage delay means to the last-stage delay means. Together headed by the transmission in the forward direction so as to sequentially delay, depending on the forward or reverse direction of transmission of the m sampling signals consecutive constituting the input signal,
Since the sign of the sign adding means is controlled,
The equalization speed can be increased by simultaneously correcting the amplitude error of the output equalized signal and the phase error of the carrier of the input signal and the equalized output signal, and the input signal has a shorter duration and the input signal has no preamble. This also eliminates the risk of lack of a signal portion in the equalized output signal corresponding to the original signal portion of the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the embodiment, FIG. 3 is a block diagram showing a modulation circuit, and FIG. 4 is an explanatory diagram of encoding of the modulation circuit. It is. (12) is an equalizing filter unit, D ₁ , D ₂ ,..., Dm are delay means, M ₀ , M ₁ , M ₂ ,.
A ₁ , A ₂ ,..., Am are addition means, (14) is an error estimator, TG ₀ , TG ₁ , TG ₂ ,..., Are tap gain adjustment means, (15) is PLL, 21) is a loop filter, (27) is V
CO.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 3/00-3/18 H04B 7/005 H04L 27/00-27/22 H03H 15/00-17/00

Claims (1)

(57) [Claims] A plurality of n-stage delay means of a first stage to a last stage having a delay equal to one sampling period of an input signal from an input terminal; and a coefficient added to each of the input signal and each output signal of the n-stage delay means. (N + 1) coefficient multiplying means, an adding means for adding the outputs of the (n + 1) coefficient multiplying means, and an output equalized signal based on the output equalized signal from the adding means. Error estimating means for estimating the amplitude error, based on the determination signal from the error estimating means, to form each different coefficient signal such that the amplitude error is minimized,
The (n + 1) individual tap gain adjusting means respectively supplied to the (n + 1) coefficient multiplying means and the output equalized signal are subjected to phase synchronization processing to detect a carrier phase error. Phase synchronization processing means for normalizing the output equalized signal in accordance with the phase error, integration processing means in the loop filtering processing means of the phase synchronization processing means, and a positive / negative sign for a signal held by the integration processing means And a storage means for storing sampling signals of the input signal protruding from the first-stage delay means and the last-stage delay means, respectively. Consecutive m pieces (where m> n)
Is supplied to the input terminal, and the n
The delay means of the stage is transmitted in the forward direction from the delay means of the first stage to the delay means of the last stage and is sequentially delayed, and then the delay means of the n stages is shifted from the delay means of the last stage to the delay of the first stage. The transmission is performed in the reverse direction toward the delay means and is sequentially delayed, and then the n-stage delay means is transmitted in the forward direction from the first-stage delay means to the final-stage delay means and is sequentially delayed. An equalizing method, wherein the sign of the sign adding means is controlled in accordance with the sign of the transmission direction of the continuous m sampling signals constituting the input signal.