JP2883501B2 - Trench insulated gate bipolar transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a trench insulated gate bipolar transistor (TrenchInsula).
ted Gate Bipolar Transist
or; hereinafter referred to as “T-IGBT”).
The present invention relates to a T-IGBT realizing miniaturization and low on-voltage.

[0002]

2. Description of the Related Art Conventionally, a T-IGBT has been known, and an example thereof is, for example, "IEEETransact".
ions Electrical Device, ED
−34 (11) pp. 2329, 1987 ". The n-channel T-IGBT described in the above document will be described below with reference to FIGS. FIG. 12 shows a conventional T-IG described in the above document.
It is sectional drawing which shows BT. FIG. 13 is an equivalent circuit diagram of the T-IGBT shown in FIG.

Referring first to FIG. 12, p ⁺ collector layer 3
An n ⁺ epitaxial layer 32 is formed on 1.
A collector electrode 40 is formed on the back surface (bottom surface) of p ⁺ collector layer 31. On this n ⁺ epitaxial layer 32, an n ^- epitaxial layer 33 is formed. P well region 34 is formed on n ⁻ epitaxial layer 33. An n ⁺ emitter region 35 is formed in a part of the surface of p well region 34.
This n ⁺ emitter region 35 is formed by diffusing high concentration n-type impurities.

An emitter electrode 39 is formed on n ⁺ emitter region 35 and p well region 34.
The trench 3 extends from the surface of the n ⁺ emitter region 35 through the p well region 34 to reach the n ⁻ epitaxial layer 33.
7 are formed. A gate insulating film 36 is formed on the inner surface of the groove 37, and a gate electrode 38 is formed on the gate insulating film 36. The gate electrode 38
For example, polycrystalline silicon into which impurities are introduced at a high concentration is used.

In FIG. 12, Wc / 2 indicates a unit cell width, and Wt / 2 indicates a half width of the groove 37. Wn indicates the width of the n ⁺ emitter region 35, and Wp / 2 indicates the width of the top surface of the p well region 34.

Next, the operation of the T-IGBT having the above structure will be described. First, referring to FIG.
2 includes a MOSFET 44 and a pnp transistor 45.
The pnp transistor 45 is driven by T44.

Referring again to FIG. 12, first, a high potential is applied to the collector electrode 40 and a low potential (or ground potential) is applied to the emitter electrode 39, respectively. In this state, a positive bias is applied to the gate electrode 38. Thereby, between n ⁺ emitter region 35 and n ⁻ epitaxial layer 33,
An inversion layer is formed along the side wall of the groove 37. That is, n
^An inversion layer is formed in channel region 41 defined by ⁺ emitter region 35 and n ⁻ epitaxial layer 33. Then, through this channel region 41,
Electron current 42 flows into n ⁻ epitaxial layer 33 from n ⁺ emitter region 35.

At this time, when a high potential is applied to the collector electrode 40, the p ⁻ collector layer 31 passes through the n ⁺ epitaxial layer 32 to the n ⁻ epitaxial layer 33.
Hole current flows into the substrate. Thereby, the pnp transistor 45 is turned on. This pnp transistor 45
Is turned off, the gate electrode 38 is biased to the ground potential or negatively biased. Thereby, the inversion layer in the channel region 41 disappears, and the pnp transistor 45 is turned off.

By having the above-described operation and structure, the T-IGBT has the following advantages.
First, in the T-IGBT, since the channel region 41 is formed in the depth direction, higher integration is possible as compared with a D-IGBT or the like in which the channel region is formed in the lateral direction. In addition, the J-FET effect which occurs between the wells, which is a problem in the D-IGBT, does not exist in the structure of the T-IGBT. Thus, the semiconductor device can have an extremely low on-voltage. Here, the ON voltage refers to a voltage required to flow a predetermined current per unit area.

[0010]

As described above, the conventional T-IGBT has the advantages of being able to achieve high integration and reducing the on-voltage, but has the following problems. Had also.

As described above, the conventional T-IGBT can be highly integrated, but the on-voltage may be increased only by miniaturization accompanying the high integration. This will be described with reference to FIGS. 11 and 14 to 16. FIG. 11 is a diagram showing the relationship between the unit cell width Wc / 2, the on-voltage V _CE (V), and the ratio R _PE (%) of the surface area of the p-well region 34 to the surface area of the unit cell. FIG. 14 shows a conventional T-MOSFET (Trenc
h Metal Oxide Semiconductor
or Field Effect Transisto
It is sectional drawing of r). FIG. 15 shows the T-
FIG. 3 is an equivalent circuit diagram of the MOSFET. FIG.
nded Abstracts of the 22n
d (1990 International) Co
nreference on Solid state D
devices and Materials, Send
ai, 1990, pp. 10 is a diagram disclosed in FIGS. 5-9, showing the ON resistance and the unit cell width (μ) in the T-MOSFET.
FIG. 7 is a diagram showing a relationship with m).

Referring first to FIG. 11, unit cell width Wc /
By gradually decreasing 2, the value of the ON voltage V _CE is gradually reduced. However, the value of Wc / 2 is 1.
It can be seen that in the region of 0 μm or less, the value of the ON voltage V _CE sharply increases. This is because pnp
This is considered to be due to a reduction in the formation region of the transistor. That is, as the pnp transistor formation region is reduced, the amount of current flowing in that region is also reduced.
Therefore, it is necessary to apply a high voltage to obtain a desired current amount. As a result,
The ON voltage will increase.

Here, referring to FIG. 14 to FIG.
A case where the OSFET is miniaturized will be described. FIG.
Referring to, n ⁻ drift layer 53 is formed on n ⁺ drift layer 52, and p well region 54 is formed on n ⁻ drift layer 53. This p-well region 54
An n ⁺ source region 55 is formed on the surface. This n
^A source electrode 59 is formed on ⁺ source region 55 and the p-well region. On the back surface of the n ⁺ drift layer 52, a drain electrode 60 is formed. Furthermore, n
^A groove 57 is formed from the surface of ⁺ source region 55 to n ⁻ drift layer 53. A gate electrode 58 is formed in the trench 57 via a gate insulating film 56. A channel region 61 is formed along the side wall of the groove 57.

FIG. 15 shows the T-IGBT shown in FIG.
3 shows an equivalent circuit diagram of FIG. In FIG. 15, the npn transistor 65 does not perform the rated operation, and the npn transistor is driven by the MOSFET 64.
Therefore, miniaturization of the width and the interval of the groove 57 is achieved by MOS
This is directly reflected in the high integration of the FET 64. Therefore, as shown in FIG. 16, as the miniaturization progresses, the reduction of the ON voltage of the T-MOSFET progresses.

As described above, when the same attempt was made on the T-MOSFET as described above, as shown in FIG. 16, the on-voltage (on-resistance) monotonously decreased with the increase in the unit cell density. Has been That is, as described above, it can be said that the problem that the on-state voltage rapidly increases with miniaturization is peculiar to the T-IGBT.

The present invention has been made to solve the above-described problems, and has as its object to provide a T-IGBT capable of simultaneously realizing high integration and low on-voltage.

[0017]

In one aspect, a trench insulated gate bipolar transistor according to the present invention has a first semiconductor layer of a first conductivity type and a second semiconductor layer formed on the first semiconductor layer. A conductive second semiconductor layer; a first conductive third semiconductor layer formed on the second semiconductor layer; and a second conductive type selectively formed on the surface of the third semiconductor layer. An impurity region, a groove extending in a depth direction from a surface of the impurity region, passing through the third semiconductor layer to reach the second semiconductor layer, a gate electrode formed inside the groove, and a third electrode.
It is assumed that the semiconductor device has an emitter electrode electrically connected to both the semiconductor layer and the impurity region, and a collector electrode electrically connected to the first semiconductor layer. And
The area of the top surface of the third semiconductor layer is 50% to 70% of the area of the bottom surface of the first semiconductor layer. Note that the expressions of “the top surface of the third semiconductor layer” and “the bottom surface of the first semiconductor layer” are “bottom surface of the third semiconductor layer” and “first surface of the first semiconductor layer” when viewed upside down. It should be construed that this can be synonymous with "the upper surface of the semiconductor layer." The same applies to the following embodiments.

In another aspect, a trench insulated gate bipolar transistor according to the present invention has a first conductivity type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer.
A conductive second semiconductor layer; a first conductive third semiconductor layer formed on the second semiconductor layer; and a second conductive type selectively formed on the surface of the third semiconductor layer. A first impurity region, a groove extending in the depth direction from the surface of the first impurity region, passing through the third semiconductor layer and reaching the second semiconductor layer, a third semiconductor layer and the first impurity region. It is assumed that an emitter electrode electrically connected to both of the regions, a gate electrode formed inside the trench, and a collector electrode electrically connected to the first semiconductor layer are provided. A second impurity region of the first conductivity type is formed immediately below the groove and at a predetermined distance from the first semiconductor layer and maintained at the same potential as the third semiconductor layer. The sum of the area of the upper surface of the third semiconductor layer and the area of the upper surface of the second impurity region is equal to the first area.
50% to 70% of the area of the bottom surface of the semiconductor layer. Preferably, between the third semiconductor layer and the second semiconductor layer, the fourth conductive layer of the second conductivity type having a higher concentration than the second semiconductor layer is provided.
Is formed, and a second impurity region is formed in the fourth semiconductor layer. Preferably, an uneven portion is formed on the bottom surface of the groove, and a second portion below the convex portion on the bottom surface of the groove is formed.
A second impurity region is formed in a region located on the semiconductor layer.

In still another aspect, a trench insulated gate bipolar transistor according to the present invention is formed on a first semiconductor layer of a first conductivity type and has a first height. A first upper surface; a second upper surface having a second height lower than the first height;
A second semiconductor layer of a second conductivity type having a third upper surface extending in the depth direction connecting the upper surfaces of the first and second semiconductor layers; and a third semiconductor layer of the first conductivity type formed on the second semiconductor layer. An impurity region of the second conductivity type selectively formed on the surface of the third semiconductor layer, and extending from the surface of the impurity region in the depth direction to the second semiconductor layer through the third semiconductor layer. An extending groove, a gate electrode formed inside the groove, an emitter electrode electrically connected to both the third semiconductor layer and the impurity region,
A collector electrode electrically connected to the first semiconductor layer, wherein a sum of an area of the third upper surface and an area of the second upper surface is:
It is 50% to 70% of the sum of the area of the bottom surface of the first semiconductor layer and the area of the third upper surface. Preferably, a plurality of the grooves are provided at predetermined intervals, and an impurity region is formed on the third semiconductor layer in a region between the grooves.

In the method of manufacturing a trench insulated gate bipolar transistor according to the present invention, first, a second semiconductor layer of a second conductivity type and a first semiconductor layer of a first conductivity type are formed on a first semiconductor layer of a first conductivity type. A third semiconductor layer is formed sequentially. First and second resist patterns are formed on the third semiconductor layer so as to define openings at predetermined intervals. Then, a predetermined amount of a second conductivity type impurity is introduced into the third semiconductor layer using the first and second resist patterns as a mask. Then, the first resist pattern is removed. After that, etching is performed using the second resist pattern as a mask to reach the inside of the second semiconductor layer under the region where the impurity is introduced,
In other regions, a groove that stays in the third semiconductor layer is formed. Then, a gate electrode is formed in this groove,
An impurity region of the second conductivity type is selectively formed on the surface of the third semiconductor layer adjacent to the trench sidewall.

According to a method of manufacturing a trench insulated gate bipolar transistor according to the present invention, in another aspect, first, a second semiconductor layer of a second conductivity type and a second semiconductor layer are formed on a first semiconductor layer of a first conductivity type. A third semiconductor layer of one conductivity type is sequentially formed. Then, a groove having a bottom surface is formed in the third semiconductor layer using a resist pattern having an opening having a predetermined width as a mask. Then, a predetermined amount of the second conductivity type impurity is introduced into a region located near the groove bottom and near the bottom of the groove bottom. By further etching using the resist pattern as a mask, a groove reaching the second semiconductor layer under the region into which the impurity is introduced and remaining in the third semiconductor layer under the other region is formed. Form. Thereafter, a gate electrode is formed in the groove, and an impurity region of the second conductivity type is selectively formed on the surface of the third semiconductor layer adjacent to the side wall of the groove.

[0022]

According to the trench insulated gate bipolar transistor of the present invention, the area of the upper surface of the third semiconductor layer is ensured at a certain ratio in the unit cell. This makes it possible to secure a current capacity flowing into the third semiconductor layer within a desired range. Thereby, it is possible to reduce the on-voltage even when miniaturizing.

In another aspect, the second region is located in the region located below the groove.
Impurity regions are formed. That is, the planar area of the third semiconductor layer is substantially expanded.
This makes it possible to secure a desired current capacity. As a result, it is possible to reduce the on-voltage even when miniaturizing.

In the case where the fourth semiconductor layer is formed so as to surround the second impurity region of the first conductivity type, the second impurity region is not affected by the current flowing through the channel region formed on the trench side wall. The effect can be reduced. This makes it possible to more reliably reduce the ON voltage. When an uneven portion is formed on the bottom surface of the groove and a second impurity region is formed in a region surrounded by the uneven portion, the second impurity region gives an electric current flowing through the channel region as described above. The influence can be significantly reduced. This makes it possible to more reliably reduce the ON voltage.

According to the trench insulated gate bipolar transistor of the present invention, in still another aspect,
A step is provided on the lower surface of the third semiconductor layer. That is, it is a step formed by the first, second, and third upper surfaces provided in the second semiconductor layer. By having such a step, when a current flows into the third semiconductor layer, the bottom portion (the portion contacting the second upper surface) and the side surface portion (the portion contacting the third upper surface) of the step portion It becomes possible to pour in from. That is, the area through which current can flow can be substantially increased. The desired current capacity can be obtained by setting the area of the side surface and the bottom surface of the step portion to a predetermined ratio in the unit cell.
This makes it possible to reduce the on-voltage when miniaturizing.

According to a method of manufacturing a trench insulated gate bipolar transistor according to the present invention, in one aspect, a predetermined amount of a second conductivity type impurity is previously implanted into a third semiconductor layer, and then the second conductivity type impurity is implanted. The region into which the impurity of the second conductivity type has been introduced and the region into which the impurity of the second conductivity type has not been introduced are simultaneously etched. Thereby, a groove is formed. The groove thus formed is formed so as to have an uneven portion on its bottom surface due to a difference in etching rate due to the introduction of impurities. Thus, a part of the bottom surface is located in the third semiconductor layer, and the other part of the bottom surface is capable of forming a groove located in the second semiconductor layer.

According to the method of manufacturing a trench insulated gate bipolar transistor according to the present invention, in another aspect, a trench is formed in advance in the third semiconductor layer so as to have a bottom surface, and then the trench is formed near the bottom surface of the trench. An impurity of the second conductivity type is introduced into a region near the bottom of the groove bottom. Thereafter, a groove is formed by further performing etching. Thus, the third semiconductor layer remains under the center of the groove, and it is possible to form a groove under the end of the groove and extending into the second semiconductor layer.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. FIG. 1 is a perspective view showing a T-IGBT according to a first embodiment of the present invention. Referring to FIG. 1, n ⁻ epitaxial layer 3 is formed on p ⁺ collector layer 1. P well region 4 is formed on n ⁻ epitaxial layer 3. On the surface of p well region 4, n ⁺ emitter region 5 is selectively formed. A groove 7 is formed from the surface of n ⁺ emitter region 5 to n ^- epitaxial layer 3. A gate insulating film 6 is formed inside the trench 7, and a gate electrode (not shown) is formed on the gate insulating film 6.
Is formed. An emitter electrode (not shown) is provided on n ⁺ emitter region 5 and p well region 4.
Is formed, and a collector electrode (not shown) is formed on the back surface of the p ⁺ collector layer 1.

In the T-IGBT having the above structure, the value of Wc / 2 is defined as a unit cell width. Also, Wp
The value of / 2 is defined as the width of the upper surface 4a of the p-well region. Furthermore, shows the area of the upper surface 4a of the p-well region 4 at Sp, shows the area of the bottom surface 1a of the unit cell S _A. In FIG. 1, the depth of the unit cell is indicated by D.

In the T-IGBT having the above-described structure, the ratio of Sp to S _{A is} expressed by R _PE = Sp / S _A ×
Defined as 100 (%). The current capacity is secured by setting the ratio R _PE to an appropriate value.

Here, the appropriate value of R _PE will be described in detail with reference to FIG. Referring to FIG. 11, as the unit cell width (Wc / 2) decreases, the value of R _PE also gradually decreases, but the on-voltage decreases because the effect of increasing the density of MOSFETs is large. . However, if the unit cell width is 1.5μ
After the on-voltage has bottomed out in the region of m to 1.0 μm, 1.
It rapidly rises below 0 μm. Therefore, the most effective way to reduce the ON voltage is that R _PE = 50% or more.
It can be said that the range is 70%. That is, by optimizing the groove width, the groove interval, and the pattern according to this ratio, the on-voltage is reduced and the T-IGBT is miniaturized.
Can be obtained.

Referring now to FIG. 2, the T-line shown in FIG.
Another embodiment of the IGBT will be described. FIG. 2 is a perspective view showing a first modification of the T-IGBT in the first embodiment based on the present invention. Referring to FIG. 2, in this modification, ap well region upper surface 4b is formed so as to be sandwiched between n ⁺ emitter regions 5. Even when the n ⁺ emitter region 5 is formed as described above, the value of R _PE is set to a value of 50% to 70%. This makes it possible to keep the on-voltage low.

Next, still another modification will be described with reference to FIG. FIG. 3 is a perspective view showing a second modification of the T-IGBT in the first embodiment based on the present invention. Referring to FIG. 3, in this modification, only the portion where only n ⁺ emitter region 5 is formed and the upper surface 4c of p well region 4 are formed along the wall surface of groove 7 in this unit cell. And a portion where the n ⁺ emitter region 5 and the p well region 4 are mixed. Also in this modification, the value of R _PE is 50% to 70%.
%. This makes it possible to reduce the ON voltage.

Next, a T-IGBT according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows a T-IG according to a second embodiment of the present invention.
It is sectional drawing which shows BT. Referring to FIG. 4, in the present embodiment, n ^- epitaxial layer 3 located immediately below trench 7 is formed.
A p-type impurity layer 19 is formed therein. The emitter electrode 9 is connected to the p-type impurity layer 19. That is, the p-type impurity layer 19 is maintained at the same potential as the p-well region 4. By providing the p-type impurity layer 19 in this manner, a part of the hole current 13 flows into the p-type impurity layer 19 as shown in FIG. That is, a pnp transistor built in also below the groove 7 is formed. This makes it possible to secure a desired current capacity.

In FIG. 4, W _p2 indicates the width of the upper surface of the p-type impurity layer 19, and W _p1 indicates the width of the upper surface of the p-well region 4. In this embodiment, R
The value of _PE is represented by the following equation.

[0036]

(Equation 1)

The value of R _PE shown in the above equation 1 is set to 50%
By setting the range to 70%, the on-state voltage can be reduced.

Next, a T-IGBT according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a T-IG according to a third embodiment of the present invention.
It is sectional drawing which shows BT. Referring to FIG. 5, in the present embodiment, one end of p-type impurity layer 19a is formed so as to be located near the bottom of the bottom end of groove 7. Then, n ⁺ base region 20 is formed to surround p-type impurity layer 19a.

Since the p-type impurity layer 19a is connected to the emitter electrode 9, the potential is close to the ground potential. Therefore, when the groove is formed so as to extend to the vicinity of the end of the groove 7, the flow of the electron current 12 flowing through the inversion layer formed in the channel region 11 may be suppressed. Then, it is conceivable that the ON voltage is increased instead. Therefore, by forming the n ⁺ base layer 20 so as to surround the p-type impurity layer 19a, the inflow of the electron current is promoted, so that the on-voltage can be more reliably reduced. In this embodiment, as in the second embodiment, the ratio of the sum of the area of the upper surface of the p-type impurity layer 19a and the upper surface of the p-well region 4 to the area of the unit cell is 50 to 70. %.

Next, a fourth embodiment according to the present invention will be described with reference to FIG. FIG. 6 is a sectional view showing a T-IGBT according to a fourth embodiment of the present invention. Referring to FIG. 6, in the present embodiment, an uneven portion is formed on the bottom surface of groove 7. Then, a p-type impurity layer 19b is formed in a region surrounded by the uneven portion.
The p-type impurity layer 19b is connected to the emitter electrode 9 and is kept at the same potential as the p-well region 4. As a result, the hole current 13 flows into the p-type impurity layer 19b. This makes it possible to obtain a desired current capacity, as in the second embodiment. Also, p
Since the p-type impurity layer 19b is formed so as to be surrounded by the uneven portion on the bottom surface of the groove 7, there is a concern that the p-type impurity layer 19b adversely affects the electron current as in the third embodiment. There is no. Note that also in this embodiment, p
The sum of the area of the upper surface of type impurity layer 19b and the area of the upper surface of p well region 4 is 50 times the unit cell area shown in FIG.
% To 70%.

Next, referring to FIG.
Example 5 will be described. FIG.
FIG. 17 is a sectional view showing a T-IGBT according to a fifth embodiment.
You. Referring to FIG. 7, in the present embodiment, a plurality of grooves 7 are provided.
Is formed. The width of the groove 7 is formed in the groove 7.
To the limits that can maintain the function as a MOS gate
The width is selected so that it can be integrated. Also p-well
The lower surface of the region 4 has a step, as shown in FIG.
It is formed so that. In this case, p-well
The depth of a part of the lower surface of the region 4 is deeper than the depth of the groove 7
It is formed as follows. Also, in this embodiment,
To prevent chip-up⁺The impurity layer 21 is provided
You. Note that in each of the above examples, the p-well region 4
This p ⁺An impurity layer 21 may be formed. Above
As described above, the lower surface of p well region 4 has a step portion.
Therefore, the hole current 13 is applied to the step portion of the p-well region 4.
From the side and bottom
You. Thereby, the p-well region into which the hole current 13 can flow can be obtained.
The area of the region 4 can be increased, and the desired current capacity can be increased.
It is possible to secure.

[0042] Incidentally, in FIG. 7, W _T is the width of the MOS gate forming region 22, W _p3 denotes the width of the p-well region 4 forming region 23. W _p4 indicates the depth of the p-well region 4 extending from the bottom of the groove 7 in the depth direction. In this embodiment, the structure shown in FIG. 7 is a unit cell. Therefore, the value of R _PE is represented by the following equation.

[0043]

(Equation 2)

The ON voltage can be reduced by adjusting the value of R _PE within the range shown by the above equation (2).

Next, referring to FIG. 8, the T-
A characteristic method of manufacturing an IGBT will be described. FIG.
(A), (b) and (c) show the T-IGB according to the present invention.
It is sectional drawing which shows one Example of the manufacturing method of T.

Referring to FIG. 8A, n ⁻ epitaxial layer 3 and p well region 4 are formed on p ⁺ collector layer 1.
Are sequentially formed. Then, an opening 15 is provided by applying a resist on the p-well region 4 and patterning the resist. That is, the first resist pattern 14a and the second resist pattern 14b are formed so as to define the opening 15. In this case, the position of the opening 15 is formed such that one end thereof coincides with the end of the groove 7 formed in a later step. Using the first and second resist patterns 14a and 14b thus formed as a mask, an n-type impurity such as phosphorus (P) is implanted at an implantation amount of 10 ¹⁶ cm ⁻² or more to form an n ⁺ impurity region. 17 is formed.

Thereafter, after removing the second resist pattern 14b, etching for forming the groove 7 is performed. At this time, since the etching rate is increased in the n ⁺ region 17 into which phosphorus is implanted, the n ⁺ region 17 is etched faster than other portions. By utilizing this, it is possible to form a trench 7 that reaches the n ⁻ epitaxial layer 3 under the region where the n ⁺ impurity region 17 is formed, and that stays in the p well region 4 in other portions. Become. Thereby, an uneven portion can be formed on the bottom surface of the groove 7, and the p-type impurity layer 19c can be formed in the uneven portion.

Thereafter, referring to FIG. 8C, a gate insulating film 6 is formed on the inner surface of the trench 7, and a polycrystalline silicon layer 8 doped with an impurity to become a gate electrode 8 is formed on the gate insulating film 6. To form Then, a cap oxide film 24 is formed on the gate electrode 8. Then, an n ⁺ emitter region 5 is formed on the surface of the p well region 4 by gas diffusion or ion implantation. The n ⁺ emitter region 5 is
It may be performed before the formation of the groove 7.

Next, a method of manufacturing a T-IGBT according to another embodiment of the present invention will be described with reference to FIG. 9A, 9B, and 9C are cross-sectional views showing steps of a method for manufacturing a T-IGBT according to another embodiment of the present invention.

First, referring to FIG. 9A, a p-well region 4 is formed through the same steps as in the above embodiment, and then a groove 7 is formed.
After a resist pattern 26 is formed so as to expose the formation region, a groove 27 having a bottom surface is formed in the p-well region 4 by using the resist pattern 26 as a mask. Then, an oxide film 28 is formed on the inner surface of the groove 27. Thereafter, an n-type impurity such as phosphorus (P) is ion-implanted using an oblique ion implantation method. At this time, the phosphorus ions are implanted only near the bottom of the bottom of the groove 27.

At this time, the projection range R _P of the oxide film is expressed by the following equation (3).

[0052]

(Equation 3)

In the above formula 3, θ indicates the implantation angle at the time of the oblique ion implantation, and t _OX indicates the thickness of the oxide film. The equation shown in Equation 3 above is
This will be described with reference to the schematic diagram shown in FIG. FIG.
Is a conceptual diagram for explaining the above equation (3). FIG.
By adjusting R _p so as to fall within the range of the above-mentioned Expression 3, from the consideration shown in FIG.
7 can be implanted only in the vicinity of the bottom end.

Next, referring to FIG. 9B, after phosphorus (P) ions are implanted as described above, the resist pattern 2
The groove 7 is formed by performing etching again using the mask 6 as a mask. Also in this case, as in the above embodiment, since the etching rate is high in the portion where the phosphorus ions are implanted, the groove 7 having the uneven portion on the bottom surface is formed as shown in FIG. 9B. Become. Then, the p-type impurity layer 19d remains in the uneven portion. After forming the p-type impurity layer 19d on the bottom of the groove 7 in this way, the resist pattern 26 is removed. Then, a gate insulating film 6 is formed on the inner surface of the groove 7, and a conductive material to be a gate electrode 8 is buried on the gate insulating film 6. Then, a cap oxide film 24 is formed on the gate electrode 8. After forming the cap oxide film 24 in this manner, the n ⁺ emitter region 5 is formed. Also in this embodiment, n ⁺ emitter region 5
May be formed before the groove 27 is formed.

[0055]

As described above, according to the present invention, T-I
When miniaturizing the GBT, a value such as the area of the upper surface of the third semiconductor layer or the sum of the area of the upper surface of the third semiconductor layer and the area of the upper surface of the second impurity region is obtained so as to obtain a desired current capacity. Selected. By setting the area of the upper surface of the third semiconductor layer or the like within a predetermined range in this manner, a formation region of the bipolar transistor can be secured, and a desired current capacity can be obtained. This makes it possible to more reliably reduce the on-voltage even when the device is miniaturized. That is, a high-performance semiconductor device can be obtained.

Further, according to the method of manufacturing a T-IGBT according to the present invention, it can be carried out with high accuracy without significantly changing the conventional process steps.

[Brief description of the drawings]

FIG. 1 shows TI in a first embodiment according to the present invention.
It is a perspective view which shows GBT.

FIG. 2 is a perspective view showing another aspect of the first embodiment based on the present invention.

FIG. 3 is a perspective view showing still another mode of the first embodiment according to the present invention.

FIG. 4 shows TI in a second embodiment according to the present invention.
It is sectional drawing which shows GBT.

FIG. 5 is a diagram illustrating a TI according to a third embodiment of the present invention;
It is sectional drawing which shows GBT.

FIG. 6 shows TI in a fourth embodiment according to the present invention.
It is sectional drawing which shows GBT.

FIG. 7 shows TI in a fifth embodiment according to the present invention.
It is sectional drawing which shows GBT.

FIGS. 8A and 8B are a cross-sectional view showing a first step of a manufacturing process, a cross-sectional view showing a second step, and a cross-sectional view showing a third step in one embodiment of a T-IGBT according to the present invention. ).

FIG. 9 is a cross-sectional view showing a first step of a manufacturing process in another embodiment of the T-IGBT according to the present invention, FIG. 9B is a cross-sectional view showing a second step, and FIG. c).

FIG. 10 is an explanatory diagram for explaining the ion implantation method shown in FIG.

FIG. 11 shows the unit cell width (Wc / 2) and the ON voltage V
FIG. 9 is a diagram showing a relationship between _CE and a ratio R _PE (%) of a surface of a p-well region to a unit cell surface area.

FIG. 12 is a sectional view showing a conventional T-IGBT.

FIG. 13 is an equivalent circuit diagram of the T-IGBT shown in FIG.

FIG. 14 is a sectional view showing a conventional T-MOSFET.

FIG. 15 is an equivalent circuit diagram of the T-MOSFET shown in FIG.

FIG. 16 is a diagram showing a relationship between on-resistance (OHM-CM ² ) and unit cell width (μm).

[Explanation of symbols]

1,31 p ⁺ collector layer 3,33 n ⁻ epitaxial layer 4,34 p well region 5,35 n ⁺ emitter region 8,38 gate electrode 9,39 emitter electrode 10,40 collector electrode 7,37 groove 19,19a, 19b, 19c, 19d p-type impurity layer 20 n ⁺ base region 21 p ⁺ impurity layer 27 groove

Claims (8)

(57) [Claims] A first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; and a second semiconductor layer formed on the second semiconductor layer. A third semiconductor layer of the first conductivity type, an impurity region of the second conductivity type selectively formed on the surface of the third semiconductor layer, and a third semiconductor layer extending in a depth direction from a surface of the impurity region. A groove extending through the semiconductor layer to the second semiconductor layer, a gate electrode formed inside the groove, and an emitter electrically connected to both the third semiconductor layer and the impurity region. An electrode, and a collector electrode electrically connected to the first semiconductor layer. In a trench insulated gate bipolar transistor, the area of the upper surface of the third semiconductor layer is smaller than that of the first semiconductor layer. 50 to 70% of the area of the bottom surface Trench insulated gate bipolar transistor. A first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; and a second semiconductor layer of a second conductivity type formed on the second semiconductor layer. A first conductive type third semiconductor layer, a second conductive type first impurity region selectively formed on the surface of the third semiconductor layer, and a depth from the surface of the first impurity region. A groove extending in a direction to pass through the third semiconductor layer and reaching the second semiconductor layer; a gate electrode formed inside the groove; and a third semiconductor layer and the first impurity region. An emitter electrode electrically connected to both, and a collector electrode electrically connected to the first semiconductor layer, a trench insulated gate bipolar transistor comprising: The third semiconductor layer at a predetermined distance from the first semiconductor layer; The are held at the potential 1
A conductive second impurity region is formed, and the sum of the area of the top surface of the third semiconductor layer and the area of the top surface of the second impurity region is 50 times the area of the bottom surface of the first semiconductor layer. % To 70%. 3. A fourth semiconductor layer having a second conductivity type and a higher concentration than the second semiconductor layer is formed between the third semiconductor layer and the second semiconductor layer, 3. The trench insulated gate bipolar transistor according to claim 2, wherein said second impurity region is formed in a fourth semiconductor layer. 4. An uneven portion is formed on the bottom surface of the groove, and the second impurity region is formed in a region located on the second semiconductor layer below the convex portion on the bottom surface of the groove.
3. A trench insulated gate bipolar transistor according to claim 2. 5. A first semiconductor layer of a first conductivity type, a first upper surface formed on the first semiconductor layer and having a first height, and a second upper surface lower than the first height. A second semiconductor layer of a second conductivity type having a second upper surface having a height of, and a third upper surface connecting the first and second upper surfaces and extending in a depth direction; A first conductive type third semiconductor layer formed on the semiconductor layer; a second conductive type impurity region selectively formed on the surface of the third semiconductor layer; and a depth from a surface of the impurity region. A groove extending in the direction extending through the third semiconductor layer to the second semiconductor layer, a gate electrode formed inside the groove, and an electric current applied to both the third semiconductor layer and the impurity region. An emitter electrode electrically connected; a collector electrode electrically connected to the first semiconductor layer; A trench insulated gate bipolar transistor having an area of the sum of the areas of the third area and the second upper surface of the upper surface, the area and the third upper surface of the bottom surface of said first semiconductor layer 50% to 70% of the sum of the above, and a trench insulated gate bipolar transistor. 6. The trench insulating gate according to claim 5, wherein a plurality of said grooves are provided at predetermined intervals, and said impurity region is formed on said third semiconductor layer in a region between said grooves. Type bipolar transistor. 7. a step of sequentially forming a second semiconductor layer of the second conductivity type and a third semiconductor layer of the first conductivity type on the first semiconductor layer of the first conductivity type; and Forming first and second resist patterns so as to define openings at predetermined intervals on the layer; and forming the first and second resist patterns in the third semiconductor layer using the first and second resist patterns as a mask. A step of introducing a predetermined amount of a second conductivity type impurity; a step of removing the first resist pattern; and a region into which the impurity is introduced by etching using the second resist pattern as a mask. Forming a groove reaching the second semiconductor layer below, and reaching the third semiconductor layer below the region where the impurity is not introduced; and forming a gate electrode in the groove. When Manufacturing method of the third trench insulated gate bipolar transistor having a step, the selectively forming an impurity region of a second conductivity type semiconductor layer surface proximate to said groove sidewalls. 8. A step of sequentially forming a second semiconductor layer of the second conductivity type and a third semiconductor layer of the first conductivity type on the first semiconductor layer of the first conductivity type, and an opening having a predetermined width. Forming a groove having a bottom surface in the third semiconductor layer by etching using a resist pattern having a mask as a mask; and forming a groove having a bottom surface in the third semiconductor layer. A step of introducing a certain amount of impurities of the second conductivity type, and further etching using the resist pattern as a mask to reach the inside of the second semiconductor layer below the region where the impurities are introduced, and Forming a groove that stays in the third semiconductor layer under the region where the silicon is not introduced, forming a gate electrode in the groove, and forming the third half adjacent to the groove side wall. Method of manufacturing a trench insulated gate bipolar transistor having a step of selectively forming a second conductive type impurity region on the body layer surface.