JP2884601B2 - Vector processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A vector processor having a plurality of models, each having a vector register having a capacity determined for each vector processor model, while maintaining compatibility with conventional logical specifications, A vector processor provided with a vector register having a capacity determined for each vector processor model, for the purpose of being able to indicate a wide range of vector register capacity for each,
A first vector control register (VCR0) having a first display bit (VC) composed of a plurality of bits, and a second vector control register (VCR1) having a second display bit (VRC) composed of a plurality of bits And the first display bit (VC)
Specifies a second mode (EF mode) when a predetermined value is determined in advance, and when the value is other than the specific value,
A mode designation means for designating a first mode (BF mode); and a value of the first display bit (VC) when the first mode (BF mode) is designated by the mode designation means. When the second mode (EF mode) is designated by the first designating means for designating the capacity of the correspondingly defined vector register and the mode designating means, the second display bit (EF mode) is designated. VR
C) and a second instructing means for instructing the capacity of the vector register determined in accordance with the value of (C). A display bit rewriting means for rewriting by an instruction is provided.

[Industrial applications]

The present invention relates to a vector processor having a plurality of models, each having a vector register having a capacity determined for each vector processor model.

The vector processor has a large-capacity register called a vector register in order to hold a large amount of data.

The capacity of the vector register differs depending on the model of the vector processor. When software, for example, an assembler, a compiler, or a target program uses the vector register, it is necessary to know the capacity of the vector register of the model on which the software is executed. is there.

For example, in the case of a compiler or the like, the method of compilation differs depending on the capacity of the vector register of the model. In a target program compiled so that it can be executed by any model, a specific vector in the program is actually used. It is necessary for an instruction to refer to a specific bit (VC) of the vector control register (VCR) of the model and to select and operate a program suitable for the capacity of the model.

For this reason, in the vector processor, the specific bit (VC) of the vector control register (VCR) provided in the vector unit (VU) indicates the capacity of the vector register of the model.

The above software uses this vector control register (VC
By reading R) with a specific vector instruction, the capacity of the vector register of the model can be known.

However, with the recent spread of supercomputers represented by vector processors, the use of supercomputers in various fields has led to an ever-increasing amount of vector data processing. Since the processing capability cannot be reduced in any model, the capacity of the vector register varies widely depending on the model.

Therefore, the capacity indication of the vector register needs to be able to indicate a wide range of capacity.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a diagram for explaining a conventional vector register capacity designating method, wherein (a) shows a configuration example of a computer system having a vector unit (VU), and (b) shows a configuration of a vector control register (VCR). An example is shown.

First, each instruction constituting a program is read out from the main storage unit (MSU) 3 to the scalar unit (SU) 1,
When the scalar unit (SU) 1 detects a vector instruction, it is sent to the vector unit (VU) 2.

In the vector unit (VU) 2, for example, when a load VCR instruction is recognized in the vector instruction control unit (VI) 2a, the vector instruction control unit (VI)
Vector control register (VCR) 21 provided in 2a
Is read and loaded into the general-purpose register (GR) 10 of the scalar unit (SU) 1.

In scalar unit (SU) 1, the general-purpose register (GR)
By referring to the display bit (VC) 210 of the vector control register (VCR) 21 loaded in 10, the capacity of the vector register (VR) in the vector unit (VU) 2 can be recognized.

This figure (b) shows the vector control register (VCR) 21
Shows the relationship between the bit value of the display bit (VC) 210 and the capacity of the vector register.

The value of the display bit (VC) 210 is determined by the model and cannot be rewritten by software.

Since the display bit (VC) 210 has only two bits as shown in the figure, only the vector register capacity of up to four types of models can be expressed.

In addition, since the other bits of the conventional vector control register (VCR) 21 are already allocated for other purposes, the number of bits of the display bit (VC) 210 cannot be expanded.

The present invention has been made in view of the above-described conventional drawbacks, and in a vector processor having a plurality of models, having a vector register having a capacity determined for each model of the vector processor, it is possible to specify a wide range of vector register capacity for each model. It is another object of the present invention to provide a vector register capacity designating means which is compatible with software created according to the above-mentioned conventional logic specification.

[Means for solving the problem]

The above problem is solved by a vector register capacity designating means configured as follows.

(1) A vector processor including a vector register having a capacity determined for each vector processor model, the first vector control register (VCR0) including a first display bit (VC) including a plurality of bits; A second vector control register (VCR1) having a second display bit (VRC) composed of a plurality of bits, and when the first display bit (VC) has a predetermined specific value, When the second mode (EF mode) is designated and the value is other than the specific value, the first mode (BF mode) is designated by the mode designation means for designating the first mode (BF mode) and the mode designation means. ) Is designated, the first instruction means for instructing the capacity of the vector register determined corresponding to the value of the first display bit (VC), and the mode instruction means, 2 of mode (EF mode)
Is designated, the second display bit (VR
And a second instructing means for instructing the capacity of the vector register determined according to the value of C). (2) The first display bit (VC) is configured to include a display bit rewriting unit that rewrites the first display bit (VC) according to a specific instruction from software.

[Action]

That is, according to the present invention, in a vector processor having a plurality of models having a vector register having a capacity determined for each vector processor model, a conventionally provided vector control register (VCR) , The first vector control register (VCR0), in addition to the vector register capacity display means indicated by the first display bit (VC) {display means in the BF mode}, a mode in which a wide range of vector register capacity is indicated. (EF mode)
Is provided.

Then, the conventional first vector control register (VC
When the first display bit (VC) of (R0) indicates, for example, '11', a second vector control register (VCR1) that can be referred to in the EF mode is provided as the EF mode. In the EF mode, the second vector control register (VCR1) functions to indicate the vector register capacity corresponding to the value of the second display bit (VRC) of the second vector control register (VCR1).

Then, the conventional first vector control register (VC
When the first display bit (VC) of the first vector control register (VCR0) indicates a value other than, for example, "11", the first display bit (VC0) of the first vector control register (VCR0) is the same as before. V
Specify the vector register capacity corresponding to the value of C).

Further, the conventional first vector control register (VCR)
Since the first display bit (VC) of (0) can be rewritten by software and can be set to either the BF mode or the EF mode, compatibility with the conventional logical specifications and interchangeability can be achieved. There is an effect that a wider range of vector register capacity can be instructed to software while keeping the same.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention, in which a first display bit (VC) 210 of a first vector control register (VCR0) 21 has a specific value (for example, '11 In the case of '), means for indicating, as the extension mode (EF mode), the vector register capacity corresponding to the value of the second display bit (VRC) 220 of the separately provided second vector control register (VCR1) 22 Is a means necessary to carry out the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the vector register capacity indicating means of the present invention will be described with reference to FIG.

In the present invention, in order to indicate a wide range of vector register capacity different for each processor model, a conventional vector control register {this is referred to as a first vector control register (VCR0)} and a second vector control register A register (VCR1) 22 is provided, and an extended mode (EF mode) is provided in which the vector register capacity is indicated by the second display bit (VRC) 220 of the second vector control register (VCR1) 22. On the other hand, the conventional display method, that is, the first display bit (VC) of the first vector control register (VCR0) 21 is used.
The mode in which the vector register capacity is specified at 210 is called a basic mode (BF mode).

Then, the first vector control register (VCR0) 21
Of the first indication bit (VC) 210 is a particular value, for example,
The case of '11' is set to the extended mode (EF mode).

In the present invention, the first display bit (VC) 210 of the first vector control register (VCR0) 21 is not fixed but can be rewritten by software.

Then, the first display bit (VC) 210 is set to '00', '0
The case of 1 ',' 10 'is the above-mentioned basic mode (BF mode), and indicates the same vector register capacity as the conventional one described with reference to FIG.

The first display bit (V
C) When the value of 210 is designated as "11", the above-mentioned extended mode (EF mode) is set, and the second display bit (VRC) 220 of the second vector control register (VCR1) 22 of the present invention is set.
The vector register capacity corresponding to the value (for example, 4 bits) is indicated.

Specifically, the vector register capacity in the extension mode (EF mode) is defined as, for example, 2 ^VRC kilobytes.

Therefore, as shown in FIG. 1, when VRC = '0000', depending on the value of the second display bit (VRC) 220,
When “2 ⁰ = 1 kilobyte” and VCR = “1111”, “2 ^0
1111 = 32 megabytes. "

The second display bit (VRC) 220 is model dependent and cannot be rewritten by software.

However, as described above, since the first display bit (VC) 210 of the first vector control register (VCR0) 21 can be arbitrarily specified by software, the conventional vector register in the basic mode (BF mode) is used. By setting the expansion mode (EF mode) as well as the capacity indication method, a wide range of vector register capacity can be indicated by the second display bit (VRC) 220 of the second vector control register (VCR1) 22. .

As described above, the vector register capacity indicating means of the present invention uses the first vector control register (VCR0) of the prior art.
The display bit (VC) of the first vector control register (VCR0) can be rewritten by software.
When the display bit (VC) is a specific value (for example, '11'), the second display bit (VCR1) of the separately provided second vector control register (VCR1) is set as the extension mode (EF mode). VRC) and the first vector control register (VCR).
0), when the first display bit (VC) is other than '11', the basic mode (BF mode)
The feature is that the vector register capacity corresponding to the value of the display bit (VC) is designated.

〔The invention's effect〕

As described in detail above, the vector register capacity indicating means of the present invention is a vector processor provided with a vector register having a capacity determined for each vector processor model, and includes a first display bit consisting of a plurality of bits. First vector control register (VCR0) with (VC)
A second vector control register (VCR1) having a second display bit (VRC) composed of a plurality of bits;
The second mode (EF mode) is designated when the display bit (VC) has a predetermined specific value, and the first mode (BF mode) is designated when the display bit (VC) is other than the specific value. When the first mode (BF mode) is designated by the mode designating means and the mode designating means, a vector register defined in correspondence with the value of the first display bit (VC) is set. When the second mode (EF mode) is designated by the first designating means for designating the capacity and the mode designating means, the value is determined corresponding to the value of the second display bit (VRC). And a second instructing means for instructing the capacity of the vector register in which the first display bit (VC) is set.
And a display bit rewriting means for rewriting the first mode (BF mode) or the second mode (EF mode) by the display bit rewriting means. Since this is specified, there is an effect that a wider range of vector register capacity, which differs for each vector processor model, can be specified while maintaining compatibility with the conventional logical specification.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional vector register capacity designating method. In the drawing, 1 is a scalar unit (SU), 10 is a general-purpose register (GR), 2 is a vector unit (VU), 2a is a vector instruction control unit (VI), 21 is a vector control register (VCR), or 1st. Vector control register (VCR0), 210 is the display bit (VC) or the first display bit (V
C) and 22 indicate a second vector control register (VCR1), and 220 indicates a second display bit (VRC).

Claims (2)

(57) [Claims] 1. A vector processor comprising a vector register having a capacity determined for each vector processor model, comprising: a first vector control register having a first display bit composed of a plurality of bits; A second vector control register provided with a second display bit, wherein the first display bit has a predetermined specific value, specifies a second mode, and specifies a second mode other than the specific value. When the first mode is specified by the mode specifying means, a vector specified in correspondence with the value of the first display bit is specified by the mode specifying means. First instruction means for instructing the capacity of a register; and value of the second display bit when the second mode is designated by the mode designating means. And a second instructing means for instructing the capacity of the vector register determined in accordance with (1). 2. The vector processor according to claim 1, further comprising display bit rewriting means for rewriting the first display bit by a specific instruction from software.