JP2884964B2 - Circuit degradation simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation method, and more particularly to a circuit simulation method for simulating deterioration of a circuit due to aging of a transistor.

[0002]

2. Description of the Related Art Circuit deterioration simulation expresses deterioration of transistor performance by changing model parameters based on how much deterioration has progressed, and simulates deterioration of the performance of the entire circuit by simulating using the model parameters. Is what you do. The model parameters on which the change is based are obtained from measurement data (current characteristics) obtained by a measurement test of DC deterioration of the transistor.

In the prior art simulation method, M
Since the substrate current is closely related to the deterioration of the OS transistor, the drain current,
In some cases, a table display is obtained based on the substrate current. For example, IEDM TECHNOLOGY DIGEST 19
88) on pages 134 to 137.

FIG. 2 is a flowchart showing a conventional simulation method. Simulation control step 1
It consists of deterioration calculation step 2 and circuit analysis program 3,
Control their execution. The circuit analysis program 3
A circuit analysis is performed based on the parameter information of the parameter file 4 before deterioration, the connection information of the connection information file 6, the parameter information of the parameter file 5 after deterioration, and the connection information. Output to analysis result 9. The deterioration calculation step 2 calculates the degree of deterioration of the element and the parameters after the deterioration from the circuit analysis result before deterioration and the deterioration information obtained by the DC deterioration measurement test of the deterioration information file 10 to obtain the deterioration list file 7. Output to the parameter file 6 after deterioration.

Further, a change in circuit performance such as a delay time due to deterioration of a MOS transistor in a circuit is taken as sensitivity of deterioration of a MOS transistor, and the sensitivity is multiplied by stress (substrate of substrate current) applied to the element ( There is a method of calculating the degree of circuit performance degradation by obtaining sensitivity and stress for each MOS transistor present in the circuit.
For example, International Conference Computer Aided Design (International Conference)
al conference On Computer
Page 25 of Aided Design 1987)
6 to 259.

[0006]

However, according to the above-mentioned first simulation method of the prior art, what kind of influence is caused by the deterioration of each transistor on the circuit, and which deterioration of the transistor is large in the circuit. There was a problem that it took time to find out whether it was affecting.

Further, in the second simulation method, the sensitivities of all the transistors in the circuit are obtained,
Further, since the degree of circuit performance deterioration is calculated, a simulation is performed for each transistor, so that there is a problem that it takes time for a large-scale circuit.

[0008]

According to the present invention, there is provided a circuit deterioration simulation method for analyzing a change in circuit operation due to aging of a transistor using a circuit simulator. Calculating the difference between the circuit simulation result based on the transistor parameters before the aging degradation and the circuit simulation result based on the transistor parameters after the aging degradation in time series for an arbitrary node, and ordering the calculation results for the arbitrary nodes in descending order. Arranging and displaying the calculation result corresponding to the transistor connected to the node.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a simulation method according to the first embodiment of the present invention.

The circuit deterioration calculating step 11 takes in the pre-deterioration analysis result and the post-deterioration analysis result from the pre-deterioration analysis result file 8 and the post-deterioration analysis result file 9, respectively, and extracts the information of the calculation points from the calculation point storage unit 13. The difference between the analysis result before deterioration and the analysis result after deterioration is obtained and passed to the display step 12. The display step 12 is based on the deterioration information of the deterioration list file 7, the calculation result from the circuit deterioration calculation unit 11, the connection information of the circuit connection information file 6, the information of the circuit deterioration, the magnitude of the fluctuation of the node potential, and the A list of the degree of deterioration of the connected transistor is displayed. The magnitude of the fluctuation of the node potential 電位
Vn is calculated by the following equation.

[0012]

Va: contact potential after deterioration, Vf: contact potential before deterioration, N: number of data The degree of transistor deterioration is calculated by the following equation.

[0014]

W: channel width, T: simulation time, Ids: drain current, Isub: substrate current, M,
B: Constant determined only by Vgd at the time of stress test The calculation point storage unit 13 is a step of storing information of nodes to be compared.

FIG. 5 is an output example of information on circuit deterioration of the N-channel MOS transistor shown in FIG.

FIG. 6 shows the N-channel MO shown in FIG.
It is an output example of the information of the circuit deterioration of the S transistor.

[0018]

As described above, according to the present invention, nodes having a large influence due to the deterioration can be narrowed down from one simulation before and after the deterioration of each transistor, so that a large-scale circuit simulation can be performed.

Further, by setting the node to be calculated at the entrance and exit of the partial circuit obtained by dividing the circuit for each operation, a partial circuit which has a great influence on the performance of the circuit is detected, and the partial circuit is further searched. By such processing, it is also possible to easily find a transistor that is affecting the performance of the circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a circuit deterioration simulation method according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a conventional circuit deterioration simulation method.

FIG. 3 is a circuit example of a ring oscillator.

FIG. 4 is a circuit example of a decoder.

FIG. 5 is a list showing a simulation result of circuit deterioration of the circuit example shown in FIG. 3;

FIG. 6 is a list showing a simulation result of circuit deterioration of the circuit example shown in FIG. 4;

[Explanation of symbols]

Reference Signs List 1 simulation control step 2 deterioration calculation step 3 circuit analysis program 4 parameter file before deterioration 5 parameter file after deterioration 6 connection information file 7 deterioration list file 8 analysis result file before deterioration 9 analysis result file after deterioration 10 deterioration information file 11 circuit deterioration calculation Step 12 Display step 13 Calculation point storage unit 41 to 56 Contact points M1N to M3N, M1P to M3P, MM1 to MM13
Transistor

Claims (1)

(57) [Claims] 1. A circuit deterioration simulation method for analyzing a change in circuit operation due to aging of a transistor using a circuit simulator, wherein a step of extracting a change in a transistor parameter; Calculating a difference from a circuit simulation result based on the transistor parameters after aging in time series for an arbitrary node; arranging the calculation result in descending order of the arbitrary node; and connecting the calculation result to the node A circuit degradation simulation method including a step of displaying corresponding to a transistor.