JP2885051B2 - Failure simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault simulation method, and more particularly to a fault simulation method for a delay fault in which a signal delay value of a logic circuit is out of an allowable range.

[0002]

2. Description of the Related Art A logic circuit realizes a desired logic operation by combining gate circuits such as AND and OR, and logic elements such as flip-flops and inverters. A delay utilization circuit such as a circuit is included. These circuits operate using a difference in signal propagation delay time of a reconvergent path on which a signal after branching is recombined, and are designed in strict consideration of element delay time and wiring delay time. . If these delay times deviate from the allowable values, the operation of the logic circuit becomes unstable,
This is a so-called delay failure state. Therefore, it is necessary to strictly handle the delay time even when simulating such a delay utilizing circuit.

On the other hand, in the fault simulation, it is necessary to faithfully simulate the behavior of a fault with respect to the test pattern of the logic circuit to be tested as described above. When executing the fault simulation, a change in a plurality of input external signals to be tested starts. It is necessary to consider tester skew, which is variation in timing, and variation in delay time of elements and wiring.

In the conventional general fault simulation method, that is, the first fault simulation method, a fault in which the signal value of the logic circuit to be verified is fixed to one value is targeted, and the above-described delay fault is performed. It was not targeted. IEE Computer Society, issued in the United States in November 1992
Test Technology Technical Committee (IEEE)
E Computer Society Test Te
Chronology Technical Commit
ee) The First Asia Test Symposium sponsored by Proceedings Fi
rst Asian Test Syposium: A
TS'92) pp. 52-56, "Path Delay Fault Simulation Algorithms for Sequential Circuits (Path Dela)
y Fault Simulation Algori
thms for Sequential Circuit
Its) A second fault simulation method for handling delay faults such as the fault simulation described in (Reference 1) has been proposed. However, since a special logic is defined and a special operation is required for each element, It is impossible to use the arithmetic processing unit of the first fault simulator that executes the above-described first fault simulation, and a large calculation time is required for complicated calculations.

Referring to FIG. 3 showing an example of a first logic circuit to be simulated for failure, the first logic circuit has input terminals T1, T2, T3 which receive supply of input signals I1, I2, I3, respectively. And AND which is an arithmetic element
It has gates G1 and G2 and an output terminal T14 for outputting an output signal O1.

Referring to Table 1 showing the signal values of the circuit in the case where there is no failure of the circuit shown in FIG. 3, that is, in the case of normal operation, the element names shown in the vertical columns of the table are input terminals, output terminals and The values of the output signals A and B of the AND gates G1 and G2 are shown. The horizontal line shows the pattern number. The value of the above circuit is the initial set value of each pattern in the test pattern for the input terminal, and the value at the time when the change ends in response to the change of the supplied input signal for each arithmetic element and output terminal, that is, The final value of each pattern is shown.

[0007]

[Table 1]

Here, the observation time at the output terminal is the last timing of each pattern, and a delay exceeding an allowable range due to a failure, that is, a delay failure is a failure in which a predetermined change is not completed by the end of each pattern due to the delay. And

Referring to Table 2, there is shown a set of fault information corresponding to each pattern, that is, a calculation result of a fault list according to the first conventional fault simulation method. The faults defined in this table correspond to the internal arithmetic elements excluding the input terminal and the output terminal, that is, the respective outputs A and B of the gates G1 and G2.
Is assumed to be a failure.

[0010]

[Table 2]

The fault information shown in Table 2 consists of three items separated by two colons (colon), and the first item is a propagation fault consisting of "element name where fault exists / value at fault". Indicates the type of “Value at the time of failure” is an abnormal value indicated by the presence of a failure. 0 is a normal value logic 1 and remains at logic 0 due to failure. 1 is a normal value logic 0 It indicates that the state remains at logic 1 due to a failure. The second and third terms respectively show the input value and output value of the target element when the fault propagates to the element shown in the element name column. The input values of an element having a plurality of inputs are shown in the order of terminal input from the upper side to the lower side of the corresponding element in FIG.

Here, in the first conventional simulation method, attention is paid to the failure information [A / 0: 11: 0] generated at the output A of the AND gate G1 in the second test pattern. In this failure pattern, the output B remains at logic 0 because the value of the lower input of the AND gate G2, that is, the value of the input I3 is logic 0 in the second pattern, and the output O1 does not propagate to the output terminal T14.
Is also a logical 0, and is a failure that cannot be detected in the second pattern. Next, when the process proceeds to the third pattern, the value logic 0 of the output A is held as it is, and the value of the input I3 becomes the logic 1, so that the value logic 0 of the output B becomes the output O.
1 as fault information, and therefore, it is determined that this fault is detected in the third pattern. However, it is the second pattern that the value of the output A changes from logic 0 to logic 1 in the normal circuit. Even if the change of the value of the output A takes more than one pattern, the change is the third pattern. By the time the eye is observed, it may have propagated to the terminal T14. In such a case, simply observing in the third pattern, even if there is a failure such that the change in the value of the output A does not propagate to the output terminal within one pattern, the value of the output O is the same as in the normal state. And therefore,
In the first conventional failure simulation method, detection and determination of this kind of delay failure is impossible.

Next, a second conventional fault simulation method shown in Reference 1 will be described with reference to Tables 3 to 5.

Table 3 shows 13 kinds of state values and codes corresponding to these state values in the second conventional fault simulation method, and Table 4 shows a case where an input change corresponding to the codes shown in Table 3 occurs. The operation results of the two-input AND gate are shown by codes, and Table 5 shows the operation results when the circuit of FIG.

[0015]

[Table 3]

[0016]

[Table 4]

[0017]

[Table 5]

Referring to Table 3, the 13 types of state values shown in the vertical columns of the table indicate the change state of the signal value in two consecutive clock periods as a hazard (a failure that may cause a plurality of changes such as spikes). Are shown in combination with the presence or absence of. The leftmost value indicates the value before the change, and the rightmost value indicates the value after the change, which are represented by logic 0, 1 and an indefinite value X. The symbol between the two vertical lines at the center indicates a change state, h indicates a hazard, nh
Indicates no hazard, and ~ (nasal symbol) indicates a change in which the presence or absence of the hazard is uncertain or observationally meaningless (don't care). For example, [1 | h | 0] represents a state change from logic 1 to logic 0 when there is a hazard, as [1 | nh |
0] indicates a state change from logic 1 to logic 0 when there is no hazard.

Referring to Table 5, the vertical columns of Table 1 represent Table 1.
The element names similar to the above and the pattern numbers of the test patterns are shown in the horizontal rows. For example, it indicates that the input I1 has changed from logic undefined in the first pattern to logic 0 in the don't care state, and has changed from logic 0 to logic 1 without hazard in the second pattern.

As described above, when a signal propagation simulation is performed, it is necessary to define special state values and execute special arithmetic processing for these state values for each element type. The use of the operation processing unit and the operation library of the above-described first failure simulation method makes it impossible to execute the failure simulation of the second failure simulation method, and performs complicated operation processing that causes an increase in operation time. There is a need to do.

[0021]

The above-mentioned first conventional fault simulation method targets a fault in which the output value of a logic circuit to be verified is fixed to one value, and detects and determines a delay fault. There was a drawback of not having the ability.

In the second conventional fault simulation method for delay faults, a special state value is defined and a special operation is required for each element. It is impossible to use the arithmetic processing unit, and there is a disadvantage that a large calculation time is required for a complicated operation.

[0023]

According to the present invention, there is provided a method for simulating a fault in a logic circuit which is generated due to a test pattern in which a period of a predetermined number of clock cycles supplied to an external input terminal is one pattern period. In a failure simulation method for tracking a signal change of a circuit element one by one and detecting a delay fault which is a failure where the signal change does not end within the one pattern period, an input terminal and an output terminal of the circuit element and each of the input and output terminals A fault model in which the delay fault exists is concentrated on a wiring portion connected to the first logic circuit, and a normal first logic circuit and a second logic circuit in which the delay fault exists are defined in units of one pattern period. The delay fault in the second logic circuit is performed in a first pattern period that is an arbitrary one pattern period. Generating first fault information including specific information of the generated first circuit element and change information of a first output value of the first circuit element with respect to a normal value caused by the delay fault; It is determined whether or not the first output value has changed in a second pattern period following the pattern period described above. If there is no change in the first output value, a list of target faults of the first circuit element is displayed. Deleting the first failure information from a certain first failure list, and adding the first failure information to the first failure list when there is a change in the first output value; The presence or absence of a change in the failure list is determined, and if there is a change in the first failure list, an operation corresponding to the change is performed, second failure information is added, the first failure list is updated, and the second failure list is updated. And generates the second failure list by the first circuit element. The first or second fault information is detected when the first or second fault list is propagated to an observable point of the second logic circuit. It is characterized by determining that it is possible.

[0024]

FIG. 1 is a flow chart showing a first embodiment of the present invention. Referring to FIG. 1, a failure simulation method according to the present embodiment shown in FIG. A failure in which the value change does not end is treated as a delay failure, and an initialization process (step S1) for setting the test pattern number to 1; a process for advancing the pattern number (step S2); The process of determining whether the number has exceeded the number (step S3), the process of determining whether there is an element to be operated (step S4), and whether the signal value of the element to be operated has changed from the signal value of the previous pattern Determination process (step S5)
A process of deleting the target failure of the operation target element from the failure list of the operation target element (step S6), and a process of adding the target failure of the operation target element to the failure list of the operation target element (step S7); Processing for determining whether there is a change in the failure list of the input of the element to be operated (step S
8), processing for performing an operation corresponding to the change in the failure list of the input of the operation target element to update the failure list of the operation target element (step S9), and performing a new operation for the current fan-out destination of the operation target element. Processing for Target Element (Step S
10) and a detection failure detection process (step S11).

The operation of this embodiment will be described with reference to FIG. 1. First, in step S1, initial values of elements in a logic circuit to be simulated are set, a failure list in the logic circuit is initialized, and a pattern number is set. Alternatively, the clock cycle number and the time are set as initial values. Here, the initial value usually starts as indefinite, and in the initialization of the failure list, normally, an empty set is set for all elements.
Also, the initial value of the pattern number is set to 0. Next, in step S2, a process of advancing the pattern number is performed, and preparation is made to supply the signal value of the test pattern of this number to the input terminal. If the result of the determination in step S3 indicates that the pattern number currently being processed exceeds the final pattern number, the process proceeds to END and ends. If it does not exceed the final pattern number, the process proceeds to step S4, and it is determined whether or not the calculation target element exists. The first element to be calculated in each pattern is all input terminals. If there is no such element, the process proceeds to step S11. If the target element exists, the process proceeds to step S5 to determine whether the signal value of the target element has changed from the signal value of the previous pattern. If there is no change in the signal value of the successive patterns in step S5, the process proceeds to step S6,
If there is a logic value fault corresponding to the signal value invariable in the fault list listing the faults targeted by the operation target element, that is, the target faults, the logic value fault is deleted from the fault list. As a result, the change in the signal value becomes 2
Stationary logical value faults detected over the pattern or more are deleted from the faults to be detected.

On the other hand, if there is a change in the signal value of the successive pattern in step S5, the process proceeds to step S7, and a fault corresponding to this change, that is, a delay fault, is added to the fault list. Regardless of the branch to step S6 or S7, the process proceeds to the next step S8 to determine whether or not the failure list has changed. The change includes an increase and decrease in the number of the elements together with a change in the content of the element of the target failure in the failure list. If there is a change in step S8, the process proceeds to step S9, where an operation corresponding to the change in the failure list is executed, the failure list is updated, and step S1 is performed.
Go to 0. If there is no change, the process proceeds directly to step S10. In step S10, the element to which the signal value of the current operation target element propagates is registered as a new operation target element.
Thereafter, the process returns to the determination process of step S4, and if there is no operation target element, the process proceeds to step S11, where it is determined that the delay propagated to the output terminal is a detectable delay fault. Here, the fault once detected can be deleted from the defined fault. Thereafter, the process returns to step S2, advances the pattern number, and repeats the processing of steps S3 to S11.

The failure simulation method of this embodiment is
For the first logic circuit to be simulated shown in FIG. 3 used in the description of the conventional technology, the initial value of the logic circuit is set to X, and a test pattern shown in Table 1 is supplied. Referring to Table 6 showing the list, it is assumed that the faults defined in this table are faults of the internal arithmetic elements excluding the input terminal and the output terminal, that is, the faults of the outputs A and B of the gates G1 and G2 as in the conventional case. This Table 6
The failure information shown in Fig. 3 is divided into two parts: (colon).
The first term indicates the type of propagation fault consisting of “element name where fault exists / D indicating delay fault and value at fault”. The “value at the time of failure” has the same definition as in the past. For example, D0 is a logical 0 due to a delay fault with respect to a normal logical 1
, And D1 indicates that the normal value logic 0 remains at logic 1 due to a delay fault. The other second and third terms are the same as in the related art, and thus description thereof is omitted.

[0028]

[Table 6]

Since the first pattern shown in Table 6 is a change from the initial value X and is not considered as a new change, the fault list corresponding to delay faults of all elements is an empty set.
In the second pattern, the output signal A of the AND gate G1 changes from logic 0 to logic 1, and the output signal A changes to 1 in a fault requiring more than one pattern period, that is, A
/ D0 is added to the failure list of the AND gate G1 together with the corresponding input signal value and the output signal value at the time of failure. However, in the second pattern, since the input signal on the lower side of the AND gate G2, that is, I3 is logic 0, this fault does not propagate any further.

Next, in the third pattern, the value of the output signal A does not change and the value of the output signal B changes.
The failure information corresponding to the output signal A is deleted from the failure list of the gate G1, and does not become a detection target delayed failure in the third pattern. On the other hand, for the AND gate G2, the output signal B changes from logic 0 to logic 1, and as a result, [B / D0: 1
1: 0] are added. The abnormal value corresponding to the influence of the failure propagates to the output terminal T14 in the third pattern, and the delay failure B / D0 is detected. As described above, the failure A / D0 causes the output terminal T1 during the second pattern.
No, it is not detected.

Referring to FIG. 2 which is a flow chart showing the second embodiment of the present invention, the difference between the first embodiment and the above-mentioned first embodiment is that a circuit element includes a storage element such as a flip-flop. And the step S24 of the process of deleting the failure list of the previous pattern other than the one propagated to the storage element between the step S3 and the step S4
Is inserted, step S6 is deleted, and step S1 is further deleted.
A step S30 is provided in which a new element to be operated is set as a fan-out destination element of a failure list or an element whose output value has changed in place of 0.

As a result, a pattern in which the abnormal value corresponding to the abnormal value corresponding to the influence of the fault does not propagate to the storage element in one pattern is deleted from the faults to be detected.

When this embodiment is applied to the failure simulation of the logic circuit shown in FIG. 3, first, a failure list that has not propagated to the storage element at the beginning of the pattern is deleted.
All the failure lists existing in the pattern are deleted, and only the part where a new change occurs is subjected to the arithmetic processing. Therefore, after the input signal I3, the AND gate G2 becomes operationally symmetric, and the value of the output signal B changes from logic 0 to logic 1,
As a result, [B / D] is added to the failure list of the AND gate G2.
0: 11: 0] are added. The abnormal value corresponding to the influence of the failure propagates to the output terminal T14 in the second pattern, and the delay failure B / D0 is detected.

As described above, in the fault simulations of the first and second embodiments, it is possible to discriminate between a fault which is fixed to a certain steady-state value and a delay fault which cannot be distinguished by the conventional first fault simulation method. It is.

Further, unlike the second conventional fault simulation method, the simulation for the normal circuit without using the definition of signal values dedicated to the delay fault simulation and the arithmetic processing is performed in the same manner as the first conventional fault simulation method. The processing is performed using the processing, and the processing for the faulty circuit is performed by replacing the input value or the output value with the signal value generated by the influence of the faulty circuit. Can be executed.

Next, referring to FIG. 4 showing a second logic circuit to be simulated for failure, this second logic circuit is an example of a sequential circuit including a storage element, and has input signals I1, I2, I3 and I3, respectively. Input terminals T1, T2, T3 and T5 receiving the supply of I4 and a clock CLK
T4, and inverters H21 and H22 which are operation elements and output signals V1 and V2, respectively.
A memory element, which receives a supply of a clock CLK at a clock terminal C of a signal at an input terminal D, outputs signals F1 to F4 using only non-inverted outputs, and outputs D-type flip-flops E21 to E24; Each signal A
AND gates G21 and G22 for outputting output signals O1 and A2, and an output terminal T for outputting output signals O1 and O2, respectively.
6, T7.

Referring to Table 7 showing a failure list of operation results of the second logic circuit by the failure simulation method of the second embodiment, the notation of this table is that the value of clock CLK is changed from logic 0 to logic 1 This is the same as the failure list of the first logic circuit in Table 6 except that the change, ie, the rise, is denoted by R.

[0038]

[Table 7]

Here, the observation time of the output signal value is from the rising time of the clock CLK to the time immediately before the rising of the next clock CLK. Only the first clock cycle starts from time 0, that is, the time immediately before the rising of the first clock. Up to. In addition, the delay fault here refers to a state where the change of the signal value is not completed by the above-mentioned observation time within each clock cycle.

Referring to FIG. 5, which is a time chart showing the timing relationship of the input signals of the second logic circuit shown in FIG. 4, each period of the test pattern corresponds to one cycle period of clock CLK. The values change in the middle of a clock cycle, and the values of the input signals I1 to I4 are given at predetermined times.

Referring to Table 7, since the initial value is undefined in the first clock cycle, all the fault lists are empty sets. In the second clock cycle, the inverter H
The output signals V1 and V2 of H21 and H22 both change from logic 0 to logic 1, and [V1 / D0: 0: 0] and [V2 / D0: 0: 0] as failure lists of the signals V1 and V2, respectively.
Is generated. In the second clock cycle, the output signal F of each of the flip-flops E21 and E22 is output.
1, F2 changes from the indefinite value X to logic 0.

Before shifting to the third clock cycle, the fault list other than the fault propagated to the flip-flops E21 and E22 as storage elements is deleted.
The fault information relating to D0 and V2 / D0 is not deleted because both have propagated to the flip-flops E21 and E22.
1 and F2 are added to the failure list. Also, the signals F1,
Since the value of F2 changes from logic 0 to logic 1, the fault list of the signals F1 and F2 includes [F1 / D0: 1
R: 0] and [F2 / D0: 1R: 0] are added. Further, since the lower input I2 of the AND gate G21 changes to logic 1, the value of the output signal A1 changes to logic 1. According to this, [A1 / D
0: 11: 0], and an AND gate G21
Is also added to the fault list of the signal A1. On the other hand, since the value of the input I4 on the lower side of the AND gate G22 is logical 0, no change occurs in the output signal A2, and therefore, a failure list of the signal A2 is not generated.

Before shifting to the fourth clock cycle, the fault list other than the fault propagated to the flip-flops E23 and E24 is deleted. Since the input of the flip-flop E23 is the signal A1, all but the fault list of the signal A1 are deleted. Also, the signal A of the input of the flip-flop E24
The failure list of No. 2 has not been generated as described above. 4th
In a clock cycle, failure information due to a change in the signal F3 itself and failure information corresponding to the failure list propagated to the signal A1 are generated as a failure list of the signal F3. This signal F
The fault corresponding to the fault list 3 is output signal O to output terminal T6.
Propagated as 1 and detected. Also, an AND gate G22
Since the value of the input I4 on the lower side changes to logic 1, the failure information corresponding to the change of the output signal A2 due to the change is added to the failure list of the signal A2. However, as described above, the abnormal value corresponding to the influence of the fault that has propagated to the upper input of the AND gate G22 in the previous third clock cycle is this one.
Since it has not propagated to the flip-flop F22 of the next stage in the cycle, it has been deleted, and no related fault information exists in the fourth clock cycle. Since the failure information corresponding to the change in the value of the signal A2 propagates to the flip-flop E24 in the fourth clock cycle, the failure information is propagated to the output terminal T7 as the output signal O2 together with the failure information accompanying the change in the output signal F4 in the fifth clock cycle. Detected.

Next, referring to FIG. 6 showing a third logic circuit to be simulated for failure, this third logic circuit is an example of a circuit having a signal branch and reconverge path, and the input signals I1 and I2 are respectively provided. Input terminals T1 and T2 receiving the supply of signals and operation elements and signals B1 and B, respectively.
Buffers C31, C32, and C33 that output 2, B3
And an AND gate G that outputs signals A1 and A2, respectively.
31 and G32, and an output terminal T6 for outputting the output signal O1.

Referring to Table 9, which shows a failure list corresponding to the first test pattern shown in Table 8, the notation of this table is based on the first to third failure lists of the first logic circuit shown in Table 6.
In addition to the term, each further has two fourth and fifth terms separated by a colon. The fourth term indicates the pattern number for which the failure information has been generated, and the fifth term indicates the number of changes in the input value. .
When the failure information changes a plurality of times, the arrow indicates the change from the first time to the second time.

[0046]

[Table 8]

[0047]

Referring to Table 9, in the first pattern, all signals change from indefinite values, and the fault squirrel is an empty set. In the second pattern, when the input signal I1 changes from logic 1 to logic 0, the output signals B1 and B2 of the buffers C31 and C32 change from logic 1 to logic 0, respectively, and the first change in the second pattern Therefore, the failure information corresponding to these output signals B1 and B2 is [B1
/ D1: 0: 1: 2: 1], [B2 / D1: 0: 1:
2: 1]. Further, this change propagates to the AND gate G31, and a fault list of the signal A1 is generated corresponding to the change of the fault list of the signal B1 and the change of the signal A1 itself. On the other hand, in the AND gate G32, first, as the first input change in the second pattern, the output signal A2 changes in response to the change in the signal B2, and [A2 / D1: 01: 1:
2: 1] and [B2 / D1: 11: 1: 2: 1] are first registered as a failure list. After that, the change in the signal A1 propagates to the AND gate G32, and at this time, the signal A1 changes to logic 0.
2 is deleted from the failure list, and only the failure information of A2 / D1 remains. Therefore, the failure list of the signal A2 after the second change is [A2 / D1: 00: 1: 2: 2].

For buffer C33, A2 /
[A2 / D1: 1: 1: 2: 1] for failure of D1
, But the failure of A2 / D1
Since a second input change occurs in the D gate G32, this information is propagated and the number of changes is updated to [A2 / D1: 1:
1: 2: 2]. On the other hand, for the failure of B3 / D1, since the input of the signal B1 changes only once, the failure information [B3 / D1: 0: 1:
2: 1]. The effect corresponding to the failure list of the signal B3 propagates to the output signal O1 as it is.

Therefore, A2 / D1 in the second pattern
And B3 / D1 failure of young detectable der Rukoto
You. In addition to this, the change in the input value of the element on the passage path
From the number information, the number of changes is 2 for A2 / D1.
And the number of changes is 1 for B3 / D1.
Therefore, the input of B3 / D1 , that is, the signal B
The path from the input of No. 3 to the previous output signal O1 is determined to be observable independently of the influence of the other paths since only one path for delay fault detection is specified. However, A2 / D
In the case of the failure of No. 1 , its input , that is , the input of signal A2
Multiple paths from the force to the previous output signal O1 cause changes
And for that, it is determined that a specific path is not possible.

[0051]

[Table 10]

[0052]

[Table 11]

On the other hand, referring to Table 11, which shows a fault-list corresponding to the second pattern in Table 10, the signal A1 changes to logic 1 in response to the change of the input signal I2 from logic 1 to logic 0 in the second pattern. From “0” to logic 0, and the failure list [A1
/ D1: 10: 1: 2: 1]. Further, the signal A2 changes and the fault detected at this time is the fault information [A2 / D1: 10: 1: 2: 1] of the signal A2 itself and the signal A2.
1 [A1 / D1: 11: 1: 2 ::
1]. This further propagates to the signal B3, the fault information [B3 / D1: 0: 1: 2: 1] and the fault information [A1 / D1: 1: 1: 2: 1], [A2 / D1:
1: 1: 2: 1], and these are output signals O
Propagate to 1. In this case, since there is no other path whose value changes, the number of changes is 1 for all detected faults.

Therefore, the detected faults are A1 / D1 and A2
/ D1 and B3 / D1, and since the path ahead is specified from the input of A1 / D1, it is determined that the influence of other paths can be independently observed.

Thus, by calculating and propagating the number of input changes of the element in which the change occurs, it is possible to determine whether or not the path for delay fault detection is specified.

[0056]

As described above, according to the fault simulation method of the present invention, in the first pattern period, the specific information of the circuit element in which the delay fault has occurred and the output value of the circuit element caused by the delay fault are normal. Generating first failure information including change information with respect to the value, adding the first failure information to the first failure list when there is a change in the output value, and changing the first failure list; , The second fault information is added and updated to generate a second fault list, and the second fault list is propagated to the second circuit element of the propagation destination, and the first or second fault information is propagated. When the fault list has propagated to the observable point of the second logic circuit, it is determined that the first or second fault information can be detected, thereby requiring a special state value definition and a special operation. Without the same There is an effect that it becomes possible to make detection and determination of the delay fault in a relatively small computation time by.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a first embodiment of the failure simulation method according to the present invention.

FIG. 2 is a flowchart showing a second embodiment of the failure simulation method according to the present invention.

FIG. 3 shows a first logic circuit to which the present invention and a conventional fault simulation method are applied.

FIG. 4 shows a second logic circuit to be subjected to the fault simulation method of the present invention.

FIG. 5 is a time chart showing a timing relationship of input signals of the circuit of FIG. 4;

FIG. 6 shows a third logic circuit to which the failure simulation method according to the present invention is applied.

[Explanation of symbols]

C31 to C33 buffers E21 to E24 flip-flops G1, G2, G21, G22, G31, G32 AN
D gate H21, H22 Inverter T1 to T8, T14 terminal

Claims (3)

(57) [Claims] 1. The method according to claim 1, wherein a signal change of a circuit element in a logic circuit caused by a test pattern in which a period of a predetermined number of clock cycles supplied to an external input terminal is one pattern period is traced one by one. A fault simulation method for detecting a delay fault, which is a fault in which the signal change does not end within a period, wherein the delay fault is concentrated on input and output terminals of the circuit element and a wiring portion connected to each of the input and output terminals. Is set, and an operation is executed for each of the normal first logic circuit and the second logic circuit where the delay fault exists in the one pattern period unit, and the arbitrary one pattern period In the first pattern period, the identification information of the first circuit element in which the delay fault has occurred in the second logic circuit and the delay fault And generating first failure information including change information of a first output value of the first circuit element with respect to a normal value, the first failure information being generated in a second pattern period subsequent to the first pattern period. It is determined whether or not the output value of the first circuit element has changed. If the first output value does not change, the first fault information is deleted from a first fault list which is a list of target faults of the first circuit element. And when there is a change in the first output value, adding the first failure information to the first failure list, determining whether there is a change in the first failure list, When there is a change in the list, a calculation corresponding to the change is performed, second failure information is added, the first failure list is updated, and a second failure list is generated. The output of the first circuit element propagates to a second circuit element to which the output propagates; A fault simulation method, comprising: determining that the first or second fault information can be detected when the first or second fault list propagates to an observable point of the second logic circuit. 2. A signal change of a circuit element including a storage element in a logic circuit, which is caused by a test pattern in which a period of a predetermined number of clock cycles supplied to an external input terminal is one pattern period, is tracked one by one. In the fault simulation method for detecting a delay fault, which is a fault in which the signal change does not end within the one pattern period, the method is characterized in that input and output terminals of the circuit element and wiring portions connected to each of the input and output terminals are concentrated. A fault model in which the delay fault exists is set, and an operation is executed for each of the normal first logic circuit and the second logic circuit in which the delay fault exists in the unit of one pattern period, and In a first pattern period which is the one pattern period, identification information of a first circuit element in which the delay fault has occurred in the second logic circuit; Generating first failure information including change information of a first output value of the first circuit element with respect to a normal value caused by the delay failure; a second pattern period next to the first pattern period; Determining whether there is a change in the first output value, and excluding failure information propagated from the first failure list, which is a list of target failures of the first circuit element, to the third circuit element, which is the storage element The first failure information is deleted, and the presence or absence of a change in the first failure list is determined. If there is a change in the first failure list, an operation corresponding to the change is performed and the second failure information is calculated. And updating the first fault list to generate a second fault list. Propagating the second fault list to a second circuit element to which the output of the first circuit element propagates; The first or second fault list is a list of the second logic circuit. Fault simulation method characterized by determining possible to detect the first or second failure information when propagated to measurement possible point. 3. The method according to claim 1, wherein the failure information is a element on a failure propagation path.
Wherein said contact Keru change frequency within a pattern period of the input of the child, the previous signal path from the input terminal of the device when a failure in which the change frequency is identified to be the one degree is propagated to the output terminal 3. The method according to claim 1 , wherein when the path for detecting the delay fault is specified as one, it is determined that the path is observable independently of the influence of the delay of the other path. Failure simulation method.