JP2886097B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a semiconductor memory device.
More specifically, the manufacturing method of
Dynamic random access memory (DRAM) cell
And a method for forming the same. [0002] FIG. 19 shows a conventional DRAM cell.
FIG. FIG. 19A shows an electric circuit of a DRAM cell.
It is a road map. In the figure, T transfers data (charge).
Transfer transistor composed of MOS transistors
, C is a storage capacity for storing charges, WL is a word line,
BL is a bit line. 6 is a storage electrode, 7 is a dielectric
A body film 8 is a counter electrode. FIG. 19B is a sectional view showing a DRAM cell structure.
FIG. In the figure, 1 is a p-type epitaxial layer, etc.
Of Si substrate and 2 are formed by LOCOS method etc.
Field oxide film (SiO_TwoMembrane), 3 and 4 are A⁺I
This is an impurity diffusion layer formed by diffusing ON etc.
The source or the drain of the transistor T. 5 is a word
Is an insulating film that insulates the gate line WL, and is a CVD oxide film (Si_ThreeN
_FourFilm or SiO_TwoMembrane). 6 shows impurity ions in the poly-Si film.
This is an electrode formed by doping the capacitor,
The storage electrode to be formed. 7 is SiO_TwoFilm and Si_ThreeN_FourInsulation of film etc.
It is a dielectric film formed by a film. 8 is not applicable to the poly-Si film
An electrode formed by doping pure ions.
The counter electrode constituting the quantity C. 9 insulates the counter electrode 8
And a PSG film or the like. 10 is a bit line
BL contact hole. [0005] WL is formed of a poly-Si film or the like.
It is a gate electrode of the transfer transistor T and a word line.
You. BL is a poly-Si film doped with an impurity or a poly-Si film.
This is a bit line formed by a side film. As above
According to the simple structure, the degree of integration of the semiconductor memory device increases and
With the miniaturization of conductor elements, DRAM memory cells
The area is getting smaller and smaller, causing the following problems:
You. (1) Storage capacitance C of memory cell depending on storage electrode area
Is reduced. (2) Due to the decrease in the storage capacitance C, the incidence of α rays
Soft errors increase. (3) High aspect ratio of bit line and contact hole
This makes pattern formation difficult. To solve such a problem, a bit line is used.
DRAM cell with storage electrode formed on insulating film covering
For example, [1] JP-A-59-231851, [2] JP-A-62-14
No. 5765. In gazette [1], the second
As shown in the figure, a plurality of active areas arranged in one word line direction
The areas are arranged in a row such that their edges are aligned in a straight line.
Bit line contact and storage for the active region
The electrode contacts are each connected to one straight line parallel to the bit line.
It is formed so that it does not exist on the line and is active
The bit line that passes between the regions has the protrusion
Contact with the department. In the publication [2], as shown in FIG.
Bit line contact and storage electrode contact for conductive region
Are on one straight line, each parallel to the bit line.
Are positioned so that there is no
The cut line passes. In this publication, the active region
There is no clear description about the planar arrangement relationship of. these
The bit lines described in the publications [1] and [2] of FIG.
It extends linearly except for the contact part. Moreover, each other
The bit line adjacent to the transistor and the impurity
The contact part with the diffused layer is lined up in the word line direction.
I have. [0007] By the way, the size of the memory is large.
As the capacity increases and the degree of integration increases, the bit line spacing becomes
It becomes even smaller. However, the above publications [1] and [2]
Memory cells, contact the bit lines and impurity diffusion layers.
In order to make the bit line
These multiple contacts are
Since they are formed linearly adjacent to each other, bit lines
And the pattern interval of the active area becomes narrow,
The risk of contact and form contact holes
There is no room to do so and the yield decreases. Also,
Even if a short circuit does not occur, the spacing between bit lines is narrow
In addition, the signal interference between bit lines increases,
When the potential change is transmitted to the adjacent bit line,
Causes a malfunction in reading the stored information from the memory cell.
I will. In contrast, if you increase the spacing between patterns,
Contrary to high integration due to increased memory cell area
become. Further, the bit line BL, the storage electrode and the active region
When forming a contact hole that connects
Since it is necessary to secure a margin for alignment, contact holes
Formation has hindered the improvement of the degree of integration. The present invention relates to
It was created in view of the problems of the conventional
Signal short circuit and signal interference between bit lines.
Semiconductor memory that can improve the degree of integration
It is an object of the present invention to provide a storage device and a manufacturing method thereof. [0009] The object of the present invention is as shown in FIG.
As illustrated in FIG.₁And the word line WL
₃, WL₄In response to the selection signal of the storage capacitor C₂Bit
Line BL₁Transfer transistor T electrically connected to₁When
A semiconductor memory device having a plurality of memory cells including
And the storage capacity C₁Is the storage electrode 20a and the storage electrode
Counter electrode formed on pole 20a via dielectric film 21
22 and the bit line BL₁Is the storage electrode 20
a is formed in a layer below the layer forming
Transistor T₁Are transfer transistors adjacent in the bit line direction.
Jista T₁A first impurity diffusion layer 14 shared with
Second impurity diffusion layer electrically connected to storage electrode 20a
13 and the bit line BL₁Is the first impurity
It has an overhang for electrical connection with the
Word line WL₃, WL₄Is the bit line BL₁Intersect with
The first impurity diffusion layer 14 and the second impurity diffusion layer
13 and the pair of bit lines BL₁
With respect to one of the bit lines BL₁And corresponding
The first connection position 16 with the first impurity diffusion layer 14 is
Bit line BL₁And the corresponding first impurity
From the second connection position 16 with the material diffusion layer 14 in the bit line direction.
Are shifted, and between the first and second connection positions, two
The word line WL₃, WL₄The transfer to be located
Transistor T₁Is characterized by being arranged
Solved by conductor storage. The object of the present invention is illustrated in FIGS.
So that the storage capacity C₂And the word line WL₃, WL₄
In response to the selection signal of the storage capacitor C₂To the bit line BL
₂₁, BL₂₂Transfer transistor T electrically connected to
₂Semiconductor memory device provided with a plurality of memory cells including
The storage capacity C₂Represents the storage electrode 20a and the storage electrode 20a.
The counter electrode formed on the electrode 20a via the dielectric film 21
Pole 22 and the bit line BL₂₁, BL₂₂Is before
It is formed in a layer below the layer forming the storage electrode 20a.
And the transfer transistor T₂Are adjacent in the bit line direction
The transfer transistor T₂The first impurity expansion shared with
The diffusion layer 14 is electrically connected to the storage electrode 20a.
A second impurity diffusion layer 13, wherein the first impurity diffusion layer
14 is the bit line BL₂₁, BL₂₂Electrical connection with
For the word line WL₃, WL
₄Is the bit line BL₂₁, BL₂₂Intersect with the said
Extending between the first impurity diffusion layer 14 and the second impurity diffusion layer 13
And the paired bit lines BL₂₁, BL₂₂To
With respect to one of the bit lines BL₂₁And corresponding
The first connection position 16a with the first impurity diffusion layer 14 is
The other bit line BL₂₂And the corresponding first
The bit from the second connection position 16a with the impurity diffusion layer 16a
The first and second connection positions 16a
Between the two word lines WL₃, WL₄Is located
As described above, the transfer transistor T₂Is placed
The problem is solved by a semiconductor memory device characterized by the following. FIG. 8 shows an example of the semiconductor memory device.
The counter electrode (47) is connected to the storage electrode.
(46) formed so as to face the upper surface, the side surface, and the lower surface.
It is characterized by having been done. In the semiconductor memory device, the word
Line WL₃, WL₄Is the transfer transistor T₁, T₂
It is characterized in that it is bent at the formation position of. The semiconductor
In the storage device, the storage electrode 20a is connected to the word
Line WL₃, WL₄, The bit line BL₁, BL₂₁, B
L₂₂Formed of a conductive film thicker than any of
It is characterized by. FIG. 8 shows an example of the semiconductor memory device.
So that the storage electrode (45) is spaced from the storage electrode in the height direction.
And a plurality of conductive films extending in the horizontal direction.
It is characterized by that. In the semiconductor memory device, the field
The adjacent word line WL extending on the insulating film 12₄above
The storage electrodes 20a are formed so as to overlap.
It is characterized by having been done. [0015] The above-mentioned problems are shown in Figs.
As exemplified in FIG.₁And the word line W
L₃, WL₄In response to the selection signal of the storage capacitor C₁The
Line BL₁Transfer transistor T electrically connected to₁
Of a semiconductor memory device provided with a plurality of memory cells including
A transfer transistor adjacent in a bit line direction.
Star T₁A first impurity diffusion layer 14 shared by
Product electrode C₁Impurity diffusion layer 13 electrically connected to
The first impurity diffusion layer 14 or the bit line
BL₁Has an overhang for electrical connection between the two,
Bit line BL forming a pair₁With respect to one of the bit lines
BL₁And the first impurity diffusion layer 14 corresponding thereto.
The first connection position is the other bit line BL₁And it
From the corresponding second connection position with the first impurity diffusion layer 14
The first and second connections are displaced in the bit line direction and
Between the two word lines WL₃, WL₄Is located
So that the transfer transistor T₁To form multiple
And the transfer transistor T₁First insulating film 15 covering
And forming the bit on the first insulating film 15.
Line BL₁Forming the bit line BL₁Cover
Forming a second insulating film 18;
Forming a storage electrode 20 thereon;
Counter electrode C covering the storage electrode 22₁Work to form
And a method for manufacturing a semiconductor memory device.
To solve. In the method for manufacturing a semiconductor memory device,
As illustrated in FIG. 8 and FIG.
a) forming a gap underneath;
The method is characterized in that the counter electrode (47) is formed. In the method for manufacturing a semiconductor memory device,
Forming the storage electrode (45) with a plurality of conductor films;
It is characterized by. [0018] [0019] According to the present invention, two adjacent pixels in the bit line direction can be used.
One transfer transistor connected to one bit line
To the shared first impurity diffusion layer and a separate storage electrode
An electrically non-shared second impurity diffusion layer;
And one bit in a pair of bit lines
The first connection position between the line and the first impurity diffusion layer and the other via
And a second connection position between the bit line and another first impurity diffusion layer.
The first connection position and the second connection position are shifted from each other in the bit line direction.
So that two word lines exist between the connection positions
Transfer transistor, and the storage
The bit line is formed at a position that can be covered by the pole. According to such a structure, the interval between the bit lines
The bit line below the storage electrode even when the width becomes narrower
Further enhances the shielding effect and prevents bit line interference
Is done. In addition, the bit line and the storage electrode contact
To prevent contact, change the bit line formation position to the word line direction.
And the bit line contact portion is moved from the active region.
Changing the basic position of the active area even if it overhangs
Without overhanging the two transfer channels in the bit line direction.
Can be arranged in the element isolation region between transistors
Therefore, without increasing the bit line spacing,
Integration between transfer transistors can be narrowed to improve integration
I do. Further, the storage electrode is formed on the field insulating film by a wire.
Over the lead wire, or on the lower surface of the storage electrode.
Form a counter electrode or connect storage electrodes to word lines and bit lines.
Thicker or multiple storage electrodes
By forming from a conductive film, the storage capacity is increased.
You. Further, for example, avoid bit line contacts
When the word line is bent, the transfer transistor
The degree of freedom is improved, which contributes to the improvement of integration. [0022] [0023] An embodiment of the present invention will now be described with reference to the drawings.
Will be described. FIGS. 1 and 2 show a first embodiment of the present invention.
FIG. 2 shows a structural diagram of a first DRAM cell according to the example of FIG.
You. FIG. 1 is a plan view of a first DRAM cell, and FIG.
1 is a sectional view taken along the line AA ′, and FIG. 2B is a sectional view taken along the line BB ′ in FIG.
FIG. In the figure, reference numeral 11 denotes an epitaxial layer or the like.
Si substrate, 12 is a field oxide that has been selectively LOCOS oxidized
Membranes 13, 14 are As⁺Thermal diffusion of impurities such as ions
The impurity diffusion layer to be formed is a transfer transistor T₁
Source and drain. WL_Three, WL_FourIs a poly-Si film
Is a gate electrode formed by
Also serves as a word line. The broken line in FIG. 1 is impure
The material diffusion layers 13 and 14 are shown. Reference numeral 15 denotes a gate electrode WL_Three, WL_FourInsulate
Insulating film such as a gate oxide film_ThreeN_FourFilm, SiO_TwoOn the membrane
Formed. BL₁Is a bit line and contains impurities.
It is formed by a poly-Si film 17 and a polycide film.
18 is a bit line BL₁SiO insulating_TwoIt is a membrane. These
Transfer transistor T₁Is configured. Also 20a
Is a poly-Si film containing impurities according to the desired film thickness.
The storage electrode to be formed. Reference numeral 21 denotes a dielectric film,
It is formed by heat-treating the product electrode 20a. Reference numeral 22 denotes a poly-Si film containing impurities.
And the storage electrode 20a
Storage capacitance C together with body film 21₁To form Also, in FIG.
Where 16 is the bit line BL₁Contact hole
You. As shown in FIGS. 1 and 2, the transfer transistor T₁But
The region to be formed (hereinafter referred to as an active region) is a bit line B
L₁And the word line WL_Three, WL
_FourDirection (bit line BL₁In the direction in which
The active regions that exist in the direction of
WL_Three, WL_FourAlternately to the left and right with respect to the extension direction of
Are arranged in a zigzag. Also each word
Line WL_Three, WL_FourAre arranged in the word line extending direction.
So that it passes through the inside of the active region and near the side in order
The gate electrode and the gate electrode pass through the active region.
Function. In other words, the word line is formed by a transfer transistor.
The first intersection formed and the absence of a transfer transistor
It will pass through the second intersection in order. Further, word line WL_Three, WL_FourIs a bit
Line BL₁Contact and accumulation with the impurity diffusion layer 14
Bypasses the contact between the electrode 20a and the impurity diffusion layer 13.
It is bent to rotate. This allows the same
The spacing in the bit line direction becomes narrower, and the active area becomes zigzag.
Of semiconductor memory devices when placed in
Is controlled. Part where bit line contacts impurity diffusion layer
Min does not exist linearly with respect to the direction in which the word lines extend.
Therefore, the distance between bit line contacts and bit lines is large.
Short circuit and bit signal voltage interference are prevented.
The yield at the time of manufacturing the conductive memory device is also improved. Its interference
Is suppressed, a read malfunction is prevented. Bit line BL₁Are the impurity diffusion layers 13 and 1
4 and in the impurity diffusion layers 13 and 14
It is protruding. Also, the bit line BL₁Is the next bit line B
L₁Having a bend away from the projecting portion of the
Minute is bit line BL₁Activities arranged in the direction of extension
Located between the areas. Therefore, the bit line BL₁Butt
Output part and adjacent bit line BL₁Between the bent part of the and the active area
The interval is the word line WL_Three, WL_FourIn the direction of extension
It is in a state of being out of order. Thereby, the bit line BL₁of
Contact part and adjacent bit line BL₁Is enough
, So that the adjacent bit lines BL₁Trust between
Signal interference is prevented. Moreover, the bit line BL₁Bending of
Since the part is located between the active regions, the word line extension
The distance between the active regions in the direction is the bit line BL₁Can be placed large
It is enough if the bit line BL₁At the bend of
Therefore, the degree of integration of the semiconductor memory device does not decrease. Particularly, in this embodiment, the extension of the bit line
Bit line contacts and storage electrode contacts
Since it is on the line, the bit line
The effect of preventing them from approaching each other is great. Circuit with the above structure
Specifically, one word line WL_Three, WL_FourAre the same
Bit line BL connected to transmission transistor₁And different transfer
Bit line BL connected to transistor₁Intersect alternately with
Will be. Thus, a first DRAM cell is formed.
It is. The method of manufacturing the DRAM cell will be described later.
You. (Description of Apparatus of Second Embodiment) FIGS. 3 and 4 show a second embodiment of the present invention.
FIG. 3 is a structural diagram of a DRAM cell according to the third embodiment, and FIG.
4 (a) and 4 (b) are sectional views thereof. In the figure, T_TwoIs the transfer transistor, C
_TwoIs the storage capacity, and the same reference numerals as in the first embodiment denote the same devices.
Has ability. 16a and 16b are bit lines BL
_{twenty one}, BL_{twenty two}Contact hole of the first embodiment and
The difference is the bit line BL_{twenty one}, BL_{twenty two}Contact Ho
This is the point that the positions of the tools 16a, 16b and the like are shifted. Sand
The contact between the bit line and the storage electrode
Bit line BL since it is not on a straight line in the extension direction of the bit line BL._{twenty one}
Contact hole 16a and another bit line BL_{twenty two}Between
Separation line, BL_{twenty two}Contact hole 16b and other vias
Line BL_{twenty three}Is wider than in the first embodiment.
Accordingly, the occurrence of bit signal interference is better than that in the first embodiment.
And the dielectric breakdown voltage is improved. What
The method of forming the transfer transistor is different from that of the first embodiment.
Jista T_TwoThe impurity diffusion layer 14 for the source may be expanded.
When forming contact holes 16a, 16b, etc.
By changing the resist pattern of
The forming process is performed in the same manner as in the first embodiment. (Description of Apparatus of Third Embodiment) FIGS.
FIG. 9 is a structural diagram of a DRAM cell according to a third embodiment of the present invention.
FIG. 5 is a plan view, and FIG. 6 (a) is an AA 'arrow of FIG.
FIG. 6B is a sectional view taken along the line BB ′ in FIG.
It is. In the figure, T_ThreeIs the transfer transistor, C_ThreeIs
The storage capacity is the same as in the first embodiment.
Has a function. 25a is a storage electrode, 26 is an induction electrode.
The conductor film 27 is a counter electrode. In addition, it differs from the first embodiment.
Is to connect the drain 13 and the storage electrode 25a.
Openings 24 for contact holes for bit lines (not shown).
Is insulating film 15 and SiO_TwoThe films 18 and 23 are different from each other by RIE or the like.
In that it is formed in a self-aligned manner by isotropic etching
is there. Thereby, the bit line BL₁And the storage electrode 25a
Reduce the margin when forming contact holes
, So that high integration can be achieved. in this case,
As described in the first embodiment, the bit line BL₁Is that
The bit line BL next to the song₁Sufficient distance from the protrusion
To increase the distance between bit lines.
Can prevent bit signal voltage interference and increase dielectric strength
It is possible to do. (Description of Apparatus of Fourth Embodiment) FIGS.
FIG. 13 is a structural diagram of a DRAM cell according to a fourth embodiment of the present invention.
You. FIG. 7 is a plan view thereof, and FIG. 8A is an AA ′ arrow of FIG.
FIG. 8B is a sectional view taken along line BB ′ of FIG. 7.
FIG. This embodiment is different from the first embodiment in that
The storage electrode that forms the capacitor has a cross-sectional tree structure (fin structure)
It is a point which has. That is, in the figure, 31 is d
Si substrate, such as a epitaxial layer, 32 is selectively LOCOS oxidized
Field oxide films, 33 and 34 are As⁺Ion
An impurity diffusion layer formed by thermal diffusion of a pure substance.
Transistor T_FourSource and drain. WL_Five,
WL₆Is a transfer transistor formed of a poly-Si film, etc.
T_FourFrom the word line of the DRAM cell
Be composed. 35 is a gate electrode WL_Five, WL₆Acid covering
An insulating film such as an oxide film_ThreeN_FourFilm or SiO_TwoFormed by the film
It is. BL_FourIs a bit line and contains impurity ions.
It is formed of a poly-Si film 37 or a polycide film. 38
Is the bit line BL_FourSi insulating_ThreeN_FourIt is a membrane. To these
Transfer transistor T_FourIs configured. 45a is
Bit line BL_FourSi insulating_ThreeN_FourAccumulation formed on the membrane
Electrode, formed by poly-Si film containing impurity ions
It has a cross-sectional dendrite structure formed. 46 is a dielectric film
And formed by heat-treating the storage electrode 45a.
You. 47 is a poly-Si film containing impurity ions.
A storage electrode 45a and a dielectric
Storage capacitance C together with film 46_FourTo form Thus, a fourth DRAM cell is constructed.
That the storage electrode 45a has a cross-sectional dendritic structure
As a result, the area of the storage electrode can be increased. This allows
Product capacity C_FourCan be several times larger than before.
Become. Next, a method of manufacturing the above-described DRAM cell will be described.
explain. (Explanation of Method for Manufacturing Apparatus According to First Embodiment) FIGS. 9 to 1
1 is a process for forming a DRAM cell according to a first embodiment of the present invention.
FIG. 9 (A) to 9 (C), FIG. 10 (A),
11 (B) and FIG. 11 (A) show the AA of the DRAM cell of FIG.
FIG. 9 (a) to 9 (c), FIG.
0 (a), (b) and FIG. 11 (a) show the DRAM cell of FIG.
It is a formation process figure of the BB 'section of a nozzle. In the figure, first, a D-type epitaxial layer, etc.
Is thermally oxidized on the Si substrate 11 by a selective LOCOS method or the like, and
Forming a second oxide film 12 and further forming a desired As⁺ion
And the like are implanted into the Si substrate 11. Then heat
Make sense, n⁺The impurity diffusion layers 13 and 14 are formed. Note that
n⁺The impurity diffusion layers 13 and 14 are ₁
Source and drain. Further, an unillustrated pattern formed by the selective locos method or the like is used.
The indicated SiO_TwoThe polysilicon (Si) film through the film (gate oxide film)
Gate electrode WL_Three, WL_FourTo form The gate electrode W
L_Three, WL_FourIs the word line in the DRAM cell
(FIGS. 9A and 9A). Next, the gate electrode WL_Three,
WL_FourTo a thickness of about 1000 mm of SiO_TwoInsulated by film 15
SiO with the resist film shown as a mask_TwoRIE etc. for the film 15
To form openings 16 by anisotropic etching of
You. The opening 16 serves as a contact hole for the bit line.
You. The etching gas used for anisotropic etching is
CF_Four/ O _Two(FIGS. 9B and 9B). Further, the Si substrate 11 provided with the opening 16
The entire surface is doped with impurity ion
A Si film 17 is formed by a low pressure CVD method or the like, and a resist (not shown) is formed.
Patterning by RIE method using the strike film as a mask
(FIGS. 9C and 9C). Next, the patterned
SiO 2 is used as an insulating film 18 on the entire surface of the Si film 17._TwoFilm and Si_ThreeN _Four
A film is formed, and then a resist film (not shown) is used as a mask.
And the insulating film 18 and SiO_TwoThe film 15 is opened, and the opening 19 is formed.
Provide. The opening 19 is provided in the contact hole of the storage electrode.
(FIGS. 10A and 10A). Next, the entirety of the Si substrate 11 provided with the openings 19
A poly-Si film 20 containing impurities with a desired thickness on the surface
Then, using a resist film (not shown) as a mask,
The re-Si film 20 is patterned by anisotropic etching such as RIE.
To synchronize. In addition, patterning the poly-Si film 20
To form the storage electrode 20a. Also etching gas
Is CCl_Four/ O_Two(FIGS. 10B and 10B). Further, the storage electrode 20a is heat-treated to
O_TwoA dielectric film 21 such as a film is formed (FIG. 10C,
(C)). It should be noted that after the formation process of FIGS.
Represents a counter electrode 22 (not shown)
An ion-containing poly-Si film is formed on the entire surface of the dielectric film 21.
As a result, the first DR as shown in FIGS.
AM cells can be manufactured. (Theory of the Manufacturing Method According to the Device of the Third Embodiment)
FIG. 12 to FIG. 14 show the D according to the third embodiment of the present invention.
FIG. 4 is a process chart of forming a RAM cell. FIG.
(C), FIGS. 13 (A), (B), FIGS. 14 (A), (B)
FIG. 9 is a process chart of forming a section AA ′ of the DRAM cell in FIG. 5;
is there. 12 (a) to 12 (c), FIGS. 13 (a) and 13 (b),
FIGS. 11A and 11B show BB of the DRAM cell of FIG.
FIG. FIGS. 12A and 12B and FIGS. 12A and 12B
The forming process according to the first embodiment shown in FIG.
9A, 9B and 9A, 9B
The description is omitted because it is the same as the formation process. Following these
And SiO_TwoWith the opening 16 provided in the film 15, SiO 2_TwoMembrane 1
5 and the entire surface on the Si substrate 11 exposed from the opening 16
Poly-Si film 17 or silicide film containing impurities in Si and Si
O_TwoThe film 18 is formed by a low pressure CVD method (FIG. 12).
(C), (c)). Next, a resist film (not shown) is used as a mask.
Then, the poly-Si film 17 is anisotropically etched by RIE or the like.
Patterned bit line BL_ThreeTo form At this time
SiO_TwoSimultaneous patterning of the film 18 on the poly-Si film 17
(FIGS. 13A and 13A). Furthermore, poly-Si film 17
About 1000 膜厚 thickness on the entire surface of the Si substrate 11
SiO_TwoThe film 23 is formed by a CVD method or the like (FIG. 13)
(B), (b)). Next, the transfer transistor T_ThreeCash register in part
The contact film for the storage electrode 25a is
The opening 24 is formed by anisotropic etching such as RIE.
(FIGS. 14A and 14A). The opening 24 is self-
It can be formed in a consistent manner. That is, D of the third embodiment
As already described in the structure of the RAM, the insulating film 15 and the SiO 2_Twofilm
When anisotropic etching such as RIE is performed on
Line BL_ThreeImpurity expansion with the insulating film left on the top and sides
An opening 24 is formed on the scattering layer 13. The opening is
Line BL_ThreeIs defined by the insulating film remaining on the side of the. Further, similarly to the first embodiment, the opening 24
PolySi film 25 having a desired thickness is formed on the entire surface of Si substrate 11 provided with
Is formed by a low pressure CVD method or the like. After that, cash register not shown
The poly-Si film 25 is anisotropic, such as RIE, using the strike film as a mask.
Patterning is performed by etching. In addition, the poly-Si film 2
5 is in contact with the impurity diffusion layer 13 by patterning.
A storage electrode 25a is formed (FIG. 14B)
(B)). Subsequent formation steps are the same as before
25a is heat-treated to give SiO_TwoForm dielectric film 26 such as film
Further, the counter electrode 27 contains impurity ions.
The formed poly-Si film is formed on the entire surface of the dielectric film 26. This
The DRAM cell of the third embodiment as shown in FIGS.
Can be manufactured. (Explanation of Method for Manufacturing Apparatus of Fourth Embodiment) FIGS.
Is a process for forming a DRAM cell according to the fourth embodiment of the present invention.
FIG. 15 (A) to 15 (C) and FIGS.
Each of (A) and (B) of FIG. 18 corresponds to the DRAM cell shown in FIG.
FIG. 15 is a process chart related to the formation of a cross section taken along the line AA ′ in FIG.
(A) to (c) and (a) and (b) in FIGS.
FIG. 4 is a process diagram of forming a cross section taken along the line BB ′. In the figure, first, as in the first embodiment,
Selective LOCOS method for Si substrate 31 such as P-type epitaxial layer
Thermal oxidation to form a field oxide film 32,
And the desired As⁺Impurity ions such as ions are transferred to the Si substrate 31.
Inject into After that, heat treatment is performed, and n⁺Impurity diffusion layer 3
3, 34 are formed. Note that n⁺Impurity diffusion layer 33,
34 is a transfer transistor T_FourSource and drain
You. Further, not shown SiO 2_TwoFilm (gate oxide film)
Through the gate electrode WL with a poly-Si film or the like._Five, WL₆
To form Note that the gate electrode WL_Five, WL₆Is DRA
It becomes a word line in the M cell (FIG. 15A,
(A)). Next, the gate electrode WL_Five, WL₆The film thickness 10
About 00Å SiO_TwoFilm or Si_ThreeN_FourIsolation by insulating film 35 such as film
The insulating film 35 is formed using the resist film (not shown) as a mask.
An opening is formed by anisotropic etching such as RIE, and an opening 36 is formed.
To form The opening 36 is a bit line contact.
It becomes a hall. Also, the edge used for anisotropic etching
Ching gas is CF_Four/ O_Two(FIG. 15B)
(B)). Further, the Si substrate 31 provided with the opening 36 is
Poly Si containing impurity ions with a thickness of about 1000 mm on the entire surface
A film 37 is formed by a low pressure CVD method or the like, and a resist (not shown) is formed.
Patterning by RIE or the like using the film as a mask
(FIGS. 15C and 15C). Next, in this embodiment,
A film thickness of about 1000 mm on the entire surface of the
Si as thermal oxidation insulating film_ThreeN_FourA film 38 is formed (FIG. 16)
(A), (a)). Next, the Si_ThreeN_FourSi substrate 31 on which film 38 is formed
Over the entire surface of_TwoImpurity of the same thickness as film 39
Poly-Si films 40 containing oxide ions are sequentially laminated,
SiO of the same thickness_TwoFilm 40 and poly-Si film containing impurity ions
42 and a top layer of SiO_TwoA film 43 is formed. What
Contact, SiO_TwoFilm and a poly-Si film containing impurity ions
The forming step is repeated N times as desired (FIG. 16).
(B), (b)). Next, a resist film (not shown) is used as a mask.
And selectively stack N + 1 times of SiO_TwoThe film was laminated N times
Poly-Si film and Si_ThreeN_FourThe film 38 and the insulating film 35 are formed by RIE.
The opening 4 is removed by anisotropic etching.
4 is formed. The etching gas is SiO_TwoFilm, Si_ThreeN_Four
CF to film_Four/ O_Two, CCl for poly-Si film_Four/
O_Two(FIGS. 17A and 17A). Further, an SiO having an opening 44_TwoAll of the film 43
A poly-Si film 45 containing an impurity with a thickness of about 1000 mm
It is formed by a low pressure CVD method or the like (FIG. 17B,
(B)). Then, using a resist film (not shown) as a mask
Poly-Si films 45, 42, 40 and SiO_TwoMembranes 43, 41, 39
Is patterned by anisotropic etching such as RIE
(FIGS. 18A and 18A). Next, isotropic etching of HF (hydrofluoric acid) or the like
By patterning SiO_TwoThe entire surface of the films 43 and 41
Then, the storage electrode 45a is formed. Note that the bit line BL
_FourForming a poly-Si film 37 and a gate electrode WL_Five, WL₆
Si to insulate_ThreeN_FourEven if the film 38 is exposed to the HF solution,
Is not performed. The storage electrode 45a has a dendritic structure in cross section.
(FIGS. 18B and 18B). In addition, SiO_TwoMembrane 39 omitted
It does not matter. After the formation steps of FIGS. 18B and 18B,
Heat-treats the storage electrode 45a as before,_TwoMembrane, etc.
Dielectric film 46 is formed, and then the
To form a poly-Si film containing pure ions on the entire surface
Do more. As a result, the transfer traffic as shown in FIGS.
Transistor T_FourAnd storage capacity C_FourDR of the fourth embodiment having
AM cells can be manufactured. (Summary of Manufacturing Method) As described above, the storage electrode 20
a, 25a and 45a are the bit lines BL previously formed.₁,
BL_Two, BL_ThreeAnd BL_FourInsulating films 18 and 23 for insulating
And 38. Thereby, the storage electrode 20
a, 25a and 45a are formed three-dimensionally,
L₁, BL_Two, BL_ThreeAnd BL_FourOf the contact hole
The aspect ratio can be reduced. further,
The storage electrodes 20a and 25a have a three-dimensional laminated structure,
5a has a cross-sectional dendritic structure to reduce the area of the storage electrode.
And therefore the storage capacity C₁, C_Two, C_Three
And C_FourCan be increased several times compared to the past.
You. According to the third manufacturing method of the present invention,
Bit line BL formed in_ThreeRIE of insulating films 18 and 23
Opening in a self-aligned manner by anisotropic etching such as
Align the electrode contact hole with the part 24
It becomes possible. Further adjacent bit line BL_{twenty one}And B
L_{twenty two}And BL_{twenty two}And BL_{twenty three}Widening separation between comrades
Therefore, the withstand voltage can be improved. According to the fourth manufacturing method of the present invention,
SiO_TwoFilms 39, 41, 43 and poly containing impurity ions
Continue the process of forming the Si films 40, 42 and 45 into two layers N times
And the N times continuous SiO_TwoThe membranes 39, 41, 43 and the
The poly-Si films 40, 42 and 45 are patterned and
SiO which continued N times later_TwoOnly membranes 39, 41, 43 are isotropic
Of cross section dendritic structure by removal by reactive etching
The storage electrode 45a can be formed. [0056] As described above, according to the present invention, the bit
In two transfer transistors adjacent in the direction of the scanning line,
First impurity diffusion layer connected to and shared by one bit line
And a non-shared second electrically connected to separate storage electrodes.
It has an impurity diffusion layer and is connected to a pair of bit lines.
And a first contact between one of the bit lines and the first impurity diffusion layer.
Between the second bit line and another first impurity diffusion layer.
The second connection position is shifted in the bit line direction from the second connection position.
Two word lines are connected between the first connection position and the second connection position.
Arrange transfer transistors so that they exist
Since the bit line was formed at a position that can be covered with the product electrode,
The storage electrode improves the effect of suppressing signal interference between bit lines.
Can be higher. Moreover, bit line and storage electrode contact
The bit line formation position to prevent contact with
In the direction of the gate line and activate the bit line contact area.
Basic layout of the active area even if it extends from the area
Of the overhang without changing the
It can be arranged in the element isolation region between the transfer transistors
Word line method without increasing the bit line spacing
The distance between transfer transistors in each direction can be reduced,
Can be improved. Further, the storage electrode is connected to a wire on the field insulating film.
Over the lead wire, or on the lower surface of the storage electrode.
Form a counter electrode or connect storage electrodes to word lines and bit lines.
Thicker or multiple storage electrodes
By forming from a conductive film, the storage capacity can be increased.
You. Further, for example, avoid bit line contacts
When the word line is bent, the transfer transistor
The degree of freedom can be improved and higher integration can be achieved. [0058]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a DRAM cell according to a first embodiment of the present invention. FIG. 2 is a sectional view of a DRAM cell according to the first embodiment of the present invention. FIG. 3 is a plan view of a DRAM cell according to a second embodiment of the present invention. FIG. 4 is a sectional view of a DRAM cell according to a second embodiment of the present invention. FIG. 5 is a plan view of a DRAM cell according to a third embodiment of the present invention. FIG. 6 is a sectional view of a DRAM cell according to a third embodiment of the present invention. FIG. 7 is a plan view of a DRAM cell according to a fourth embodiment of the present invention. FIG. 8 is a sectional view of a DRAM cell according to a fourth embodiment of the present invention. FIG. 9 is a sectional view (No. 1) showing a manufacturing step of the DRAM cell according to the first embodiment of the present invention; FIG. 10 is a sectional view (2) showing a step of manufacturing the DRAM cell according to the first embodiment of the present invention; FIG. 11 is a sectional view (No. 3) showing a step of manufacturing the DRAM cell according to the first embodiment of the present invention. FIG. 12 is a cross-sectional view (part 1) illustrating a process for manufacturing a DRAM cell according to the third embodiment of the present invention. FIG. 13 is a sectional view (2) showing a step of manufacturing a DRAM cell according to the third embodiment of the present invention; FIG. 14 is a cross-sectional view (part 3) illustrating a process for manufacturing a DRAM cell according to the third embodiment of the present invention. FIG. 15 is a cross-sectional view (part 1) illustrating a process for manufacturing a DRAM cell according to the fourth embodiment of the present invention. FIG. 16 is a sectional view (2) showing a step of manufacturing a DRAM cell according to the fourth embodiment of the present invention. FIG. 17 is a sectional view (3) showing a step of manufacturing a DRAM cell according to the fourth embodiment of the present invention. FIG. 18 is a sectional view (part 4) illustrating a process for manufacturing the DRAM cell according to the fourth embodiment of the present invention. FIG. 19 shows an equivalent circuit of a DRAM cell and a DR according to a conventional example.
It is sectional drawing of an AM cell. [Description of Signs] T, T _{1 to} T ₄転 送 transfer transistors C _, C _{1 to} C ₄蓄積 storage capacitors 1 _, 11 _, 31 Si Si substrate (semiconductor substrate) 2 _, 12 _, 32 33 ... drain (impurity diffusion layer) 4,14,34 ... source (impurity diffusion layer) 15 ... Si ₃ N ₄ film or SiO ₂ film (insulating film) 6,20a, 25a, 45a ... storage electrode 7,21,26 , 46 ... dielectric film 8,22,27,47 ... counter electrode 9 ... PSG film 10 ... bit line contact holes 18,23,35,39,41,43 ... SiO ₂ film (insulating film) 38 ... Si ₃ N ₄ film (heat-resistant oxidizing insulating film) 17, 20, 25, 37, 40, 42, 45: poly-Si film (conductor film) 19, 24: opening (storage electrode contact portion) 16, 36: opening (Source contact portion) WL, WL _{1 to} WL ₆ … word line (gate _{Pole) BL, BL 1 ~BL 4,} BL 21 ~BL 23 ... bit lines

Claims (1)

(57) [Claims] A semiconductor memory device comprising: a plurality of memory cells each including a storage capacitor and a transfer transistor that electrically connects the storage capacitor to a bit line in response to a word line selection signal, wherein the storage capacitor includes a storage electrode And a counter electrode formed on the storage electrode via a dielectric film, wherein the bit line is formed of a layer below a layer forming the storage electrode, and the transfer transistor is arranged in a bit line direction. A first impurity diffusion layer shared with the adjacent transfer transistor and a second impurity diffusion layer electrically connected to the storage electrode, wherein the first impurity diffusion layer is electrically connected to the bit line. An overhanging portion for connection, wherein the word line intersects the bit line and extends between the first impurity diffusion layer and the second impurity diffusion layer; The bi A first connection position between the bit line and the corresponding first impurity diffusion layer is shifted in a bit line direction from a second connection position between the other bit line and the corresponding first impurity diffusion layer. And the transfer transistor is arranged such that the two word lines are located between the first and second connection positions. 2. 2. The semiconductor memory device according to claim 1, wherein said counter electrode is formed so as to face an upper surface, a side surface, and a lower surface of said storage electrode. 3. 2. The semiconductor memory device according to claim 1, wherein said word line is bent at a position where said transfer transistor is formed. 4. 2. The semiconductor memory device according to claim 1, wherein said storage electrode is formed of a conductive film thicker than any of said word line and said bit line. 5. 2. The semiconductor memory device according to claim 1, wherein said storage electrode comprises a plurality of conductive films each extending in a lateral direction at intervals in a height direction. 6. 2. The semiconductor memory device according to claim 1, wherein said storage electrode is formed so as to overlap said adjacent word line extending on a field insulating film. 7. A semiconductor memory device comprising: a plurality of memory cells each including a storage capacitor and a transfer transistor that electrically connects the storage capacitor to a bit line in response to a word line selection signal, wherein the storage capacitor includes a storage electrode And a counter electrode formed on the storage electrode via a dielectric film, wherein the bit line is formed of a layer below a layer forming the storage electrode, and the transfer transistor is arranged in a bit line direction. A first impurity diffusion layer shared with the transfer transistor adjacent thereto, and a second impurity diffusion layer electrically connected to the storage electrode, wherein the bit line is electrically connected to the first impurity diffusion layer. An overhanging portion for connection, wherein the word line intersects the bit line and extends between the first impurity diffusion layer and the second impurity diffusion layer; The bi A first connection position between the bit line and the corresponding first impurity diffusion layer is shifted in a bit line direction from a second connection position between the other bit line and the corresponding first impurity diffusion layer. And the transfer transistor is arranged such that the two word lines are located between the first and second connection positions. 8. 8. The semiconductor memory device according to claim 7, wherein said counter electrode is formed so as to face an upper surface, a side surface, and a lower surface of said storage electrode. 9. 8. The semiconductor memory device according to claim 7, wherein said word line is bent at a position where said transfer transistor is formed. 10. 8. The semiconductor memory device according to claim 7, wherein said storage electrode is formed of a conductive film thicker than any of said word line and said bit line. 11. 8. The semiconductor memory device according to claim 7, wherein said storage electrode is formed of a plurality of conductive films each extending in a horizontal direction at intervals in a height direction. 12. 8. The semiconductor memory device according to claim 7, wherein said storage electrode is formed so as to overlap on said adjacent word line extending on a field insulating film. 13. A method of manufacturing a semiconductor memory device including a plurality of memory cells each including a storage capacitor and a transfer transistor that electrically connects the storage capacitor to a bit line in response to a word line selection signal, the method comprising: A first impurity diffusion layer shared by the adjacent transfer transistors; and a second impurity diffusion layer electrically connected to the storage electrode, wherein the first impurity diffusion layer or the bit line is electrically connected to both. With respect to a pair of bit lines, a first connection position between one of the bit lines and the corresponding first impurity diffusion layer is provided with an overhanging portion for connection. The plurality of transfer transistors are displaced in the bit line direction from a second connection position with one impurity diffusion layer and two word lines are located between the first and second connection positions. Forming, forming a first insulating film covering the transfer transistor, forming the bit line on the first insulating film, and forming a second insulating film covering the bit line. Forming a storage electrode on the second insulating film; and forming a counter electrode covering the storage electrode via a dielectric film. 14． Forming a gap below the storage electrode,
14. The method according to claim 13, wherein the counter electrode is formed also in the gap. 15. 14. The method according to claim 13, wherein the storage electrode is formed of a plurality of conductor films.