JP2886858B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to integrated circuits, and more particularly to CMOS (phase-change memory).
(Complementary metal oxide semiconductor) integrated circuit. [Conventional technology]   In conventional bulk (integrated) CMOS devices,
One of the main limitations in miniaturizing devices is
In order to avoid switch-up. Here, "Latch up
“P” means P⁺Source / drain regions and N-type
Region, P-type well, and N^-Depends on mold source / drain area
Self-holding current flows through the PNPN-type thyristor
That means To avoid such latch-up
Contains P, which is many times the minimum dimension of the device.⁺Type
Region and N⁺Identifying the minimum separation between the mold area
is necessary. For example, for a 1 micron rule CMOS device
In case, P⁺Type region and N⁺Design of separation interval with mold area
Rules can be 5 microns or more
It is. Such a large separation interval is required for VLSI CMOS images.
This is a major constraint on surface utilization efficiency.   P⁺Type region and N⁺Need for separation distance from mold area
One of the methods suggested to reduce the condition is to use C
One or both of the two types of transistors that make up the MOS
Forming the active region in recrystallized polysilicon
There is a law. However, such devices are reproducible
It is very difficult to manufacture with
Manufacturing requires a number of non-standard difficulties and
Carrier mobility in the tunnel region is not constant
There's a problem.   In developing CMOS devices, the integration density and operating speed
Another third criterion is single event disruption (SEU = Singl
e Event Upset). Sand
That is, an integrated circuit is constantly emitting a certain amount of background radiation.
Exposure to the line level, and as circuit miniaturization progresses,
Many conventional processes are suspended by alpha particles
Be more susceptible to careers. Thus silicon substrate
Alpha particles that hit the surface typically have multiple electron-holes
Open the pair, and so once that happens
When it is generated, it becomes near the source / drain junction of the active device.
The electric field at the connection point of the circuit
It is possible that enough charge will be collected to cause the
It is. In this way, a one-shot event disruption
There is a possibility that an electrical error will be introduced. [Problems to be solved by the invention] Purpose of the invention   The present invention provides a novel device structure and a manufacturing method thereof.
Provided by conventional technology.
It tries to meet the requirements that have not been met. Especially
Ming has a high operating speed, low leakage current, and
Are resistant to severe single event disruptions, and⁺Type
Area and N⁺Separation space between the mold area was possible
Provide CMOS devices that can be narrower
It is something.   Thus, the present invention relates to a crystalline channel region and an oxide.
More completely isolated source and drain regions
To provide an insulated gate field effect transistor having
It is. The source / dose separated by these oxides
The first step in forming the “lane” region is in silicon.
A recess is formed by etching in the
After the recess is covered with oxide, it is
Fill. Then a short isotropic etch was performed.
After that, a filament portion of polysilicon is deposited and further formed.
In the active device, the source separated by oxide
Between the source / drain area and the channel area
Make contact. Note that the sidewall nitride filaments are placed on the gate region.
Forming the silicon etching process automatically
A self-alignment process is also possible.   The impurities in the “source / drain” area are
Micro-region in contact with crystalline silicon near the tunnel region
Diffuses outward through the
These diffusion regions are electrically connected to the source / drain area.
It will work as an area.   The terms used in the following description are explained briefly.
I will clarify. That is, first, in the embodiment described in the present invention,
Self-aligned with the gate region (almost)
The heavily doped region surrounded by the transistor structure (particularly
(Horizontal view of transistor)
Has almost the same status as the source / drain area of the device.
Therefore, this structure is especially
Named "source / drain" area in brackets
And However, this “source / drain” area is electrically
Oxide rather than effective source / drain region
Majority carriers from the heavily doped region
It cannot be injected directly into the tunnel region. here
The electrically effective source / drain region is an oxide
Heavily doped polysilicon regions separated by
In the micro-region adjacent to the crystalline silicon near the channel region
Is a relatively small diffusion region formed by outward diffusion of
And In the following description, data according to the present invention will be described.
New "source / drain" structure for vice
For the sake of clarity, the source / drain
The contact area is called
However, these source / drain contact areas are simply
In addition to functioning as a contact, conductive diffusion
It serves other purposes, such as composition. In addition,
Electrical connection to these source / drain contact areas
The contact is the field of the source / drain region of the conventional MOS device.
It is performed in the same way as the case.   Thus, in the device according to the invention, P⁺Type region and
N⁺The true separation distance from the mold area is adjacent to each other and
Determined by the shortest distance between invaded source / drain regions
The channel area of one transistor
Small P at the edge of the region⁺P invaded from the diffusion region⁺
Field acid below source / drain contact area
N in the lower part of the oxide layer⁺Mold source / drain area
At the edge of the channel region of the NMOS device
The minimum distance along the road leading to the small N-type outward diffusion area
It will be determined more. This thing
Chi, P⁺Type region and N⁺The effective separation interval between the
Much more visible than the layout of the road
It is nothing but bigger. Fact, book
In an integrated circuit according to the invention, P⁺−N⁺The separation area is
Can be exceptional as a separate design rule
Is even.   Furthermore, an advantage of the present invention is that a single event disturbance state change can be achieved.
Is to resist. That is, according to the present invention,
In some devices, the source / drain junction is almost complete.
Collects charges because they are completely separated by oxides
Area per device that can be
It is extremely small compared to. Do not do this
That is, a position free enough for the generated charges to be collected
And disrupt the state at the electrical connection point.
That the absorption of a single particle is substantially less
That is.   Further, the advantage of the present invention is that good control of carrier mobility is achieved.
Is possible. That is, many
SOI (silicon-on-insulator) devices
In the fabrication technology, the deposited and annealed silicon
Which forms the channel region of the active device
As a result, the carrier mobility is low as a result.
Or it lacks reproducibility. Such conventional production techniques
Unlike the art, the channel in the device according to the invention
Is formed by a growth method, and is used for high-concentration ion implantation.
In bulk silicon that has never been exposed to damage due to
And therefore the carrier mobility is high,
Is the defect density of crystalline silicon grown low?
However, while utilizing many of the various advantages of SOI devices,
In addition, good transistor characteristics unique to the present invention can be obtained.
The Rukoto.   The present invention further provides an electrically active source / drain.
Of the sharp distribution curve of the impurity distribution curve at the junction
This is to provide a device with a static structure. But
However, these diffusion regions are not
Source / drain implanted impurities that remain
Compact (unlike diffused source region formed more)
Is it formed by outdiffusion from the source?
From a certain extended length (thermal
Determined by characteristics Is expressed by the integrated value of
Is larger than in the case of
As a result, an inclined drain effect is obtained. further
If desired, the source / drain of the device in the present invention.
Contact region and source / drain diffusion region
To achieve this, it is necessary to use a low concentration drain (LDD)
It may be performed in combination with the on-injection method.
If this is the case, the ion implantation process
Formation of contact parts and etching of silicon recesses
Make sure to do this before starting. Or, alternatively,
The source / drain contour of the device according to the invention
The source region and the source / drain diffusion region are formed in two types.
N-type impurities (eg, both phosphorus and arsenic)
This is done using a differential outward expansion.
It may be possible to obtain a gradient impurity concentration distribution due to scattering.
Yes. Thus, a further advantage of the present invention is that the series resistance is
Minimizing thermionic effect without introducing into the electrical properties of
It can be limited.   Further advantages of the present invention include source / drain contact
Extremely high concentration value strikes in the recess formed in the region.
That ion implantation for tip formation can be additionally performed
And thereby further improve the separation effect.
Becomes possible. The field separation in this case is isotropic
Not under source / drain contact area
The resulting parasitic or leakage current paths are
It is possible to control this more appropriately,
Such passages occurring in other directions are not controlled.
Gate line feeds from moat (active device area)
On the side of the gate region that crosses the gate isolation region,
Source / drain out-diffusion area is almost field-separated
Extending to the edge of the area, and
Parasitic or leakage current paths originating at the width of the
Preferably, as in the case of other leaking electrical paths, the additional
Not controlled by ON injection. On the contrary,
The improvement of the field separation effect simply depends on the tank area.
(That is, between the PMOS device region and the NMOS device region,
Not only between the moats (ie
NMOS device area and adjacent to these NMOS device areas
Between two NMOS device regions). Either
Even in the case of
Buried oxide layer is an extension of the field isolation region
Active diffusion region in silicon
The interval between
Will increase. Further, the lower part of the buried oxide layer
For extremely high concentration channel stop in silicon
By performing additional ion implantation,
Enhance the separation effect without causing problems
Is possible.   A preferred field separation scheme for use in the present invention is:
It is not necessary to use the LOCOS method (selective oxidation method).
R method (or SWAMI method = sidewall mask isolation method)
In addition, a field isolation region with almost vertical sidewalls
It is also possible to use various separation methods to form. Ma
In addition, the manufacturing process according to the present invention is referred to as a self-alignment process.
Source / drain separated by an oxide layer
Conductive ring surrounding the surface of the contact area
The source / drain contact
Area other than the edge of the active device channel area
In order to prevent electrical coupling with the substrate at
To form a high taper edge in the field separation region
It is preferred to use a separation technique without any. Thus, saw
The drain / drain contact region is near the channel region
Acid that makes it possible to contact silicon at room temperature
A nitride etch is performed on the source / drain contact region.
Contacts the silicon under the field oxide region
Do not go as deep as you can. like this
The restriction is that the field isolation method used is field oxide.
Slope with considerable steepness at the lateral interface between the region and silicon
Separation method that forms a surface (for example, the above-mentioned MFFFR method or S
The WAMI method, etc.)
May not be used, but other field separation methods
If used, take into account the above constraints
There is a need. The field separation technology used is limited.
At least slightly, it will form an indented field isolation region
Such as direct moat separation
Is substantially less preferred than the LOCOS method.   Further, the advantage of the present invention is that the above-mentioned latch-up tendency is reduced.
In doing so, the source / drain junction is almost completely
Effectively separated from substrate by oxide over area
Source / drain capacitor separated by oxide
The contact area borders the channel area
Small, electrically effective active source / drain regions
(Due to the lowering of the junction barrier due to charge injection)
The current regeneration function cannot occur. sand
In other words, this source / drain connection in the parasitic thyristor
If so, move further away from the other junctions in the thyristor.
Not only apart, but also smaller than the latter joint
To further reduce the current gain of the parasitic thyristor
This is especially favorable. Are these benefits another perspective?
In other words, the effective mote area (active device area)
Since the pattern given here is decreasing,
That it can reduce the tendency to
is there.   A further important advantage of the present invention is that short channel
The effect is that the effect is reduced. The device according to the invention
The junction depth that determines the short-channel effect is oxide
The source / drain contact area separated by
Of undercut used to combine with lux silicon
Degree and diffusion length of outdiffusion into the bulk silicon It is determined by the integral of. In the present invention, this diffusion
Typical for devices of otherwise equal depth
0.15 to 0.25 micron
It is possible to reduce to 0.1 microns
It is. In the present invention, the junction depth is thus reduced
Subthreshold leakage current and threshold voltage
Vt shift, reduced barrier due to drain, or
Various factors such as current multiplication and punch-through phenomena
It is possible to reduce the short channel effect. When
In particular, barrier reduction and punch-through due to drain
For elephants, minority carriers generated by impact ionization
Buried oxide layer
And the source / drain interface (electrically
Valid source / drain areas and source / drain ports
Field strength along most of the
To reduce the barrier and punch-through
The phenomenon will be significantly reduced. Further points of the present invention
Reduces sheet resistance in "source / drain" area
That is. That is, the present invention provides a source / drain
Tact region depth and channel region conductor
And the effective junction depth associated with
Is different from the conventional technology in that
. Thus, the sheet resistance of a thin film is defined as the resistivity ρ
It is equal to the value divided by the thickness of. In this case, silicon
Resistivity rises above a certain value by introducing impurities
It is impossible to make
The sheet resistance of the drain / drain diffusion region (silicide or self
No influence from self-aligned tungsten and other surface short-circuit layers
Increase the depth of the source / drain regions
Only with and can it be reduced. However
While increasing the depth of the source / drain regions
Has many side effects, and those side effects
Many of the effects are undesirable. Thus the above advantages
One way to make use of the
Source / drain contact area depth in normal CMOS
Source / drain by increasing
This is to reduce sheet resistance. Source / de
The lane contact area is implanted with a very high concentration of ions.
Doping to the saturation level
And this means that the resistance of these
Therefore, compared to a normal device of the same size,
That it is possible to make this much smaller
. This further increases the operating speed of the device.
And as an interconnect for the source / drain regions
It also means that the utility is improved.   The present invention envisions a CMOS device as one embodiment.
Although it is specified, the present invention calls this an NMOS device
May be used, or in some cases, applied to PMOS.
It is also possible.   Further, the advantage of the present invention is that
Gate area and silicidation process
And silicide surface of source / drain contact area
Or, if desired, peripheral wiring with titanium nitride.
That it can be formed.   In fact, the present invention forms silicidation and peripheral wiring
Can absorb impurities from silicon in processes, etc.
In particular, in connection with the process of forming a functional surface layer,
It is advantageous for (For example, this is a direct reaction TiSi_Two/ TiN
Potential for re-cide / peripheral interconnect formation process
Problem. ) When using this type of process,
In the future, absorption of such impurities (and silicidation
Source / drain diffusion area
The area becomes shallower, resulting in spikes (contact
Source to the underlying substrate), the more the source /
The drain diffusion region may be shallow. As above
Another potential problem with conventional processes is contact resistance.
This is a problem with anti-
If impurities in the drain region are excessively insufficient,
It is difficult to form ohmic contacts with low contact resistance.
It is. Yet another potential alternative to the above traditional process
The problem is the silicide corner closest to the gate area.
If an excessive voltage drop occurs in the
The production of thermoelectrons. In an embodiment of the present invention, the saw
Minimum lateral direction with equivalent depth of drain / drain contact area
Than the normal source / drain diffusion depth
Can be set to a much larger value.
Total amount of impurities implanted during the ion implantation step
Can be increased, which reduces the shortage of impurities.
It is possible to resist. In addition, the diffusion of polysilicon
Since its properties are much higher than that of crystalline silicon,
Impurities inside the source / drain contact area
Concentrations reach equilibrium more easily and therefore local impurities
It is also possible to prevent the contact resistance from increasing due to lack of. Or
Therefore, the present invention provides a process for forming a silicide or forming a peripheral wiring portion.
Possible to absorb impurities from silicon such as process
Spikes when used in conjunction with a process to form
Resistance to occurrence and specific contact resistance
And improved resistance to hot carrier effects
The benefit of doing so.   Further, the advantage of the present invention is that the source / drain region
Capacity is conventionally used (for given dimensions and depth)
Source / drain region
As a result, the parasitic capacitance is reduced as a result of the present invention.
Operation speed of circuits incorporating devices
In some cases.   In another embodiment of the invention, the separation by oxides
Source / drain contact area
This is made of metal material without using any
So that In this case, the concave insulated by the oxide layer
After the formation of the recess, the metal material (preferably,
On the source / drain core
Fill the surface of the contact recess. Next, the oxide layer
After the undercut, a conformal polysilicon
A saw separated by the oxide layer by forming a cone layer
Electrically connect the drain / drain contact area to the substrate.
They will be combined. [Means to solve the problem]   To achieve such an object, the present invention provides an insulated gate electrode.
A field effect transistor active device;
A substrate having a single-conductivity-type single-crystal semiconductor upper portion;
A plurality of active device regions surrounding the active device region;
Multiple field separation areas that define the area and multiple traffic
Wherein the plurality of transistors are each
a) a gate line that traverses the active device area
To define a transistor channel below the gate line
And insulated from the transistor channel
A gate line, b) provided on both sides of the gate line
A plurality of source / drain contact regions,
Each of the source / drain contact regions is
The substrate is indented and doped with impurities of the second conductivity type.
Semiconductor material portion, and provided below the semiconductor material portion.
Having a bent portion, and the semiconductor material portion and the substrate
A dielectric layer having an upwardly extending portion provided therebetween;
The dielectric material between the semiconductor material portion and the substrate;
A first portion provided on the upwardly extending portion of the body layer
The semiconductor material portion and the transistor chip.
A second portion provided on the substrate between the first and second channels.
Semiconductor connector in contact with the semiconductor material portion
The plurality of source / drain contacts comprising:
A plurality of transistors, the plurality of transistors,
One corresponding transistor channel
Multiple source extensions separated from each other by star channels
A diffusion region and a plurality of drain diffusion regions,
The source diffusion region and each of the drain diffusion regions are
One of the plurality of semiconductor connectors on the side opposite to the semiconductor material section.
Contacting the first and second parts and the second
The plurality of source extensions doped with impurities of a conductivity type of
A diffusion region and the plurality of drain diffusion regions.
An integrated circuit is provided. [Example]   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The working method and mode of use will be described. However, the present invention
The scope of use is wide, and
The examples are merely specific embodiments of practicing the invention.
It is not intended to limit the gist of the present invention.
Yes.   In the following description, a MOS device is described as an embodiment of the present invention.
The method of manufacturing the vice shall be described and the
The process flow used for cropping is the MFFFR method, that is, the SWAMI method.
(Wall mask insulation method)
However, it goes without saying that other methods may be used. In the present invention, first, as shown in FIG.⁺Type base
P on board 10^-Having the epitaxial layer 12
Injecting and pushing impurities into the silicon wafer
Thus, an N-type well 14 and a P-type well 16 are formed. About
Pattern and etch nitride / oxide dielectric layer
As a result, only the active device area (moat area) 18
Cover.   Needless to say, the substrate 10 is not necessarily an epitaxy.
Need not be silicon, and need not be silicon
No matter what, if it has a crystalline semiconductor surface part
Good. That is, for example, instead of SOI (silicon-on-
Insulator) structure and its crystalline semiconductor surface
Parts are completely separated by a buried dielectric layer
Is also good. Or also less preferred than silicon
Introduces silicon / germanium and other semiconductor structures
It may be used. Similarly, the N-type wells 14 and
CMOS well structure consisting of P-type well 16 and
The so-called "twin tab", which is necessarily described later
Process (N-type well 14 or PMOS device area
Type well 16, i.e. the NMOS device area
Process of doping by performing on-implantation)
It is not necessary to make
Although there is no
It is also possible to do. ・ The process flow at the next point is the LOCOS method (selective acid
Slightly different from the field separation method
And the etch reaction of the nitride / oxide dielectric layer is
After stopping on the silicon, patterning the nitride layer
While the photoresist mask used remains,
After the etching of the capacitor, the substrate 10 (more precisely,
Part of the epitaxial layer 12) has a depth of, for example, 2000 angstroms.
Let the storm remove the etch. Then new
After a simple nitride layer is deposited, a short etch-back
The silicon recess just formed by etching
The nitride layer is left on the side wall (only) of the depression. Above
Process when the field oxide layer 20 is grown
Lateral wraparound is reduced and such processing
Compared with the case where the process is not performed, the above field oxidation
The concave part of the material layer will be deeper into the substrate.   As mentioned earlier, the field insulation method was used.
Other methods may be used.
The field insulating dielectric layer 20 is not necessarily called oxide.
It is not necessary to oxidize this for layer 20
It is preferable to use a material layer. ・ Use the photoresist mask as it is
Then, ion implantation for channel stop formation is performed. This
To do this, for example, set the implantation energy to 100 keV and
3 × 10¹²atoms / cm^TwoIndiscriminate injection of boron as
Now. By performing additional ion implantation in this manner,
The threshold of the parasitic transistor in the thick field
Field voltage increases, and the field oxide
This helps to prevent generation of leakage current at the bottom of the layer 20.
It is. . Next, the field oxide layer 20 is immersed in, for example, water vapor.
At a temperature of 900 ° C and a thickness of about 8000 Å
Lengthen. ・ Next, after growing and removing the dummy gate oxide layer,
The gate oxide layer 22 may be_TwoIn a mixed atmosphere of
And the thickness will be 250 angstroms at 950 ° C
To grow. Then, a polysilicon layer 24 (for example,
(So that only 4500 Angstroms)
Dope (eg with POCl3). After that, the protective layer 2
6 (for example, a TEOS oxide with a thickness of 2000 angstroms
LPCVD by [Decomposition of tetraethyl orthosilicate]
Deposited oxide), but this layer 26 contains nitride or nitride
/ Oxide composite layer may be more advantageous)
Deposition on polysilicon layer 24 and subsequent etch process
The polysilicon layer 24 is protected from the process. Then
The photoresist layer 28 is patterned to form the polysilicon layer 24.
(This layer not only becomes the gate later, but also at the gate level.
A predetermined pattern)
I do. FIG. 1 shows the structure thus obtained.
It is.   The dielectric structure that constitutes the gate is
Less preferred, but multi-layer induction using others
Dielectric layer or dielectric material other than silicon dioxide
Structure of an insulated gate field effect transistor having
May be implemented.   In addition, the polysilicon layer 24 is not necessarily
It does not need to be made of crystalline silicon,
Although not preferred, the layer 24 may have a multilayer structure or
Combined with, or instead of, multilayer structures, metal silicides
Using a structure that includes side or refractory metal materials;
You may. ・ Then, the oxide (or nitride) protective layer 26
After the etching process,
While the photoresist layer 28 remains, silicon
Performing an etching process to form the polysilicon layer 24 as desired.
Etch to the pattern If necessary, at this time
Reach-through ion implantation at the point (via polysilicon layer 24)
Ion implantation method that reaches the inside of the substrate
The photoresist layer is formed by using only the NMOS region or the P-type well 16.
Patterning to expose, implantation energy 80ke
V, dose amount 1 × 10¹³atoms / cm^TwoDo as
As a result, the NMOS device has an LDD region (low concentration drain).
Region). . Then, on the polysilicon layer 24, for example, a thickness of 2000
Angstrom nitride layer 30 conformally (example
For example, by using LPCVD (chemical vapor deposition).
After the deposition, the nitride layer 30 is etched back.
From the filament (Fig. 3, also indicated by the reference numeral 30)
Is left. Figure 2 shows the structure thus obtained
.   The nitride layer 30 is not necessarily made of silicon nitride.
Need not be, but followed by a gate dielectric layer
Silicon nitride should be used for protection from the oxidation process.
Particularly preferred. However, use non-silicon dielectric material
Is possible, or (less preferred)
However, the filament part is simply made of oxide.
It can be formed even if it is formed. . Then, for the exposed silicon part, for example, a depth of 5000
Etch to Angstrom. However,
Field oxide layer 20, protective layer 26 and sidewall nitride
Silicon is source / drain core due to the
Because only the desired part of the contact area is exposed,
The above etching process is an etching process without patterning
Preferably, it is a process. This self-aligned etch process
Therefore, as shown in FIG.
The part 32 is formed by etching.   The etch depth in the above etch process must be strict
It is not necessary, but the source / drain contact area
The depth of the region is two-thirds or more of the thickness of the field insulating region 20
Preferably, this is a mandatory requirement.
There is no. The thickness of the source / drain contact area
Is increased, the required etching time in the etching process
The process will take longer, but will otherwise cause significant disruption to the process.
Does not result in Conversely, reduce the thickness of the area
P⁺Type region and N⁺The passage to the mold area is shortened and
As a result, some of the advantages of the present invention will be diminished.
It is. Thus, in the present invention, the source / drain con
The tact depth should be at least twice the depth of the groove 38
Is desirable. However, we have to adhere to such a depth relationship
If not, some of the benefits of the present invention are preserved as such
However, such an implementation is not very favorable.
Yes. ・ Etched silicon as above
Later, a dielectric layer 35 (preferably an oxide layer) is formed.
Then, the concave portion 32 of the silicon is covered. For this
Is, for example, an oxide film with a thickness of 250 angstroms
After growing the oxide, 1500 Å thick oxide
A layer is formed. Thus, a thick oxide layer can be deposited
250 angstrom thick oxidation prior to formation
Better interface state by growing the material film
It becomes possible. But instead of doing this, grow
If the dielectric by the method is preferred,
I will grow a dielectric that will be 1500 angstroms
You can also do it.   In the above process, the growth (as in this example)
When using dielectric by vapor deposition instead of dielectric by method
In this case, the side wall dielectric filament portion 30 has an oxidation resistance.
It is not necessary to form it with an electric conductor.
Instead, it can be made of oxide. • At this point, additional channel storage as needed
By performing ion implantation for forming a pump, the dielectric 35 (third
At the bottom of the figure (formerly at the bottom of the field oxide layer 20)
Channel (in addition to the channel stop area 21)
A stop region 34 is formed. For this, for example,
Input energy 100 keV, dose 2 × 10¹²atoms / cm^Twoage
Perform boron ion implantation as indiscriminate ion implantation
Alternatively, add an additional mask to form the NMOS device area.
That is, only the P-type well 16 is exposed to implanted ions.
The injection energy to 100 keV and the dose to
1 × 10¹³atoms / cm^TwoConcentration of boron ions
An injection may be performed. Figure 3 is thus obtained
This shows the structure that was used. Next, the recess 32 is refilled. To do this,
For example, an amorphous silicon with a thickness of 5000 angstroms
After forming a conformal layer conformally, the photoresist
Perform a flattening process by etching back
As a result, the semiconductor material portion 36 and the gate oxide layer 22
Make it qualitatively the same plane. (Note that this refill
In the process, instead of the above amorphous silicon, polysilico
May be used. FIG. 4
The structure shown in is obtained.   In some cases, as described above,
Do not flatten to the plane of the original substrate surface
May be. That is, instead of the above, the silicon deposition depth
And the etch back depth of the semiconductor material
The surface of 36 is higher than the surface of gate oxide layer 22
To In such an embodiment, the process
Therefore, the groove 38 surrounding the semiconductor material portion 36 is
Direct contact with substrate near edge of field oxide layer 20
The advantage is that the risk of
It is. (Of course, an acid for etching back the dielectric layer 35)
The compound etch-back process takes a long time
By doing so, the semiconductor material portion 36 and the channel region 33
Contact (and interdiffusion) state between silicon and nearby
It is necessary to continue the etch-back process to obtain
It is important. For example, as the field oxide layer 20
When this is formed by the LOCOS method, the upper surface
It will be inclined from the surface of the wall filament part 30
Therefore, the substrate 10 near the field oxide layer 20 is
The necessary to remove isotropically to expose
The length of the dielectric layer 35 exposes the substrate 10 near the gate region 24.
Of the dielectric layer 35 necessary to remove the
It can be longer than the length. Even better
In addition, the field oxide layer 20 causes a load on the oxide etch.
The dielectric layer 35 serves as a gate.
Near the field oxide layer 20 near the region 24
Can also actually erode quickly. In case
Therefore, in the above-described refilling step, the concave portion 32
Refilling this with metal material instead of silicon
In this case, for example, the metal material may have a thickness
Is 5000 Å by chemical vapor deposition.
After deposition, etch back using photoresist
What is necessary is to perform flattening by. . Thus, by performing the oxide etching process,
The drain / drain contact recess 32
The conductor layer 35 is etched back, and the edge of the semiconductor material portion 36 is removed.
A groove 38 (Fig. 5A) is formed around the periphery. This etch process
Short-term wafers, preferably with, for example, 10% HF
ET shall be used. Then polysilicon
(Or possibly amorphous silicon) thin
Layer (semiconductor connector) 40 is conformally deposited and formed.
Then, the groove 38 is refilled. This is shown in Figure 5A.
The structure is obtained. FIG. 5B shows the structure.
Near the boundary between the gate region 24 and the semiconductor material portion 36
The part is shown enlarged. -Then etch back the thin polysilicon layer 40
Thus, silicon is left only in the groove 38. (This d
The touch-back treatment is preferably performed using, for example, pyrocatechol KO.
Short wet etch with H or KOH aqueous solution
No, but if desired, use the plasma etch method.
Is also good. Next, the nitride side wall filament portion 30 is
For example H_ThreePO_FourRemoved by wet etching
It is. (This wet etch is performed to improve reliability.
Yes, but less preferred, if desired
If this process is omitted, the nitride side wall filament portion 30
May be left as is. )
By forming the oxide side wall portion 42, preferably,
Good topography (planar configuration) and silicidation
The gate to the source / drain region.
To prevent the occurrence of short circuits, and
Mass during source / drain doping ion implantation
To form a circle. By the above steps, the structure shown in FIG.
Will be obtained. Note that the polysilicon layer 40 is not covered.
By changing the wearing thickness and the thickness after etch back
In addition, the oxide side wall portion 42 defines the position where the semiconductor material portion 36 is formed.
The nitride side wall filament portion 30 defined
It is possible to reduce the width. If you do this
Is one of the implanted ions for doping the semiconductor material portion 36.
The portion between the semiconductor material portion 36 and the gate region 24
Recon will also collide, which means that
Reduce the width of the filament part of the oxide side wall part 42
As a result, the electrically effective source / drain region 44
This means that the impurity concentration can be increased.
These include this electrically effective source / drain region 44.
It is possible to adjust the profile of impurity concentration
It is nothing less than that. This is sometimes
Avoids the hot carrier effect and lowers the series resistance.
To make the compromise between reducing
Is valid for. However, it is necessary to improve the management system in manufacturing.
To prevent the resistance to punch-through phenomenon from deteriorating
To do this, the filament part by the oxide side wall 42 is required.
Is sufficiently large and the high concentration impurities
To prevent high concentrations of impurities from entering the substrate
Is most preferred. ・ Next, for example, the injection energy is set to 150 keV and the dose is
To 3 × 10^Fifteenatoms / cm^TwoArsenic as the NMOS device area
Region, that is, the P-type well 16 and the implantation energy is 20 keV.
And the dose is 5 × 10^Fifteenatoms / cm^TwoIn front of boron as
The mask injected into the PMOS device region, that is, the N-type well 14 is used.
By performing the masking process twice, P⁺Type
And N⁺Source / drain impurities of the above NMOS device
Introduce to the region and the PMOS device region respectively. this
The semiconductor material portion 36 by ion implantation twice.
Doping followed by annealing (e.g. argon
In an atmosphere at 900 ° C for 65 minutes).
This promotes the outward diffusion of impurities and
Is doped with silicon, and the electrically effective source /
A drain region 44 is formed. In this case, exposure if desired
The entire surface of the silicon region (ie, semiconductor material portion 36 and
A known method for forming a self-aligned silicide region in the gate region 24)
It may be formed by. (For this, the example
For example, to make titanium 2000 Angstrom thick
After deposition over the entire surface, heat it to 675 ° C in a nitrogen gas atmosphere.
Heat to allow silicidation reaction to take place.
Recon (this silicon has already formed a nitrogen-containing compound
The titanium putter was not at the top
And interconnect processing to define surrounding interconnects.
And then heated to 800 ° C to make the silicide
Annealing to reduce the sheet resistance
Do it. (Note that in this case, the semiconductor material section 36 is
Formed deeper than the source / drain diffusion region
Therefore, these regions are more implanted than normal.
Retention of large total dose of impurities, impurities in silicide
The risk of impurity concentration being reduced by precipitation on
Not at all. FIG. 7 shows the structure obtained by the above processing steps.
It shows the structure. ・ Thus, the process involves deposition of an interlayer dielectric layer,
Tact hole etch formation, metal material deposition and its
Etch treatment, application of a protective film and its etching
End by performing the usual steps such as
Will be completed.   FIG. 8 shows the present invention manufactured as described above.
1 is a plan view showing a semiconductor integrated circuit structure according to the present invention. [The invention's effect]   As described above, the integrated circuit according to the present invention is half that.
When the conductive material portion 36 is completely insulated by the dielectric layer 35,
These semiconductor materials 36 are etched by silicon.
To form a recess and oxidize the etched area
Covering with an object and filling the recess with polysilicon
After a short isotropic etch, the polysilicon
The filament part of the concrete is adhered,
Edged semiconductor material section 36 and active device channel area
Contact with the area 33, and then the minute area of this contact area
Out-diffusion through the active region
A minute diffusion region 44 is formed in the
Region 44 serves as an electrically effective source / drain region
In addition, the side wall was placed above the gate.
By forming the filament part 30 of the silicide,
The etching process can be a self-alignment process.   Thus, the present invention has the following effects as described above.
It is to do. 1. Valid P⁺−N⁺Separation interval from layout at circuit design
Latch-up because it is much larger than visible
The tendency is reduced, in fact, the integrated circuit according to the invention
In P⁺−N⁺Separation intervals make this a separate design rule.
It is possible to make an exception as a file. 2. Resistant to one-shot event disruption. 3. Extremely good carrier mobility control
It must be possible. 4.Do not add series resistance to the electrical characteristics of the device.
In addition, the thermionic effect can be minimized. 5. Add to the board directly under the source / drain contact area
By forming additional channel stop regions
The separation effect can be further improved if necessary.
Ability. Such improvement of the separation effect is simply
Between the NMOS regions (that is, the NMOS device region adjacent to the PMOS device region).
Between the mote as well as between
(That is, a certain NMOS device region and its neighboring
Between NMOS device regions). 6. The present invention uses the LOCOS method, the MFFFR method (SWAMI method), etc.
It can be implemented using various field separation technologies.
That. 7. The latch-up tendency further reduces the current regeneration effect.
Can be reduced by limiting the area.
When. 8. The short channel effect is reduced. 9. When the sheet resistance in the "source / drain" area is conventional
Better than conventional interconnect wiring
A region must be obtained. 10.Conventional self-aligned direct reaction silicidation process or
Describes a direct reaction metallization process with the fabrication method according to the invention.
Can be used in combination. 11. The parasitic capacitance in the source / drain area is reduced,
As a result, the operating speed of the circuit incorporating the device according to the present invention
Can be increased. 12. The present invention is applied to a silicidation process and a peripheral wiring layer formation process.
Surface layer that can absorb impurities from silicon
By combining with processes that can be formed
And improved resistance to spikes
Is obtained. 13. The present invention is applied to a silicidation process and a peripheral wiring layer forming process.
Surface layer that can absorb impurities from silicon
By combining with processes that can be formed
And the advantage that the specific contact resistance is improved can be obtained.
When. 14. The present invention is applied to a silicidation process and a peripheral wiring layer forming process.
Surface layer that can absorb impurities from silicon
By combining with processes that can be formed
The resistance to the hot carrier effect is improved.
Benefits.   The following section is further disclosed in connection with the above description. (1) Insulated gate field effect transistor active device
Have, and A substrate having an upper portion of a single crystal semiconductor; The plurality of active devices surrounding the plurality of active device regions;
A field separation area defining a vice area; • across the active device area at a given point
At the bottom of those places, the channel area of the transistor
And isolated from the transistor channel region.
A plurality of conductive gate lines, A plurality of source / drain contact areas, .Each of the plurality of source / drain contact regions
Is recessed into said substrate and is separated from said substrate by a dielectric layer.
Having a partially separated conductive material portion, .Slightly above the source / drain contact area
One of the channel regions is adjacent to the other
Is electrically coupled by the outward diffusion
Integrated circuit. (2) the source / drain contact region is
Outward diffusion of impurities into adjacent ones of the channel regions
Electrical connection by means of
The junction depth of the outward diffusion part of the object is
Less than half the depth of the source / drain contact area
The integrated circuit according to claim 1, wherein (3) the source / drain contact region is the substrate
Have a surface substantially flush with the surface of the
2. The integrated circuit according to claim 1, comprising: (4) the source / drain contact region is the substrate
Has a surface on a plane substantially above the surface of the
2. The integrated circuit according to the above item 1, wherein (5) The gate line is horizontally insulated by the saw.
-Drain contact region to sidewall dielectric filament
Separated by the
Where the drain / drain contact region is bonded to the substrate
The out-diffusion portion in the vicinity of the position is the dielectric filament.
Item 1 described above as having a width almost equal to the width of the
Integrated circuit. (6) With the source / drain contact area
And the adjacent ones of the channel regions
1000 Angstroms
Trom or below maximum depth
(Provided by surrounding joints)
2. The integrated circuit according to claim 1, wherein (7) The insulated source / drain contact area
The dielectric surrounding is made of silicon dioxide
2. The integrated circuit according to claim 1, comprising: (8) A small portion of the source / drain contact region
If at least the substrate at the bottom is higher
Having a pure concentration, said impurities being insulated each
The failure in the vicinity of the source / drain contact region
The conductive type is opposite to that of the pure substance diffusion section.
2. The integrated circuit according to item 1. (9) The integrated circuit is an NMOS device and a PMOS device
And the higher impurity concentration is higher than that of the NMOS.
Item 8 described above, which is unevenly distributed at the bottom of the device
The described integrated circuit. (10) The field insulating region is provided in the substrate,
The substrate is at the top where the impurity concentration is higher
And the filament insulating region is formed by the impurities.
A channel stop area is defined at the bottom of
Higher impurity below the source / drain contact area
Substance concentration is higher than the impurity concentration of the channel stop region.
2. The integration circuit according to claim 1, wherein
Road. (11) The source / drain contact region is
Have a depth of at least two-thirds the depth of the field insulating region.
2. The integrated circuit according to claim 1, wherein (12) The isolated source / drain contact area
Is substantially filled with doped polysilicon.
2. The integrated circuit according to the above item 1, wherein (13) The source / drain contact region is substantially
Before being filled with refractory metal material
2. The integrated circuit according to item 1. (14) The integrated circuit is an NMOS device and a PMOS device
These NMOS devices and PMOS devices
The minimum separation between the chairs via the field isolation region is
Through field isolation between NMOS devices
So that it is no larger than three-half of the minimum separation
2. The integrated circuit according to the above item 1. (15) The semiconductor is substantially made of silicon.
2. The integrated circuit according to claim 1, comprising: (16) The source / drain contact region is formed of the conductive material.
Within 20% to 80% of the minimum width of the gate line
2. The integrated circuit according to claim 1, wherein the integrated circuit has
Road. (17) The source / drain contact region is formed of the conductive material.
Within 20% to 80% of the minimum width of the gate line
With a depth of 2000 Angstroms
Make sure it is within 5000 Angstroms.
2. The integrated circuit according to claim 1, wherein (18) Insulated gate field effect transistor active device
Have, and .A substrate having an upper portion of a single crystal semiconductor; .Surrounding and defining multiple active device areas
Field oxide region, -Traverse the area at a predetermined location on the active device
Cut off the transistor channel at the bottom of those places
Define the area and define these transistor channels.
Insulated from the tunnel region, and further polycrystalline material, mainly polycrystalline
A plurality of gate lines made of crystalline silicon, . Consisting of multiple source / drain contact areas, • Each of these source / drain contact areas
Recessed into the substrate and partially separated from the substrate by a dielectric layer
Having electrically insulated conductive material, .Slightly above the source / drain contact area
One of the channel regions is adjacent to the other
Is electrically coupled by the outward diffusion
Integrated circuit. (19) The source / drain contact region is
Outward diffusion of impurities into adjacent ones of the channel regions
Electrical connection by means of
The junction depth of the outward diffusion part of the object is
Less than half the depth of the source / drain contact area
Item 19. The integrated circuit according to Item 18, wherein (20) The source / drain contact region is the substrate
Have a surface substantially flush with the surface of the
19. The integrated circuit according to claim 18, comprising: (21) The source / drain contact region is the substrate
Has a surface on a plane substantially above the surface of the
Item 19. The integrated circuit according to Item 18, wherein (22) The gate line is horizontally insulated by the insulated saw.
-Drain contact region to sidewall dielectric filament
Separated by the
Where the drain / drain contact region is bonded to the substrate
The out-diffusion portion of the impurity in the vicinity of the
The width of the filament portion is almost equal to the width of the filament portion.
19. The integrated circuit according to item 18. (23) With the source / drain contact area
And the adjacent ones of the channel regions
1000 Angstroms
Trom or below maximum depth
(Provided by surrounding joints)
19. The integrated circuit according to claim 18, wherein (24) The isolated source / drain contact area
The dielectric surrounding is made of silicon dioxide
19. The integrated circuit according to claim 18, wherein the integrated circuit comprises: (25) A small portion of the source / drain contact area
If at least the substrate at the bottom is higher
Having a pure concentration, the impurities being
In the vicinity of the source / drain contact region
The conductivity type is opposite to that of the impurity diffusion portion.
Item 19. An integrated circuit according to Item 18. (26) The integrated circuit is an NMOS device and a PMOS device
And the higher impurity concentration is higher than that of the NMOS.
Item 25, which is unevenly distributed at the bottom of the device
The described integrated circuit. (27) The field insulating region is provided in the substrate,
The substrate is at the top where the impurity concentration is higher
And the filament insulating region is formed by the impurities.
A channel stop area is defined at the bottom of
Higher impurity below the source / drain contact area
Substance concentration is higher than the impurity concentration of the channel stop region.
Item 21.
Road. (28) The source / drain contact region is
Have a depth of at least two-thirds the depth of the field insulating region.
19. The integrated circuit according to claim 18, wherein the integrated circuit is configured as follows. (29) The insulated source / drain contact area
Is substantially filled with doped polysilicon.
Item 19. The integrated circuit according to Item 18, wherein (30) The source / drain contact region is substantially
Before being filled with refractory metal material
19. The integrated circuit according to item 18. (31) The integrated circuit is an NMOS device and a PMOS device
These NMOS devices and PMOS devices
The minimum separation between the chairs via the field isolation region is
Through field isolation between NMOS devices
So that it is no larger than three-half of the minimum separation
Item 19. The integrated circuit according to Item 18, wherein (32) The source / drain contact region is formed of the conductive material.
Within 20% to 80% of the minimum width of the gate line
Item 19. The integrated circuit according to Item 18, wherein
Road. (33) The source / drain contact region is formed of the conductive material.
Within 20% to 80% of the minimum width of the gate line
With a depth of 2000 Angstroms
Make sure it is within 5000 Angstroms.
19. The integrated circuit according to claim 18, wherein (34) Insulated gate field effect transistor active device
Have, and .A substrate having an upper portion of a single crystal semiconductor; .Surrounding and defining multiple active device areas
Field oxide region, -Traverse the area at a predetermined location on the active device
Cut off the transistor channel at the bottom of those places
Define the area and define these transistor channels.
Insulated from the tunnel region, and further polycrystalline material, mainly polycrystalline
A plurality of gate lines made of crystalline silicon, . Consisting of multiple source / drain contact areas, .Each of these source / drain contact areas
× 10¹⁸Doped in the above concentration, invades the substrate,
And partially insulated from the substrate by a dielectric layer
Crystal silicon part, .Slightly above the source / drain contact area
One of the channel regions is adjacent to the other
Are electrically coupled by the outward diffusion of
Outer diffusion is less than 1000 Angstroms or less
Source / drain contacts in the substrate
A maximum depth that is less than half the depth of the region (the outdiffusion
(Provided by the joint surrounding the part)
An integrated circuit characterized by: (35) The source / drain contact region is the substrate
Have a surface substantially flush with the surface of the
35. The integrated circuit according to the above item 34, comprising: (36) The source / drain contact region is provided on the substrate.
Has a surface on a plane substantially above the surface of the
35. The integrated circuit according to the above item 34, wherein: (37) The gate line is horizontally insulated by the insulated saw.
-Drain contact region to sidewall dielectric filament
Separated by the
Where the drain / drain contact region is bonded to the substrate
The out-diffusion portion of the impurity in the vicinity of the
The width of the filament portion is almost equal to the width of the filament portion.
34. An integrated circuit according to item 34. (38) The isolated source / drain contact area
The dielectric surrounding is made of silicon dioxide
35. The integrated circuit according to the above item 34, comprising: (39) A small portion of the source / drain contact area
If at least the substrate at the bottom is higher
Having a pure concentration, said impurities being insulated each
The failure in the vicinity of the source / drain contact region
The conductive type is opposite to that of the pure substance diffusion section.
34. An integrated circuit according to item 34. (40) The integrated circuit is an NMOS device and a PMOS device
And the higher impurity concentration is higher than that of the NMOS.
Item 39, which is unevenly distributed at the bottom of the device
The described integrated circuit. (41) The field insulating region is provided in the substrate,
The substrate is at the top where the impurity concentration is higher
And the filament insulating region is formed by the impurities.
A channel stop area is defined at the bottom of
Higher impurity below the source / drain contact area
Substance concentration is higher than the impurity concentration of the channel stop region.
35.The integration circuit according to claim 34, wherein
Road. (42) The source / drain contact region is
Have a depth of at least two-thirds the depth of the field insulating region.
35. The integrated circuit according to claim 34, wherein (43) The integrated circuit is an NMOS device and a PMOS device
These NMOS devices and PMOS devices
The minimum separation between the chairs via the field isolation region is
Through field isolation between NMOS devices
So that it is no larger than three-half of the minimum separation
35. The integrated circuit according to the above item 34. (44) the source / drain contact region is the conductive
Within 20% to 80% of the minimum width of the gate line
35. The integration circuit according to claim 34, wherein
Road. (45) the source / drain contact region is the conductive
Within 20% to 80% of the minimum width of the gate line
With a depth of 2000 Angstroms
Make sure it is within 5000 Angstroms.
35. The integrated circuit according to claim 34, wherein (46) When manufacturing integrated circuits, (A) preparing a substrate having an upper portion of a single crystal semiconductor, (B) A plurality of flashes are provided at predetermined locations on the single crystal semiconductor.
Forming a field isolation region and forming a field isolation region.
Define an active device area in between, (C) a predetermined region including a predetermined portion of the active device region;
A portion of each of the active device regions above the location
Multiple transistors that define the transistor channel area
Forming an edged gate line, (D) forming a side wall filament portion on the gate line
And (E) the gate line in the upper portion of the single crystal semiconductor;
Or the field separation area, or
The side wall filament part on the gate line
Even uncovered areas to approximately the specified depth
Source / drain contact by etching
Forming a recess (F) A dielectric layer is formed on the bottom and side walls of the recess.
Formally, (G) The source / drain contact recess is made conductive.
Filled with material, (H) forming the conformally formed dielectric layer as described above;
Etch bar around source / drain contact recess
The source / drain contact
Forming a groove surrounding the surface of the recess,
Refill the groove with conductive material filament, (I) heating the substrate to separate the source / drain;
Out diffusion of impurities from the ground contact region.
The source / drain contact region
Combined with the corresponding transistor channel area
Multiple source / drain diffusions are formed
A method for manufacturing an integrated circuit, comprising: (47) (j) The source / drain contact recess is formed
In the step (g) of filling with a conductive material,
To use a conductive material that is lightly doped
Following the above process, (K) the source / source in the PMOS active device area;
Introducing P-type impurities into the drain contact region
The source / drain in the NMOS active device region.
N-type impurities into the contact region
47. The method of manufacturing an integrated circuit according to the above item 46. (48) In the step (c) of forming the conductive gate line,
Firstly made of polysilicon and for protection
To form a conductive part covered by a dielectric layer
47. The method of manufacturing an integrated circuit according to the above item 46. (49) In the step (c) of forming the conductive gate line,
First, polysilicon / silicide sand
Consisting of a switch structure and covered by a protective dielectric layer
The method according to claim 46, wherein the conductive portion is formed.
Manufacturing method of integrated circuit. (50) The protective dielectric layer is made of silicon nitride
And the insulated source / drain contact area
In the step of isotropically etching back the electric body layer surrounding the
In this case, the protective dielectric layer does not remove it,
Surrounding the isolated source / drain contact area
The electric conductor layer is mainly made of silicon oxide.
50. The method of manufacturing an integrated circuit according to the above item 49, wherein: (51) The source / drain contact recess is made conductive.
In the step (g) of filling with the material,
Fill the lane contact recess with metal material
49. The method of manufacturing an integrated circuit according to claim 46, wherein (52) The metal material is tungsten, molybdenum, tan
Tar, niobium, columbium, palladium and
Select and use as appropriate from among metals such as
52. The method of manufacturing an integrated circuit according to the above item 51.   The embodiments of the present invention have been described above.
The integrated circuit and its fabrication method according to
May be added or changed as appropriate.
Needless to say.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, FIG. 2, FIG. 4, FIG. 5, FIG. 5A, FIG. 5B, FIG. 6, and FIG. FIG. 8 is a plan view showing a part of an integrated circuit device according to the present invention. 10 ...... P ⁺ -type substrate 12 ...... P ^- -type epitaxial layer 14 ...... N-type well 16 ...... P-type well 18 ...... active device region (moat region) 20 ...... field oxide region 22 ...... gate oxide Layer 24 Polysilicon gate layer 30 Nitride filament part 33 Channel region 35 Dielectric layer 36 Semiconductor material part 38 Groove 40 Polysilicon layer (or amorphous silicon layer), 42 ... sidewall filament part 44 ... impurity diffusion part (effective source / drain area), 46
... silicide region.

Continuation of the front page (72) Inventor Che-chaway Richardson Ableton Benz, Texas, USA 558 (56) References JP-A-60-161669 (JP, A) (58) Fields studied (Int. Cl. ⁶ , DB name) H01L 27/092 H01L 21/8238 H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] A substrate having an insulated gate field effect transistor active device, further comprising: a first conductivity type single crystal semiconductor top; and a plurality of fields surrounding the plurality of active device regions and defining the plurality of active device regions. An isolation region; and a plurality of transistors, each of the plurality of transistors: a) a gate line, defining a transistor channel across the active device region and below the gate line; and B) a plurality of source / drain contact regions provided on both sides of the gate line, wherein the plurality of source / drain contact regions are provided on both sides of the gate line;
Wherein each of the drain contact regions has a semiconductor material portion indented into the substrate and doped with a second conductivity type impurity, and a portion provided below the semiconductor material portion; A dielectric layer having an upwardly extending portion provided between a portion and the substrate; and a dielectric layer between the semiconductor material portion and the substrate and on the upwardly extending portion of the dielectric layer. A semiconductor connector in contact with the semiconductor material portion, the semiconductor connector having a first portion provided and having a second portion provided on the substrate between the semiconductor material portion and the transistor channel. The plurality of transistors, including the plurality of source / drain contact regions; and each other by a corresponding one of the plurality of transistor channels. A plurality of source diffusion regions and a plurality of drain diffusion regions, wherein each of the source diffusion regions and each of the drain diffusion regions is the first and one of the plurality of semiconductor connectors on a side opposite to the semiconductor material portion. Contact the second part,
An integrated circuit comprising: the plurality of source diffusion regions and the plurality of drain diffusion regions doped with an impurity of the second conductivity type. 2. The integrated circuit according to claim 1, wherein the semiconductor connector has a junction depth that is less than or equal to half the depth of the source / drain contact region in the substrate.