JP2886909B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an effective technique applied to a semiconductor integrated circuit device having a multilayer wiring structure employing a CCB method.

[Conventional technology]

The semiconductor integrated circuit device having a multilayer wiring structure (semiconductor pellet) are CCB (C ontr on the mounting surface of the chip carrier substrate
It is implemented in olled C ollapse B onding) scheme. That is, the CCB method is a method in which a semiconductor integrated circuit device is mounted with a bump electrode (solder electrode) interposed on a chip carrier substrate, and both are electrically connected. This kind of
The CCB method can increase the mounting density as compared with the bonding wire method.

The semiconductor integrated circuit device employs, but is not limited to, a gate array system. In order to increase the number of signal wirings connecting the circuits and increase the use rate of the circuits, for example, aluminum wiring having a four-layer wiring structure is used. Is formed. The external terminals (bonding pads) formed in the uppermost layer wiring (fourth layer wiring) forming step are electrically connected to the third layer wiring through connection holes formed in the underlying interlayer insulating film. Have been. On the main surface of the external terminal, a barrier metal layer (or BL) deposited by a sputtering method through a bonding opening formed in a final protective film covering the external terminal.
M: Ball Limiting Metallization) and bump electrodes are sequentially laminated.

The barrier metal layer is a chromium (Cr) film, a copper (Cu) film,
Each of the gold (Au) films is sequentially deposited from the surface side of the external terminal. The Cr film serves as a barrier for suppressing a reaction between the Cu film and an external terminal. The Cu film ensures the leak property with the bump electrode. The Au film prevents oxidation of the Cu film. That is, this barrier metal layer has a feature of improving the adhesion (bondability) between the external terminal and the bump electrode.

On the main surface of the external terminal, a silicon nitride film deposited by a sputtering method between the external terminal and the final protective film is formed. This silicon nitride film is used as an etching stopper at the time of dry etching for forming the bonding opening, while improving the moisture resistance of the fourth layer wiring, particularly the external terminal.

A semiconductor integrated circuit device adopting the CCB method is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-318742 (Japanese Patent Application No. 62-156346).
No.).

[Problems to be solved by the invention]

The present inventor has studied the semiconductor integrated circuit device adopting the above-described CCB method, and has found the following problem.

Since the external terminal is arranged on the step of the connection hole formed on the third layer wiring, the surface of the external terminal has a step shape corresponding to the step of the connection hole.
The barrier metal layer deposited on the main surface of the external terminal by the sputtering method has reduced step coverage at the step, and the barrier metal layer is not partially deposited on the surface of the external terminal. A void is generated in the bump electrode with a portion where the poor adhesion of the barrier metal layer occurs as a nucleus. For this reason, the current path of the bump electrode is reduced due to the void, and there is a problem that the migration resistance is reduced. Also,
Since the thermal resistance of the heat radiation path of the bump electrode increases, there is a problem that the circuit characteristics of the semiconductor integrated circuit device change and the electrical reliability decreases.

Further, the silicon nitride film deposited on the main surface of the external terminal by the sputtering method also has reduced step coverage at the stepped portion, similarly to the barrier metal layer. Bonding opening is HF: NH ₄ F
It is formed of an HF-based etchant having a buffering action, such as a system. After the etching is completed, a washing process is performed,
When this type of etchant is diluted by washing with water, the pH (pH) decreases and the acidity increases. For this reason, the diluent of the highly acidic etchant penetrates into the surface of the external terminal through the portion where the poor deposition of the silicon nitride film occurs, and the external terminal itself is etched. In the worst case, there is a problem that the external terminals and the lower third-layer wiring are disconnected, and the electrical reliability (or the production yield) is reduced.

An object of the present invention is to provide a technique capable of improving the electrical reliability of a semiconductor integrated circuit device having a multilayer wiring structure employing a CCB method.

Another object of the present invention is to provide a technique capable of improving the production yield of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The following is a brief description of an outline of typical inventions disclosed in the present subject matter.

(1) A wiring formed under the interlayer insulating film is electrically connected to an external terminal on the interlayer insulating film through a connection hole formed in the interlayer insulating film, and a bonding formed on a final protective film covering the external terminal. In a semiconductor integrated circuit device in which a barrier metal layer deposited by sputtering on the external terminal through an opening and a bump electrode layer formed of solder are sequentially laminated, a wiring under the interlayer insulating film is formed of an aluminum film or an aluminum alloy film. The external terminals on the interlayer insulation are made of a copper film or a gold film, and the surface of the external terminals is reflowed by laser irradiation.

(2) A silicon nitride film deposited by a sputtering method is provided between the external terminal and the final protective film.

[Action]

According to the above-mentioned means (1), the step formed on the surface of the external terminal at the step of the connection hole connecting the external terminal and the lower wiring is flattened by laser irradiation and formed on the surface of the external terminal. Since the step coverage of the barrier metal layer is improved, bondability between the barrier metal layer and the bump electrode layer can be improved, and the generation of voids can be reduced.

Further, since the wiring under the interlayer insulating film can be finely processed by etching, the integration degree of the semiconductor integrated circuit device can be improved.

According to the means (2) described above, the step coverage of the silicon nitride film formed on the external terminal is improved by the means (1), so that the etching solution is diluted by washing with water to reduce the acidity when forming the bonding opening. Even if it becomes stronger, the external terminals are not etched, and disconnection of the external terminals and the underlying wiring can be prevented.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a multilayer wiring structure employing the CCB method.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Example of the invention)

FIG. 2 (cross-sectional view) shows a configuration of a semiconductor device adopting the CCB method according to one embodiment of the present invention.

As shown in FIG. 2, the semiconductor device 1 adopting the CCB method
Reference numeral 00 denotes a pin grid array (PGA) type package, for example. In this semiconductor device 100, a semiconductor integrated circuit device (semiconductor chip) 1 is mounted on a chip carrier substrate (base substrate) 101 with a bump electrode (solder electrode) 30 interposed therebetween. A cap 102 is provided on the back surface (the surface on which no elements are formed) of the semiconductor integrated circuit device 1 via a solder brazing material 103. This is a semiconductor integrated circuit device 1
The heat can be effectively dissipated from the cover 102 to the cap 102. This semiconductor integrated circuit device 1 is made of resin
It is hermetically sealed by 104. The bump electrode 30
Is provided between an input / output terminal formed on the chip carrier substrate 101 and an external terminal (25C) of the semiconductor integrated circuit device 1, and is electrically connected to both. The input / output terminals of the chip carrier substrate 101 are
Are connected to the input / output pins 105 of the chip carrier substrate 101 through respective wirings and through holes.

Next, the semiconductor integrated circuit device (semiconductor pellet) 1
The specific configuration will be briefly described with reference to FIG.

The semiconductor integrated circuit device 1 according to one embodiment of the present invention has a four-layer wiring structure.

As shown in FIG. 1, the semiconductor integrated circuit device 1 is mainly composed of a p ^- type semiconductor substrate 1A made of single crystal silicon. An n ⁻ -type epitaxial layer 3 is stacked on the main surface of the p ⁻ -type semiconductor substrate 1A. An active region (element formation region) is provided on the main surface of the p ⁻ type semiconductor substrate 1A.
In this active region, a buried n ⁺ type semiconductor region 2 is formed between the p ⁻ type semiconductor substrate 1A and the n ⁻ type epitaxial layer 3. The active region is electrically separated from other surrounding active regions by an element isolation region. The element isolation region mainly includes a p ⁻ type semiconductor substrate 1A, an element isolation insulating film (for example, a silicon oxide film) 4 and a p ⁺ type semiconductor region 5.

A bipolar transistor is formed in the active region. This bipolar transistor has a vertical structure in which an n-type collector region, a p-type base region, and an n-type emitter region are sequentially arranged. n-type collector region is n ^-
The semiconductor device includes an epitaxial layer 3, a buried n ⁺ -type semiconductor region 2, and an n ⁺ -type semiconductor region 6 for raising a collector potential. The p-type base region includes a p ⁺ -type semiconductor region 7 that is a graft base region and a p-type semiconductor region 8 that is an intrinsic base region. The n-type emitter region is constituted by an n ⁺ -type semiconductor region 9.

An aluminum wiring 16 a is connected to the collector potential raising n ⁺ -type semiconductor region 6 through a collector opening 4 a formed in the element isolation insulating film 4. A base opening formed in the element isolation insulating film 4 is formed in the p ⁺ type semiconductor region 7.
One end of the base extraction electrode 11 is connected through 4b. The other end of the base extraction electrode 11 is connected to an aluminum wiring 16b through a connection hole 14 formed in the insulating film 13. The base extraction electrode 11 is formed of a polycrystalline silicon film into which a p-type impurity (B) has been introduced. An emitter extraction electrode 12 is connected to the n ⁺ type semiconductor region 9 through an emitter opening 4c formed in the element isolation insulating film 4.
The emitter extraction electrode is electrically connected to an aluminum wiring 16c through a connection hole 15 formed in the insulating film 13. The emitter extraction electrode 12 is formed of a polycrystalline silicon film into which an n-type impurity (As) has been introduced. Each of the aluminum wirings 16a, 16b, and 16c is formed in a first-layer wiring forming step. The aluminum wirings 16a to 16c and the aluminum wiring described other than this are made of pure aluminum or aluminum alloy to which Si or Cu or both are added. Si has the effect of reducing alloy spikes and Cu has the effect of reducing migration. Each of the insulating films 10 and 13 is formed of a silicon oxide film.

Each of the aluminum wirings 16a to 16c is an interlayer insulating film 17.
Covered with. On this interlayer insulating film 17, an aluminum wiring 19 formed in a second-layer wiring forming step is formed. The aluminum wiring 19 passes through a connection hole 18 formed in the interlayer insulating film 17 to form a first-layer aluminum wiring 16.
Connected to a. The connection hole 18 has a stepped surface formed in a floor shape to improve the step coverage of the aluminum wiring 19.

The aluminum wiring 19 is covered with an interlayer insulating film 20. On this interlayer insulating film 20, aluminum wirings 22a, 22b and 22c formed in the wiring forming step of the third layer are formed. Aluminum wiring 22a a second-layer aluminum wiring through connection hole 21 formed in interlayer insulating film 20;
Connected to 19.

Each of the aluminum wirings 22a to 22C is an interlayer insulating film 23.
Covered with. On this interlayer insulating film 23, wirings 25a and 25b and external terminals (bonding pads) 25c formed in the fourth-layer wiring forming step are formed. The wiring of the fourth layer is formed of, for example, copper (Cu). External terminal 25c
Represents a third through a connection hole 24 formed in the interlayer insulating film 23.
It is electrically connected to the aluminum wiring 22b of the layer. The surface of the external terminal 25c has a stepped shape due to the step of the connection hole 24, but is flattened by reflow of the surface by laser irradiation.

Wirings 25a, 2 formed in the fourth-layer wiring forming step
A silicon nitride film 26 deposited by a sputtering method is formed on 5b and the external terminals 25c. The silicon nitride film 26 is used as an etching stopper for improving the moisture resistance of the wirings 25a and 25b and the external terminals 25c and for etching when forming the bonding openings 28 formed in the final protective film 27 covering them.

The external terminal 25c is electrically connected to the bump electrode 30 through the bonding opening 28 with the barrier metal layer 29 interposed therebetween. The barrier metal layer 29 improves the adhesion of the bump electrode 30.

Next, after the external terminals 25c are formed, a method of forming the bump electrodes 30 with the barrier metal layer 29 interposed between the external terminals 25c will be described with reference to FIGS. This will be briefly described with reference to FIG.

First, a connection hole 24 is formed by etching the interlayer insulating film 23 covering the third-layer aluminum wiring 22b formed on the interlayer insulating film 20 using a predetermined mask pattern. In addition,
Most of the third-layer wirings 22 and wirings and elements under the third-layer wirings are processed by dry etching for the purpose of miniaturization.

Next, a conductive film 25 is formed by depositing, for example, copper (Cu) on the interlayer insulating film 23 by a sputtering method. At this time, the surface of the conductive film 25 on the connection hole 24 has a stepped shape due to the step of the connection hole 24, and an overhang shape 31 is formed as shown in FIG.

Next, laser irradiation is performed on the entire surface of the conductive film 25 (and only the region that becomes the external terminal 25c), and the conductive film 25 is reflowed. As the laser, for example, a xenon (Xe) -chlorine (C1) laser having a high absorptivity of laser light on the surface of copper is used. Since this laser outputs laser light of a single wavelength of 308 nm, sufficient reflow can be performed by irradiating the surface of the conductive film 25 with spot irradiation for about 20 ns. The copper has good laser light absorption compared to aluminum, and the energy of the laser light can be concentrated on the surface layer of the copper, so that only the conductive film 25 can be reflowed, and the copper is disposed in the lower wiring and the lower layer. There is a characteristic that does not affect the effect on the element. By this reflow, the overhang shape 31 is relaxed as shown in FIG. 4, and the surface of the conductive film 25 is flattened.

Next, the flattened conductive film 25 is wet-etched with a predetermined mask pattern to form external terminals 25c. The fourth wiring layer is usually used as a power supply wiring layer and does not require fine processing, and is therefore processed by wet etching.

Next, the interlayer insulating film 2 exposed on the external terminals 25c and exposed
3 silicon nitride film 26 deposited by sputtering method, final protective film 2
Each of the silicon oxide films 7 is sequentially laminated as shown in FIG. The silicon nitride film 26 deposited on the external terminals 25c
Since the surface of the external terminal 25c is flattened, the step coverage is improved.

Next, a bonding opening 28 is formed in the final protective film 27 by wet etching using a predetermined mask pattern. HF: NH ₄ F having a buffer action
This is performed using an HF-based etchant such as a system. At this time, the silicon nitride film 26 is used as an etching stopper layer. After the wet etching, a water washing process is performed. This washing process dilutes the HF-based etchant that has permeated the inner wall of the bonding opening 28 and the like, and increases the acidity of the HF-based etchant. However, the surface of the external terminal 25c is flattened by reflow, and the silicon nitride film 26 free from poor adhesion exists on the surface of the external terminal 25c, so that the external terminal 25c is not etched.

Next, the exposed silicon nitride film 26 is removed by etching using the final protective film 27 in which the bonding openings 28 are formed as an etching mask.

Next, external terminals on the final protective film 27 and exposed
A barrier metal layer 29 is laminated on 25c by a sputtering method. The barrier metal layer 29 is made of a chromium (Cr) film 29a, copper (Cu)
The film 29b and the gold (Au) film 29c are sequentially laminated. Since the surface of the external terminal 25c of the barrier metal layer 29 on the external terminal 25c is flattened, the step coverage is improved and there is no poor attachment. This barrier metal layer
29 is processed by etching.

Next, a solder layer is deposited on the surface of the barrier metal layer 29 by a lift-off method, and unnecessary solder layers other than on the surface of the barrier metal layer 29 are removed by a wet back method. Thereafter, the bump layer 30 is formed by performing reflow on the solder layer as shown in FIG.

As described above, copper is used for the external terminals 25c of the semiconductor integrated circuit device 1 employing the CCB method, and the surface of the external terminals 25c is reflowed by laser irradiation and flattened.
The step coverage of the silicon nitride film 26 formed on the external terminal 25c is improved. Thereby, the external terminals 25 based on the dilution of the etching solution for forming the bonding openings 28 are formed.
Since etching of c can be prevented and disconnection of the external terminal 25c can be prevented, electrical reliability can be improved. Also,
The production yield of the semiconductor integrated circuit device 1 can be improved.

Further, the step coverage of the barrier metal layer 29 formed on the external terminal 25c is improved. As a result, the bondability between the barrier metal layer 29 and the bump electrode 30 can be improved, and the occurrence of voids can be reduced, so that the current path of the bump electrode 30 is increased and the migration resistance of the bump electrode 30 is improved. , Electrical reliability can be improved. Further, the thermal resistance of the heat radiation path of the bump electrode 30 can be reduced, and the heat generated by the circuit operation of the semiconductor integrated circuit device 1 can be sufficiently released to the outside, so that the fluctuation of the circuit characteristics can be reduced, Reliability can be improved.

Further, since the third and lower wirings can be formed by dry etching by being formed of an aluminum film or an aluminum alloy film, miniaturization can be achieved and the degree of integration of the semiconductor integrated circuit device 1 can be improved. Can be.

Further, by using copper, which is a low-resistance material, for the fourth-layer wiring, the thickness of the fourth-layer wiring can be reduced, so that the number of manufacturing steps for flattening the final protective film 27 is reduced. Can be reduced.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

For example, the present invention can be applied to a semiconductor integrated circuit device adopting the CCB method configured by a wiring layer of two-layer wiring or three-layer wiring.

In the present invention, gold (Au) may be used instead of copper for the uppermost layer wiring.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a multilayer wiring structure employing a CCB method, electrical reliability is improved and the degree of integration is improved.

Further, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device adopting the CCB method according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device mounted with the semiconductor integrated circuit device. FIG. 6 to FIG. 6 are cross-sectional views of main parts showing a method of forming the semiconductor integrated circuit device in each step. In the drawing, 1 ... semiconductor integrated circuit device, 22a, 22b, 22c ... a third-layer aluminum wiring, 25a, 25b, ... a fourth-layer wiring, 25
c: external terminal, 26: silicon nitride film, 29: barrier metal layer, 3
0 ... Bump electrodes.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/768 H01L 21/60

Claims (3)

(57) [Claims] A first protective film that electrically connects a wiring under the interlayer insulating film and an external terminal on the interlayer insulating film through a connection hole formed in the interlayer insulating film and covers the external terminal; In a semiconductor integrated circuit device in which a barrier metal layer and a solder electrode layer each deposited by sputtering on the external terminal through the bonding opening are sequentially laminated, the wiring under the interlayer insulating film is made of an aluminum film or an aluminum alloy film. A semiconductor integrated circuit device, wherein the external terminals on the interlayer insulating film are made of copper or gold having a reflowed surface. 2. The semiconductor integrated circuit device according to claim 1, wherein the reflow of the surface of the external terminal is performed by laser irradiation. 3. The semiconductor integrated circuit device according to claim 1, wherein a silicon nitride film deposited by a sputtering method is formed between the external terminal and the final protective film.