JP2887236B2 - Video display processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video signal device, and more particularly to a video signal device.
Or multiple movable patterns to larger fixed patterns
Can be superimposed at the selected position above
Also, it concerns the video display processor. Display image
Face is one pixel at a time, horizontal and vertical
It is possible to scroll in the direction. [Prior Art] One or more movable patterns are transferred to a larger fixed pattern.
Overlay at selected position on turn (super import
The basic principle to be adopted is that of the U.S.
No. 4,243,984, which has already been disclosed. Ma
Other systems that disclose movable patterns include:
For example, U.S. Pat.Nos. 4,112,422, 4,129,858, 4,
034,990, 4,107,664, 4,016,362, 4,116,4
No. 44, No. 4,771,155, No. 4,296,476, No. 4,232,374
No. 4,177,462 and 4,119,955 etc.
There is. [Summary of the Invention] A video monitor or a TV used as a video monitor
The graphic pattern of the Levi receiver is
Scroll by hardware scroll function
It is possible to do. In this case, the vertical scroll register and horizontal scroll register
Up to 256 pixels in the horizontal direction
And up to 256 pixels vertically
Can be scrolled. This horizontal scroll
Registers form part of the advanced video processor
And is dependent on the host microprocessor (CPU).
Is loaded. Host microprocessor
8-bit information is used to determine the horizontal position of the cell, and
The 8-bit information is used to determine the horizontal position, and the
Controls the operation of the Vance Video Processor. in this case,
Depending on the vertical and horizontal dimensions of the screen, the horizontal
Crawl register or vertical scroll register
By changing any of the 8-bit storage contents
The display screen in one of the left and right directions for each pixel.
Or roll up and down. The display screen mentioned here depends on the operation mode.
Arranged in 8 to 256 lines and 192 to 256 rows
It is defined as a group of pixels. The display screen is built into the advanced video processor.
Horizontal scroll register and vertical scroll
Once by changing the contents of the
1 pixel per horizontal and vertical
It is possible to crawl. Horizontal scroll
Stored contents of register or vertical scroll register
Is changed and obtained from a storage location in the video display RAM
The data being displayed is stored in the horizontal scroll register and
The vertical scroll register allows the video display RAM
It is changed according to the address change. Example Next, an example of the present invention will be described with reference to the drawings. FIG. 1 shows an advanced video processor 1 according to the present invention.
1 is a block diagram illustrating a video display system 100 including
It is. In the figure, the host microprocessor (CPU) 3
0 is the bidirectional data bus 51, control bus 49 and interrupt line
47 and the advanced video processor (AVDP) 1
Interface. This advanced video processor
1 connects the microprocessor 30 with the color video monitor 33
It is used to interface. Advan
The video processor 1 further includes a dynamic RAM 31
To store the information displayed on the video screen.
The microprocessor 30 and the advanced video processor
Advance via an 8-bit data bus 51 between the processors 1
The configuration registers of the video processor 1 are loaded, and
The microprocessor 30 is displayed on a video screen 32.
The information to be shown is supplied to the video RAM 31. Advancebi
The video processor 1 is activated by the microprocessor 30.
Refresh video screen 32 independently of Seth
Perform Video RAM 31 has an 8-bit address bus and
Advance video processing via an 8-bit data bus
Accessed by the servicer 1. Advanced video processing
The server 1 also has the necessary RAS (row address strobe)
And CAS (column address strobe) signals
Dynamic Video RAM 31
Interface with Sessa 1. Further advance
The video processor 1 has a random access memory.
Video RAM 31 is connected, and this RAM 31
Through the memory 53, the memory address bus 55, and the control line 45.
Connected to the advanced video processor 1. Figure
As a display method for shapes (hereinafter referred to as graphics)
Can use two methods, using a red-green-blue (RGB) monitor 33
This is connected to the advanced video processor via the RGB bus 39.
And a composite video monitor / television
This is connected to a color difference bus 41 and a video encoder using a receiver 35.
Video processor via the coder / RF monitor 37
One or both of the two methods of combining with 1
Is used. The composite video monitor / telephone
The audio input is also given to the Levi receiver 35 via the audio bus 43.
available. Advanced Video Processor 1 has 7 basics
CPUs that contain functional blocks
The control logic 65 communicates with the host microprocessor 30.
Interface with advanced video processor 1
And constitutes the end of the control line 49,
Input / output data via the data bus 51,
To the host microprocessor 30 via the interrupt line 47
An interrupt operation is performed for this. This CPU control
5 types of host microprocessors 30
The basic operation of can be performed. That is, the bidet
Write data to the RAM 31;
Reading of data, internal of advanced video processor 1
The corresponding data (read from RAM 31) for register 63
Data writing of these advanced video processors 1
Data from some of the internal registers 63
Of the advanced video processor 1
To the internal audio generator 69 contained in the display logic.
It is writing to do. The format and direction of the data transfer is control line 49, especially C
By SW, CSR (top of Fig. 2a) and mode input line
Is controlled. Line CSW is accessed from microprocessor 30
This is a write selection line to the advanced video processor 1.
When this line CSW is activated to a low level,
8 bits on CD0 to CD7 (Fig. 9)
Strobe input to advanced video processor 1.
On the other hand, the line CSR
This is a read selection line to the video processor 1,
Line VSR is activated to a low level,
8-bit data from lines 1 to 7 on lines CD0 to CD7
Data is output and read by microprocessor 30
Perform Line CSW and CSR are both low level.
When activated to the audio generator 69,
Address is specified. The above mode shall be used if the originator of a read or write transfer.
This line is generally used to determine the destination.
(Microprocessor 30)
It has been continued. Advanced video with the above host microprocessor 30
Table 1 shows the data transfer method between processors 1. Video RAM control logic 6 among the basic function blocks
7 (see Fig. 1)
Controls the interface to the video RAM 31
In response to the control signal output to the control line 45, the
Of the video RAM 31 specified via the memory address bus 55
Transferred to the memory address location via the data bus 53
It is responsible for data transfer. The embodiment shown
Then, this data bus 53 is an 8-bit bidirectional bus.
The memory address bus 55 multiplexes this into 8-bit data.
Address bus. The advanced video shown in FIG.
The processor 1 has a dynamic
16K bytes (for example, TMS4416
2 or its equivalent) or 32K bytes
For example, 4 TMS4416s or their equivalents) or 6
4K bytes (for example, 8 TMS4416 or equivalent
Product) can be directly addressed (but TMS4 above)
416 is the Texas Instruments product number
). Internal registers (group) 63 shown in FIG. 1 and FIGS. 2a and 2b
Means two read-only registers, a status register and
And one sprite collision register (Table 2).
And 64 write-only registers (Table 3). This
The function of the write-only register is as follows.
That is, three of these write-only registers are
The operation mode of the advanced video processor 1 is specified.
Therefore, for example, RGB monitor 33 or composite video monitor
Operation modes required to drive the NITA / TV receiver 35
Specify options such as and the format of the video signal output. Ma
Of the write-only registers in the internal register block 63
Six are specified for the advanced video processor 1.
Display memory address mapping register by register
To specify the storage location in the video RAM 31.
It is. In addition, one of the write-only registers
Sprite processor 10 is a text register
Specify the color while operating in default mode. Alone
There are two registers, which are registers for scrolling
Where one is for horizontal scrolling and the other is vertical
It is for directional scrolling. More programmable interrupts
There is only one register, which is generated by all TV monitor signals.
During each horizontal retrace period, the interrupt register
Advanced Video Processor 1 settings can be changed
4 block move addresses and decrement
Counter register is used for each block of video memory.
The specified block of the lock is
32 memory locations.
Is a color palette pilot register.
Up to 16 types per horizontal scan line (from Lavalette)
Specify the colors that can be displayed. Next, the functions of the read-only register are as follows:
It is. That is, the status register contains interrupts and switches.
Simultaneous bright and on any one horizontal scan line
A flag indicating that there is an eleventh spride is remembered.
Have been One for the advanced video processor 1
8 bit status register 28 (Figure 2a) is included
This status register is a microprocessor
30 can read it out. This stay
Table 4 shows the format of the status register 28. interrupt
The flag indicating pending (F) and the sprite
The flag (C) indicating the occurrence of time and the 11th sprite
Flag (11S) and the 11th spr
And a number representing the site number. The status register 28 can be read at any time.
The status bits of the F, C, and 11S flags are
Test may be performed. Read status
Interrupt flag F is cleared by
Bit of frame flag (F) by asynchronous read of
May be reset and lost as a result,
The reading of status register 28 is
Only when the processor 1 interrupt is pending
Good to do. Also, reading of this status register 28
Only one transfer of data is required. Interrupt pending flag (F) The F status flag of the status register 28
Is always set to 1 when there is
Bit is set in one of the following three
In other words, when the movement of the block is completed,
When the grammatical interrupt mode is selected,
When the memory end occurs (vertical retrace period)
It is. The interrupt pending flag is the status register
Data is read from the
Reset to 0 by set signal. Appropriate interrupt enable bit (write-only register
1 IE bit 2 or PIE bit of write-only register 10
When 2) is set to 1, the F status flag
If logic is a logic one, INT is always activated low.
It is. After execution of each interrupt, status register 28
Read the interrupt mode and clear the interrupt mode.
Waits for a new interrupt at the next interrupt
Need to work. Simultaneous flag (C) The C status flag in the status register 28 is 2
When one or more sprites are fired at the same time
Is set to 1. This simultaneous occurrence of sprites
Any two sprites overlap one on the clean
This happens when pixels are shared. in this case,
Some or all of the sprites are off-screen.
Crabs and transparent color sprites are also considered.
Flag exists after completion of reading status register 28
Or advanced video processor 1 is externally reset
After that, it is cleared to logic 0. Note that reading this status register 28
Reset immediately after resetting
You need to make sure that is executed. The advanced video processor 1 controls each simultaneous
The xel position at which point on the screen
Regardless of whether the pixel is
Check. This operation is performed every 1/60 second.
Move two or more pixel positions during a period like
In the state where the
When performing an occurrence check, multiple sprites
Pixels to be overlapped, or multiple pixels
When the sprites are overlapped, the rear sprite image
Display the face on the transparent background part of the front sprite screen
It is possible. The 11th sprite flag (11S) and the 11S status flag in the number status register
Horizontal scan line (line 0-209 depending on the selection mode)
Contains more than 11 sprites,
And whenever the frame flag (F) is logic 0,
Reset to 0. This 11S status flag is the status register
After reading of data is completed, or Advanced Video Processor
After 1 is reset externally, it is cleared to 0. Ma
Whenever the 11S flag is set to logic 1,
The flag is set and becomes effective.
The number of the eye sprite is the lower 5 of the status register 28.
Input to bit. However, this 11th sprite
There is no interruption by setting. Any sprite group (may be one group, multiple groups
It can be determined whether a sprite collision occurred in
Determined by the bright collision detection register 83 (Fig. 2a).
It is. This sprite collision register 83 is an 8-bit register
To determine which sprite group caused the collision
Can be used. Sprite color byte is color
4 bits, 1 leading clock bit and 1
And the remaining three bits are
Used to divide the site into eight groups
Each bit of the unit collision register 83 consists of these eight groups.
Corresponds to one of Therefore, two sprites collide
Must be one of these bits or more.
The upper bit will be set. This sprite
The collision register 83 is stored in the register 30 by the microprocessor 30.
Cleared by reading the register. Splice
The configuration of the above eight groups in the collision register 83
Fig. 6 shows the results. Note that this register 83 is read three times.
Data transfer is required. The sprite processor 10 is an embodiment shown in FIG.
Now, the advanced video process formed on a single chip
It controls the sprite control for all
With this sprite processor 10, one horizontal scanning line
10 sprites (in the case of the embodiment of FIG. 1)
Can be With a conventional video display processor, one run
Was limited to just four sprites per line
is there. The sprite itself may be multicolor or single color.
Half of each horizontal scan line in the site
The color can be different from the light. In addition
Providing a unique sprite coincidence detection method in the embodiment
Has been done. In such a method, somewhere on the display screen
One or two sprites have at least one overlapping pixel
When sharing files, sprites occur simultaneously.
Yes. The splices needed to embody these features
The mapping is built in the video RAM31. Graphics and text processing is graphic
Text processor 60, in this case a microphone
Advanced video processor 1 by microprocessor 30
The setting of the embodiment shown in FIG.
In this case, one of the following display modes is performed. 8 × 8 pixels on a display screen consisting of 256 × 192 pixels
The first uses two color resolution for each block of cells
Graphics display mode. 8 × 1 pixels on a display screen consisting of 256 × 192 pixels
A second graphic using two colors for each block of cells
Display mode. 4 × 2 pixels on a display screen consisting of 256 × 192 pixels
Third graphics using two colors for each block of cells
Display mode. At a full pixel resolution using 512 x 192 pixels, 8
High resolution using two colors for each block of × 1 pixel
4th graphics display mode. Using all bitmaps with 256 × 210 pixel resolution
Fifth graphics display mode. First text mode using 24 rows and 40 columns of text. Second text mode using 24 rows and 80 columns of text. However, all of the fifth graphics display modes
Graphics display and text other than bitmap mode
In the text mode, all tables are driven. The audio generator 69 in the embodiment of FIG.
This function generates audio in the
Devices are, for example, Texas Instruments
It can be replaced by the SN764889 device and so on. this
The circuit consists of three programmable tone generators and one
120 to 100,000H with programmable noise generator
z frequency response band and 15 dB from 2 dB to 28 dB in 2 dB steps.
It has a programmable attenuation step of. FIG. 2 referred to next is the advanced video shown in FIG.
FIG. 2 is a block diagram of a processor 1. As described earlier with reference to FIG.
Like the internal register 63, two read-only registers
Data and 64 write-only registers. In the figure,
In addition, 16 9-bit registers each corresponding to 16 colors
A certain color palette register 2 is included. these
Color palette register 2 is a sprite control logic
59 (Figure 2b) and the graphics / text
First, second, and third color buffers that form part of Sessa 60
61, 62, 64 (Fig. 2b) and borders for program colors
Color register 29 (Fig. 2b) and text color register
Address 30. In addition, the advanced video processor 1 is shown in FIG.
In the embodiment shown in FIG.
Fetches the color of each character,
Not in mode. The above color palette register 2
Is addressed by the color palette read logic 65.
The stored contents of each color palette register are D / A
It is input to the conversion logic 67. This D / A conversion logic 67
Is the color palette and video output logic shown in Fig. 1.
R, G, B colors on the RGB monitor 33
Supply a signal or a video coded RF module
The color difference signal is supplied to the data 37. In addition, Advan
Depending on the configuration of the video processor 1, the above D / A conversion logic
The output of the block 67 is output to the RGB bus 39 or the color difference bus 41.
It is forced. The color palette register 2 is registered as shown in Table 3.
These include the color palette registers R32 to R63
The input of the color code to the star 2 is the color palette
Controlled by write logic 3. This palette
Tables 5 and 6 show the formats. The pallet is
It consists of 16 9-bit registers and uses this
This allows the user to display 16 of the 512 colors on the screen
Can be displayed at the same time. External reset
For color difference output as shown in Table 7 based on the bit signal
Initialize the color palette with the default value of
Now. Horizontal counter or programmable logic array
(PLA) 5 counts the position on the horizontal scanning line,
Decode instructions based on the position of the scanning beam
D / D to specify the position and color of the sprite
Generates timing signal for A conversion control logic 67
It is. Also, a programmable logic array as a vertical counter
B (PLA) 6 counts the row position on the scanning line, and
After decoding, the horizontal counter PLA is
In the same way as for data,
Generate a timing signal for FIG. 2 shows
Although not shown above, the above horizontal counter PLA5 and vertical counter PL
A6 is combined with the following logical functions. The color priority logic 7 first determines the color
29, text color logic 30, color buffalo
Gick 61, 64 and sprite control logic 59
Priority of the color logic to be used. In this case
Priority is given to the background pattern and sprite in the active area.
If there is, sprite display, further sprites overlap
In the case of the sprite display in the
Automatically determined. In addition, three or more
Subordinate colors and seven types of motions
The color priority log to the video processor 1.
Specify from the check. The interrupt logic 8 is based on a timing signal interrupt.
Interrupts the host microprocessor 30
And execute input to one of the registers. In addition,
In Table 8, "IE" is the interrupt enable of register 28
Bit 2 and “F” are interrupt registers in the status register.
Flag bit 0, and “PIE”
Indicates the Gramable Interrupt Enable bit 2 respectively
Yes. Interrupt for any horizontal scan or scan line
The programmable interrupt logic 29 is shown in FIG.
In the embodiment, an 8-bit register is provided.
The contents of the memory are compared with the contents of the vertical counter PLA6.
As a result, the scan line is executed by the host microprocessor 30
Requires interrupting the program sequence inside
If this is known, the interrupt logic 8
Issue a request for The sprite control logic 59 is used to
Control the vertical position from the vertical counter PLA6.
Check the sprite horizontal position pattern and
And fetch color data. The sprite control logic 59 (FIG. 2b) is used in this embodiment.
Processes and checks all 32 sprites
To determine whether the position is valid. Next
When the sprite is loaded on the scan line of
The sprite control logic 59 has the number of the sprite.
Or load the vertical position on the sprite stack 11 (load)
Is performed. Sprite stack 11
Output to the RAM address bus 69 and output to the video RAM 31
Used for search to read back display data once written
Is done. The CPU register 12 (Fig. 2a)
Data bus 51A included in advanced video processor 1
Via the host microprocessor 30 to the video RAM 31
Interface. The name register 13
Enter the background pattern name (8-bit number)
Remember, this allows for the next character to be displayed
Fetch pattern bytes and color bytes of. Further
The address register 14 has a host microprocessor 30
Command (even if it is a read command or a write command)
Address the video RAM 31 based on
In addition, advanced video processor 1 and internal register 63,
Address color palette register 57 (Fig. 1)
It is. The scroll logic includes a vertical state register 2
2, vertical scroll register 23, character counter 24, horizontal scroll
Includes roll register 25 and horizontal state register 26
Thing. The first to fourth graphic modes and the first and second graphic modes
4 screens for the text mode
Is divided into. These characters are used when the TV is horizontal.
As the vertical scanning progresses, the character
Counter 24. Also the above horizontal state register
26, which pixel of each character is currently being displayed
Is determined. Further, the vertical state counter 22
Determine which line of each character is currently being displayed.
is there. The fifth graphics mode is bitmapped
Will not be split into characters. In this mode,
As the horizontal and vertical scanning of the levi progresses,
Horizontal state register 26, vertical state register 22, and
And the character counter 24 counts for each pixel.
These counters point to the address of video RAM 31
This is used for. On the other hand, horizontal scroll register
The star 25 includes an 8-bit number, and the 8-bit number
The horizontal scroll position of the screen. This water
The stored contents of the horizontal scroll register 25 are the
Initially, the horizontal state register 26 and character counter 24
Is loaded into. Change the starting position of these counters
This allows the screen to be placed in up to 256 different horizontal positions
You can scroll. The vertical scroll register 23 also contains an 8-bit number.
And the vertical scroll of the screen
Determine the position of the file. This vertical scroll register 23
The contents are stored in the vertical state register 22 at the start of each scan.
And loaded into character counter 24. Of these counters
Up to 256 screens by changing the starting position
It is possible to scroll to different positions of. Base registers 15, 16, 17, and 18 are individual sections of video information.
Defines the storage location in the video memory 31 where the image is stored
It is a register. Of these registers, the name base register
Register 15 defines the location of the name table in memory,
Color base register 16 defines the location of video color information.
The pattern base register 17 maps each character.
To determine the position of the pattern bits
The position register 18 stores the sprite pattern and sprite
Of sprites, sprite horizontal position, sprite vertical position, etc.
It defines the storage space. Further command register
Reference numerals 19, 20, and 21 denote registers for controlling the operation mode of the advanced video processor 1. The status register 28 is connected via the data bus 51A.
The following interrupt information to the host microprocessor 30.
Send a status signal to reflect. In other words, the occurrence of a programmable interrupt
The number of sprites in use is 10 or more, and two sprites
Site collision, eleventh splice on scan line
Information such as a 5-bit addition status bit for the
The CPU control logic 65 is the host microprocessor 30
Output an interrupt signal to the internal video register 63
Or interrupt or read to video RAM 31
Write and read commands, if any
Or receives a mode command indicating the operation (mode)
It is. Plank name register 27 (two 16-bit registers
From one section of memory to another
Used to move data to parcels. These two
Should move to one of the plank name registers 27
The number of bytes is stored, the other is the read memory location
Has been done. The destination of the write memory is address register 14.
Is located within. The color buffer 60 has a 3-byte pattern plane
Color information is stored in the buffer 64
Color output to bus 86 is stored and output at any time
It is in a state where it can be done. This buffer 64 is 1 byte
That stores the information of two or four types of 4-bit color
Corresponding to the first to fourth graphics display modes.
When the pattern bit is 1, this color byte
Are output to the color bus and the least significant bits of
Bit is 0, the most significant bit of this color byte
Are output to the color bus. Fifth graphics
Display mode (1 or 0 bit is mapped
Mode), the least significant bits are displayed.
To be the first color pixel (eg, "1")
The most significant bits are the second color pixel
(For example, “0”). On the other hand, buffers 61 and 62
This is a buffer for storing time, and the stored contents are stored in buffer 64.
You will be empowered. The pattern buffer 84 stores
Logic 1 and 0 that determine whether to display
Therefore, the output is input to the pattern shift register 586.
Are shifted in series. This pattern shift register
Output of the color priority logic 7 by the output of the
The color signal from the buffer 64 is changed according to the force.
Is output to step 86. Sprite register 100 (Figure 2a) is sprite horizontal
Pointer 82, sprite pattern register 81, sprite
Color register 80 and sprite simultaneous selection logic
Including 70. This operation is equivalent to 10 horizontal scan lines.
This is repeated 10 times for sprites. Supra above
The horizontal sprite position is assigned to the site horizontal counter (pointer) 82.
Is decremented (reversely stepped) to zero value
It is. Next, the sprite pattern register 81
Start shifting columns. In this case, if the bit is 1,
The sprite color signal is output to the color bus 86.
If it is 0, leave it as it is. The above sprite color register 80 is a sprite color
4 bits for initial clock, 1 bit for initial clock, and
It has three bits for indicating a light group.
It is. The sprite coincidence detection logic 70 (Fig. 2a)
Two simultaneously from the bright pattern register 81 (Fig. 2a)
Or logical 1 of more sprites is shifting
To determine if such a condition has occurred.
Two or more sprites
Collision on the screen. These sprites are 10
3 bits stored in the sprite color registers 80
And the bit corresponding to the sprite group
Is set in the sprite coincidence register 83. However
In this case, these sprites are shadowed
When this bit is set, this bit is not set. This
The three bits in the sprite color register 80
Decode into 8 groups and sprite each group
Can correspond to 1 bit of coincidence register 83
. Next, a description will be given with reference to FIG. Figures 1 and 2
The coincidence detection device in the embodiment of the present invention
This is especially effective when applied to games. Say here
A video is, for example, a video that belongs to sprite group 1.
Spaceship 110 as Prite 1 and Sprite Group
Multiple locations as sprites 2,3,4 assigned to
Flying on a boat 112, sprite 8 of group 4
Disk 113, and sprite flow belonging to group 3
The star cluster 115, 116, 117 uses these sprites to
Execute the system. In this case, for example, a sprite
One of the rocket ships 112a, b, c belonging to group 2 is assigned to another location
And sprites occur simultaneously
Is detected and the sprite coincidence register 83 (Fig. 2a)
Bit 2 is set. Space Ship 110
Collision with one of the 112 rocket ships (missiles)
In the same way, the simultaneous occurrence of sprites is detected,
Bits 1 and 2 of write simultaneous register 83 are set
Is performed. The host microprocessor 30
Reads out the simultaneous register 83 and sets bit 1
Performing a check on spaceship 11
Checking if 0 collided with another object
it can. Figure 5 shows a multicolor sprite. Sprite is horizontal
Can have different colors on a scan line. Fifth
The sprite on the left of the figure consists of a hat 121, eyes 123, mouth 125, and nose 126.
And have four different colors.
It is a sprite. On the other hand, the sprite in the center of FIG.
Surface sprite 127, which is
23, mouth 125, nose 126 on the same horizontal scan line
Therefore, a sprite that is separate from the sprite on the left in Fig. 5
Must be rendered as. Sprite 1 and sprite
2 is combined with the
Prite 129 is completed. The sprite coincidence detection logic 70 shown in FIG.
A sprite when one of the sprites
Output to register 83. Figure 7 is represented by graphics and alphabets
Data (also referred to as video text)
In order to be able to produce
The video text system shown in the figure is also shown.
Model 235, data access means 234 and UART (U
niversal Asynchronous Receiver / Transimitter) 233
Two-way communication via the standard transmission line 237 used.
It has become. Microprocessor 30
Interface with ROM memory 231 and RAM memory 232
And an operator interface via keyboard 236.
-Face. In addition, the advanced video processor
The first RAM is four RAMs representing the video RAM 31, that is, the seventh RAM.
Connected to A RAM, B RAM, C RAM, DRAM as shown
Yes. These four RAMs are preferably Texas
By using TMS4116 manufactured by Instruments,
Providing the memory required to store video data.
Wear. Video data is sent to the advanced video processor 1.
It is output as a more constant sequence and then video
Each horizontal scan line is encoded by the encoder 37
Dot data for the TV receiver
It becomes possible to visually recognize it with the machine 35. This TV receiver 35
Required for refreshing and displaying images on a computer
All information and synchronization signals are transferred to the video display
Supplied by service 1. FIG. 8 shows an example of the operation through the DMA controller 103 and the DMA pin 101.
Here is an example of direct memory access (DMA) method.
This DMA pin 101 allows the host microprocessor 30
The video RAM31 can be accessed directly. This pin is accessed by microprocessor 30
If not, it will be in the logic 1 state. Various embodiments of the present invention have been described above.
The device and method according to Ming are limited to these examples.
Rather, various additions or changes may be made to the described embodiment as appropriate.
Needless to say, it can be added.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a video display system according to the present invention. FIG. 2 (FIGS. 2a and 2b) is a block diagram showing an advanced video processor in the system shown in FIG.
FIG. 3 is a schematic diagram showing a state immediately before a collision between two sprites, FIG. 4 is an explanatory diagram when a sprite is used in a computer game, and FIG. 5 is a diagram when a graphic is displayed using a sprite. FIG. 6 is a diagram showing a method of allocating bytes and bits in the present invention, FIG. 7 is a block diagram showing another embodiment of the present invention, and FIG. 8 is a function of direct memory access to an advanced video processor according to the present invention. FIG. 3 is a block diagram showing a configuration in the case of using. 1 advanced video processor, 10 sprite processor, 30 host microprocessor (CPU), 31 video RAM, 33 color (RGB) monitor, 35 composite video monitor or television receiver, 37 ... Video encoder or RF modulator, 57 ... Color palette and video output logic, 60 ... Graphics and text processor, 63 ... Internal registers, 65 ... CPU (microprocessor) control logic, 67 ... Video RAM control Logic, 69 ... Voice generator.

Continuation of front page       (56) References JP-A-53-33741 (JP, A)                 JP-A-53-125732 (JP, A)                 JP-A-55-123732 (JP, A)                 JP-A-56-94390 (JP, A)                 JP-A-56-94391 (JP, A)                 JP-A-56-43977 (JP, A)                 JP-A-56-94389 (JP, A)                 JP-A-56-150039 (JP, A)                 JP-A-57-11390 (JP, A)                 JP-A-58-46978 (JP, A)                 JP-A-58-97378 (JP, A)

Claims (1)

(57) [Claims] A video display processing device, comprising: a memory port for reading or writing display data and a color code from an external memory; and a color corresponding to a pixel of the scanning linear video display device connected to the memory port, from the external memory. An image processing apparatus for continuously reading data through the memory port; a sprite horizontal position; and sprite color data corresponding to a moving image. The image processing device stores the moving image corresponding to a horizontal position of a scanning line of the video display device. The at least one sprite register for outputting the sprite color data, an input, a plurality of color palette registers, and an output, wherein the plurality of color palette registers each include a color code capable of specifying a number of colors exceeding the number. A color to store and output through said output a color code corresponding to the color data received at said input A palette, the image processing device, the at least one sprite register, and the color palette connected to the color palette, and when there is no sprite color data output of the sprite register, the image processing device sends the color to the input of the color palette. When data is supplied, and when there is a sprite color signal output from any one of the sprite registers, the sprite color data is supplied from a sprite register having the highest priority within a predetermined sprite priority to an input of the color palette. A color priority logic circuit, an input connected to the output of the color palette, and a digital-to-analog converter having an output and outputting an analog color signal corresponding to the color code received at the input; An image processing device and the at least one sprite register; When the horizontal line next to the scanning line of the display device includes a moving image, the sprite horizontal position and sprite color data of the moving image are stored in the corresponding sprite registers, so that one moving image has a different sprite color for each different horizontal line. A video display processor comprising: sprite control logic that can include data.