JP2887795B2 - Driving device for solid-state imaging device and endoscope scope having the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention is to transmit a horizontal and a vertical clock from an operation side having an oscillator to a solid-state imaging device such as a CCD, and the solid-state imaging device The present invention relates to a driving device of a solid-state imaging device for driving a camera and an endoscope provided with the same.

(Prior art) For example, a CCD image pickup device (hereinafter simply referred to as “CCD”) mounted on the distal end of a scope of an electronic endoscope device controls the accumulation and transfer of signal charges by a clock pulse given from the operation side. Is done.

FIG. 11 is a configuration diagram showing a conventional CCD 1 and its driving device. The CCD 1 shown in FIG. 1 has a four-phase drive for vertical charge transfer and a two-phase drive for horizontal charge transfer, and the vertical clock pulse (V1
-V4), the horizontal clock pulses (H1, H2), and the reset pulse (RS) are output, amplified by the driver 3, and then supplied to the CCD1. Then, the video signal (OS) obtained by the control based on each pulse signal is supplied to the signal processing unit 4 on the operation side via the amplifier 32, and the image data is generated and displayed on a display device (not shown).

(Problems to be Solved by the Invention) However, in the above-described conventional apparatus, in addition to the reset pulse and the video signal cable, the horizontal and vertical clocks for controlling the horizontal transfer and the vertical transfer of the solid-state image sensor are controlled. Since the number of cables corresponding to the number of phases is required to connect the operation side and the solid-state imaging device side, there is a problem that the number of cables connecting the operation side and the solid-state imaging device side increases.

In addition, especially in an endoscope using a solid-state imaging device, the number of cables connected to the solid-state imaging device is large, so that the diameter of the endoscope scope becomes large, operability is reduced, and insertion time during insertion is reduced. There was a risk that the burden on the subject would increase.

In view of the above problems, an object of the present invention is to provide a driving device for a solid-state imaging device capable of reducing the number of cables connecting the operation side and the solid-state imaging device side.

Another object of the present invention is to reduce the number of cables connecting the operation side and the solid-state imaging device side, thereby reducing the diameter of the endoscope scope, improving the operability of the endoscope scope, and improving It is an object of the present invention to provide an endoscope which can reduce the burden on the user.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention drives a multi-phase horizontal clock and a vertical transfer for driving a horizontal transfer from an operation side to a solid-state imaging device. In the solid-state image sensor driving device that transmits a multi-phase vertical clock and reads an image signal from the solid-state image sensor, the horizontal clock of each different phase and the vertical clock of each different phase are multiplexed and the A plurality of clock transmitting means for transmitting to the solid-state imaging device, and a determination signal transmitting means for transmitting a determination signal indicating whether a clock transmitted by the clock transmission means is a horizontal clock or a vertical clock from the operation side to the solid-state imaging device And synchronizing the clocks transmitted by the plurality of clock transmission means in synchronization with the determination signal into a horizontal clock and a vertical clock. A clock separating means for releasing a driving device for a solid-state imaging device according to subject matter that has a.

Further, the present invention, from the operation side to the solid-state imaging device,
In a solid-state imaging device driving device that transmits a multi-phase horizontal clock and a multi-phase vertical clock to read an imaging signal from the solid-state imaging device, the first phase horizontal clock having a different phase and the phase having a different phase are different from each other. A plurality of clock transmitting means for multiplexing a vertical clock having a second polarity different from the first polarity and transmitting the multiplexed vertical clock from the operating side to the solid-state imaging device; and clock pulses transmitted by the plurality of clock transmitting means. Monitoring means, and when at least one of the clock signals has the second polarity, a discriminating means for discriminating a vertical clock transmission period, and the plurality of clock transmitting means transmit signals based on a discrimination result of the discriminating means. And a clock separating means for separating a clock into a horizontal clock and a vertical clock. .

According to another aspect of the present invention, there is provided an endoscope including the driving device for the solid-state imaging device.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 2 is an explanatory diagram showing the operation principle of the interline transfer type CCD.

In FIG. 1, a photoelectric conversion cell 10 is a subject (not shown).
Is converted into a charge signal, and the charge signal is transferred to the vertical CCD 11 during the vertical blanking period. Thereafter, this charge signal is applied to the vertical CCD 11 and the horizontal CCD 12.
After being converted into a voltage signal by the charge / voltage converter 13, and then output as a video signal.

At this time, the vertical CCD 11 and the horizontal CCD 12 require a two- to four-phase transfer clock to transfer the electric charge.
In this example, the four-phase vertical clocks (V1 to V4) and the two-phase horizontal clocks (H1, H2) are the vertical CCD11 and the horizontal CCD, respectively.
It is supplied to CCD12. The reset pulse RS gives a timing for converting the charge signal into a voltage signal.

FIG. 3 is a time chart of each clock pulse.
The signal H / V shown in the figure is outputted from a timing generation circuit described later, and outputs a signal of "L" level when the CCD is in vertical transfer and an "H" level when it is in horizontal transfer. Then, it is determined whether the transfer is vertical transfer or horizontal transfer.

Then, in the signal H / V, the electric charge is transferred between the photoelectric conversion cell 10 and the vertical CCD 11 shown in FIG. In the section T2 of FIG. 3, the signal charge is reduced by 1 in the vertical direction.
The line is shifted by the amount of the line.
, The signal charges are shifted in the horizontal direction.

As is apparent from FIG. 3, the vertical transfer and the horizontal transfer are performed alternately, and the two transfers are not performed simultaneously. That is, when signal charges are being transferred by the vertical CCD 11 shown in FIG. 2, the horizontal CCD 12 is stationary, and when signal charges are being transferred by the horizontal CCD 12, the vertical CCD 12 is not.
CD11 is stationary.

Therefore, when a CCD is mounted on the distal end of a scope like an electronic endoscope and a clock pulse is transmitted from the operating side to drive the CCD, one vertical clock (for example, V1) and one horizontal clock (for example, H1) can be superimposed, and transmitted from the operating side to the tip using the same cable.

FIG. 1 is a configuration diagram showing a preferred embodiment of a driving device for a solid-state imaging device configured by applying such a method.
As shown in the drawing, the driving device includes a timing generation circuit 2.
, Drivers 5 and 7, analog switch 6, cable C
1 to C5, which control the operation of the CCD 1 as a solid-state imaging device.

The timing generation circuit 2 generates a timing signal of a vertical clock and a horizontal clock, and receives a timing signal from an operation side.
The H / V signal for determining whether the clock transmitted to the CCD 1 is a horizontal clock or a vertical clock is output.

The driver 7 superimposes one vertical clock and one horizontal clock and transfers them from the operation side to the CCD1 side. The transmitting unit 7a superimposes and transmits the clocks V1 and H1.
And a transmitting unit 7b that superimposes and transmits the clocks V2 and H2,
A transmitting unit 7c for superimposing and transmitting the clock V3 and the RS signal,
The transmission unit 7d transmits the clock V4 independently. The transmission units 7a to 7c have MOS type FETs Q1 to Q6, and output superimposed clock pulses by ON / OFF operation of each FET. The transmitting unit 7d outputs a clock pulse in the same configuration as in the related art.

Driver 5 is output from timing generation circuit 2
It amplifies and outputs the H / V signal.

The cables C1 to C5 transmit signals output from the drivers 5 and 7 from the operation side to the CCD1 side, and are connected to the analog switch 6 on the CCD1 side.

The analog switch 6 switches contacts in synchronization with the H / V signal and separates the superimposed vertical clock and horizontal clock, and the vertical clock and RS signal. Each separated clock signal and RS signal are separated. The signal is supplied to CCD1.

 Next, the operation of the present embodiment will be described.

Now, taking the transmission section 7a of the driver 7 as an example, the FETs Q1 and Q2 are controlled to be turned on / off during vertical clock transmission. That is, if FET Q1 is turned on and all other FETs are turned off,
The cable C1 is driven to +8 [V]. When the FET Q2 is turned on and all the other FETs are turned off, the cable C1 becomes -8.
Driven to [V].

In addition, since the switching of the horizontal clock pulse is very fast, two H level and two L level FETs are provided.
Is switched by on / off control. That is, FETQ3,
When Q5 is turned on and all other FETs are turned off, cable C1 is driven to +9 [V], and cable C1 that turns on FETs Q4 and Q6 and turns off all other FETs is at 0
[V].

FIG. 4 is a section T2, T3 of the time chart shown in FIG.
It is the figure which expanded and showed the part. Since the clock pulse output from the transmission unit 7a is obtained by superimposing the clock V1 and the clock H1, the clock pulse (V1 +
As shown in H1), during horizontal transfer (when the H / V signal is at “H” level), the waveform becomes the same as that of the clock H1, and during vertical transfer (when the H / V signal is at “L” level). Is clock V1
And the same waveform.

Then, the superimposed signal (V1 + H1) output from the transmission unit 7a
Is transmitted to the CCD1 side via the cable C1 and supplied to the analog switch 6. The H / V signal output from the timing generation circuit 2 is amplified by the driver 5 and then supplied to the analog switch 6 via the cable C5.

In the analog switch 6, when the H / V signal is at "L" level (at the time of vertical transfer), the contacts 6a to 6d are connected to the cables C1 to C4 and the contacts 6e to 6g are connected to the cable.
Connect to the opposite side from C1 to C3. As a result, CCD1 terminal V1
Is cable C1, terminal V2 is cable C2, terminal V3 is cable C
3. Terminal V4 is connected to cable C4. Also, the terminal of CCD1
H1 is connected to +9 [V], terminal H2 and RS are connected to GND.

On the other hand, when the H / V signal is at "H" level (at the time of horizontal transfer)
In the analog switch 6, the contacts 6a to 6d are connected to the cable C1.
To the opposite side to C4 and connect the contacts 6e to 6g to the cables C1 to C3.
Switch to the side. As a result, CCD1 terminal V
1, V4 is connected to GND, and terminals V2, V3 are connected to -8 [V]. The terminal H1 is connected to the cable C1, the terminal H2 is connected to the cable C2, and the terminal RS is connected to the cable C3.

Therefore, in the CCD1, clock signals are supplied in the same manner as when a cable is provided for each clock signal, so that the vertical and horizontal charge transfer shown in FIG. 2 is performed smoothly. Become.

In this manner, in the present embodiment, the clock signal transmitted from the operation side to the CCD1 side is multiplexed, so that the number of cables connecting the two can be reduced. For this reason, in the scope used for the electronic endoscope, the diameter can be reduced, so that the operability is improved and the pain given to the patient can be reduced.

In this embodiment, the vertical clock V4 is configured to be transmitted independently. However, as shown in FIG. 5, the cable C4 may be bidirectional and multiplexed with a video signal (hereinafter, referred to as an OS signal). It becomes possible.

That is, since the OS signal is output only when CCD1 is in the horizontal transfer period, it does not overlap with the vertical clock V4,
If switching is performed in synchronization with the H / V signal of the contacts 6d and 6h of the analog switch 6, the vertical clock V4 and the OS signal can be connected to one cable.
Can be sent on C4. In this case, the OS signal is 7 to 12
[MHz] while the vertical clock V4 is about 15 [KHz], so there is a considerable difference between the two frequencies. Therefore, the vertical clock V4 and the OS signal can be separated by the capacitor C and the resistor R2 provided on the operation side, and the input amplifier 20 can capture only the OS signal. The diodes D1 and D2 are connected to the input amplifier 20 for the vertical clock V4.
To avoid saturation.

According to such a configuration, the number of cables can be further reduced. In the example shown in FIG. 5, the vertical clock V4 and the OS signal are separated by using the capacitor C and the resistor R2. However, as shown in FIG.
A switch 21 is provided on the input side of the input amplifier 20, and this is set to H / V
If it is configured to be turned on only during the horizontal transfer period in synchronization with the signal, the input amplifier 20 can capture only the OS signal.

In the embodiment described above, the analog switch 6
7 contacts from 6a to 6g (when OS signals are multiplexed, contacts
Although the configuration has eight (including 6h), as shown in FIG. 7, it is also possible to separate the multiplexed signal at the four contacts 6i to 6l. In this case, each terminal V1, V2,... Of the CCD1 is connected to each voltage via a high resistance R3. The high resistance R3 has a value that is as large as that when the signal from the cables C1 to C4 is supplied (when the contact of the analog switch 6 is connected and cut off when the signal is supplied). When not performed (when the contact of the analog switch 6 is open), the voltage of the terminal is maintained to be constant, so that the signal can be switched with a small number of contacts.

FIG. 8 is a time chart of signals transmitted by the cables C1 to C4, and FIG. 9 shows an enlarged view of the periods T2 and T3 shown in FIG. As is apparent from FIGS. 8 and 9, when the H / V signal is at the L level (during vertical transfer), at least one of the signals (V1 + H1) to (V4 + OS) always takes a negative value. Has become.

When the H / V signal is at the H level (at the time of horizontal transfer)
, Each signal (V1 + H1) to (V4 + OS) does not become a negative value. Therefore, as shown in FIG. 10, the output signals from the cables C1 to C4 are taken out,
30 and compare this with a voltage of -0.5 [V]. Then, the output signal of each comparator is supplied to the NOR gate 31, and the output signal is used as the H / V 'signal, which is supplied to the analog switch 6 instead of the H / V signal.

According to such a configuration, it is not necessary to transmit the H / V signal from the operation side to the CCD1 side, and the number of cables can be further reduced. The diameter can be made smaller. The reason why the comparison voltage of each of the comparators 30 to 30 is -0.5 [V] in FIG. 10 is to prevent malfunction due to the influence of noise or the like.

[Effects of the Invention] As described above, according to the present invention, since the horizontal clock and the vertical clock transmitted from the operation side to the solid-state imaging device are multiplexed, the operation side and the solid-state imaging device are connected. There is an effect that the number of cables can be reduced.

Further, according to the present invention, the number of cables for connecting the operation side and the solid-state imaging device side can be reduced, so that the diameter of the endoscope scope can be reduced, and the operability of the endoscope scope is improved. And the burden on the subject can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a time chart of each clock signal applied to the CCD, FIG. 4 is an enlarged view of the time chart shown in FIG. 3, and FIG. 5 is a multiplexed OS signal. FIG. 6 is a configuration diagram showing a modification of the example shown in FIG. 5, FIG. 7 is an explanatory diagram showing a configuration in which the number of contacts of the analog switch is four, and FIG.
FIG. 9 is a time chart of each multiplexed signal, and FIG.
FIG. 10 is an enlarged view of the time chart shown in FIG. 10, FIG. 10 is a configuration diagram showing a modification of the present invention, and FIG. 11 is a configuration diagram showing a conventional example. 1 CCD 2 Timing generator 5 7 Driver 6 Analog switch 21 Switch 30 Comparator 31 NOR gate C1 to C5 Cable V1 to V4 Vertical clock H1, H2: Horizontal clock RS: Reset signal OS: Video signal

Claims (4)

(57) [Claims] A solid-state image sensor for reading an image signal from the solid-state image sensor by transmitting a multi-phase horizontal clock for driving horizontal transfer and a multi-phase vertical clock for driving vertical transfer from the operation side to the solid-state image sensor; In the image pickup device driving device, a plurality of clock transmitting means for multiplexing a horizontal clock of a different phase and a vertical clock of a different phase and transmitting from the operation side to the solid-state imaging device; A discriminating signal transmitting unit for transmitting a discriminating signal indicating whether a clock to be output is a horizontal clock or a vertical clock from the operation side to the solid-state imaging device; and a clock transmitted by the plurality of clock transmitting units in synchronization with the discriminating signal. Clock separation means for separating the clock signal into a horizontal clock signal and a vertical clock signal. Drive. 2. A solid-state imaging device driving device for transmitting a multi-phase horizontal clock and a multi-phase vertical clock from an operation side to a solid-state imaging device and reading an imaging signal from the solid-state imaging device. A plurality of clock transmitting means for multiplexing a horizontal clock having a first polarity of a phase and a vertical clock having a second polarity different from the first polarity and having a different phase, and transmitting the multiplexed signals from the operation side to the solid-state imaging device; A monitoring unit that monitors each clock pulse transmitted by the plurality of clock transmission units and determines that the period is a vertical clock transmission period when at least one of the clock pulses has the second polarity; Clock separating means for separating the clocks transmitted by the plurality of clock transmitting means into a horizontal clock and a vertical clock based on the result. A driving device for a solid-state imaging device. 3. When the number of phases of the vertical clock is larger than the number of phases of the horizontal clock, a vertical clock which is not multiplexed to the horizontal clock from among the multi-phase vertical clocks and an image obtained from the solid-state imaging device. 3. The method according to claim 1, wherein the signal is bidirectionally multiplexed and transmitted / received.
A driving device for a solid-state imaging device according to claim 1. 4. An endoscope comprising the driving device for a solid-state imaging device according to claim 1. Description: