JP2889516B2 - Method for manufacturing multilayer wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a multilayer wiring formed by a build-up method in which a plurality of wiring layers are sequentially laminated on a base material via an insulating layer. The present invention relates to a substrate manufacturing process.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a multilayer wiring board includes a bonding method in which a wiring layer is formed on a plurality of base materials, and an insulating sheet is interposed between the base materials and bonded. An insulating layer is formed on a substrate on which a wiring pattern is formed, and a lamination structure is formed by sequentially repeating the formation of the insulating layer and the wiring pattern, such as forming a wiring pattern on the insulating layer. There are several build-up methods.

According to the latter build-up method, unlike a bonding method requiring a bonding step, there is no need to overlap a plurality of base materials or insulating sheets, so that a thin multilayer wiring board can be formed at a high density and relatively easily. Can be formed. A method of manufacturing a multi-layer substrate of this type is disclosed in
392, JP-A-61-224397, JP-B-1-39236, JP-A-3-3298, and the like. In the method of manufacturing a multilayer wiring board by such a build-up method, since each of the insulating layers and the wiring layers is sequentially formed by a thin film forming method, a large number of wiring layers can be formed in a thin substrate, and a circuit and an electronic circuit can be formed. Components can be mounted at high density.

[0004]

However, when circuits are formed at a high density on the multilayer wiring board formed by the above-described build-up method, electromagnetic interference between the layers occurs, and the capacitance between the wirings is reduced. Problems such as high-frequency characteristics and withstand voltage of the circuit arise due to factors that cannot be ignored, such as a decrease in insulation resistance.

[0005] In particular, in a method of manufacturing a multilayer wiring board of a build-up type, a conductive layer between different wiring layers has a structure in which an upper wiring layer is formed on an exposed lower wiring layer without forming an insulating layer in advance. However, since these conductive connection portions have a structure in which a considerably large conductor is filled inside the surrounding insulating layer, it is considered that this portion has a large electromagnetic effect.

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer wiring board having a high frequency characteristic and a good withstand voltage even if the multilayer wiring board has a high-density internal circuit formed by build-up. It is an object of the present invention to realize a manufacturing method capable of manufacturing the same.

[0007]

Means for solving the above-mentioned problems The present invention has been made to solve the above-mentioned problem by providing a multilayer wiring board formed by a method of sequentially laminating a plurality of wiring layers on a base material via an insulating layer. In the manufacturing method, after forming a different-layer conductive connection structure in which different wiring layers are conductively connected through openings formed in the base material or the insulating layer, an insulating material is provided inside the openings so that the surface of the substrate is substantially formed. Providing a step of filling so as to be flat, thereafter, applying an insulating resist on the surface, opening only the region connected to the upper layer, further applying the insulating resist again and opening only the region, that many coating material which contains a number μm approximately fillers on the insulating resist is applied to avoid the region, polished lightly buff the surface after curing by heating or light irradiation By removing the hardened layer near the surface, and then performing sandblasting using abrasive grains of about several tens of μm to remove the polishing traces on the surface to form a uniform rough surface and buried near the surface The filler is then exposed, and then the filler is eluted by soft etching to form fine irregularities on the surface, and two plating layers are sequentially formed on the surface to provide a conductive connection portion, and a photolithography technique is used. The wiring layer is formed in a predetermined pattern by etching the plating layer.

In this case, the step of filling the insulating material is a step of selectively applying the insulating material in the opening and then mechanically flattening the surface on which the insulating material is applied. Is preferred.

According to the first aspect, after the conductive connection structure is formed in the opening of the base material or the insulating layer, the inside of the opening is filled with an insulating material, so that reliable conductive without increasing the amount of conductor. The connection can be made, the capacitance between the wiring layers can be reduced, and the insulation resistance can be increased. Therefore, the high-frequency characteristics and the withstand voltage of the substrate can be improved, and the noise resistance can be improved. Further, by filling the insulating material so as to be substantially flat, the upper insulating layer and the wiring layer can be formed on a flat surface, so that the cross-sectional structure of the substrate can be matched and wiring defects and the like can be prevented.

According to the second aspect, the step of filling the insulating material can be easily performed with simple equipment by selectively applying the insulating material and then mechanically flattening the surface. Can be. Here, screen printing can be used as a method of application, and polishing using a belt sander, a buff, or the like can be used as a method of mechanically flattening.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be described with reference to the drawings. In this embodiment, first, as shown in FIG. 1A, a through hole 10a is formed in the base material 10. Next, as shown in FIG. 1B, copper plating is performed on the front and back surfaces of the base material 10. At this time, the base material 10
The plating layers 11 and 12 are respectively formed on the front and back surfaces of the through hole 10a.
Is electrically connected to the plating layer 13 formed on the inner surface of the substrate.

Next, as shown in FIG.
The insulating material 14 is filled into the through hole 10a with a metal mask such as a stainless steel plate having an opening corresponding to the opening 0a interposed therebetween. This filling step may use screen printing. In general, as the material of the insulating material 14, various resins such as various resins dissolved in a solvent or the like, a photocurable resin, or a material mainly containing a thermosetting resin or the like can be used. . In particular, the use of a thermosetting resin containing an epoxy resin as a main component is preferable from the viewpoint of filling properties because of its low heat shrinkage.

After the insulating material 14 is hardened by usual drying hardening, light hardening, heat hardening or the like, the surface of the base material 10 is lightly polished by a belt sander, buffing or the like. By this polishing step, as shown in FIG. 1D, the surface of the insulating material 14 at the opening of the through hole 10a is formed to be substantially flush with the plating layers 11 and 12 and flat. Further, the plating layers 11 and 12
A predetermined mask is formed thereon using a photolithography technique, and an etching process is performed to form wiring layers 15 and 16 having a predetermined pattern.

Next, as shown in FIG. 1 (e), after applying an insulating resist 17 on the surface, only the region connected to the upper layer is opened using photolithography. On the insulating resist, an insulating resist 18 is further applied in the same manner, and only the above-mentioned region is opened using the photolithography technique. This opening region is the insulating material 14 and the wiring part around it in the figure.

Further, as shown in FIG. 2F, a coating material 19 containing a large number of fillers in a predetermined reactive resin is insulated by screen printing or the like on the second insulating resist 18. The material is applied while avoiding the material 14 and its surrounding wiring portion. Various thermosetting resins or photocurable resins can be used as the reactive resin of the coating material 19. As the filler contained therein, fine particles that can be eluted such as calcium carbonate, for example, particles having a particle size of about several μm are used.

After the coating material 19 is applied and cured by heating or light irradiation, the surface is lightly polished with a buff as shown in FIG. Remove the cured layer of
By performing sandblasting using abrasive grains having a particle size of about several tens of μm, a polishing trace on the surface is removed to form a uniform rough surface, and the filler embedded near the surface is exposed. In this state, by performing soft etching using a cleaning acid solution or the like, the filler is eluted,
Form fine irregularities on the surface.

After this, a step of opening a through hole 10b in the substrate is provided as needed. This through hole 10b is
Like the through hole 10a shown in FIG. 1A, it is formed by drilling or the like. This through hole 10b is formed in the wiring layer 16
And conductive wiring between the wiring layer and the upper wiring layer.

As shown in FIG. 2 (h), electroless plating is performed on the surface of the coating material 19 thus roughened to form a first plating layer 20 on the entire surface.
The second plating layer 21 is formed by performing electrolytic plating. The reason why the plating layer is formed in two layers is to maintain the smoothness of the surface of the plating layer while increasing the adhesion strength of the plating layer. The conductive connection portions C are formed by these plating layers. This conductive connection portion C is formed on a wiring layer 15 formed in a ring shape, as shown in FIG. In this plating step, the inner surface of the through hole 10b is also covered with the plating layer, and the front and back of the substrate are electrically connected.

Next, as shown in FIG. 2I, the plating layers 20, 21 are formed by the same photolithography technique as described above.
Is etched to form a wiring layer 22 in a predetermined pattern. Then, when a wiring layer is further formed on the wiring layer, an insulating material 23 similar to the above-described insulating material 14 is filled in the recess formed above the conductive connection portion C. At this time, the insulating material 23 is similarly filled in the through hole 10b.

In this embodiment, a structure equivalent to a blind via hole is formed in the portion of the through hole 10a, and the inside is filled with the insulating material 14, so that the amount of conductor can be reduced. Therefore, it is possible to reduce the electromagnetic effect on the upper wiring layer (the effect on the high-frequency characteristics, the withstand voltage, and the like due to the capacitance and insulation resistance between conductors). In this embodiment, since the opening surface of the insulating material 14 is mechanically polished and flattened, the upper layer structure can be formed after the upper surface of the wiring layer is flattened. (The unevenness of the lower layer affects the formation of the upper layer and causes the loss or disconnection of the wiring) can be prevented at the same time.

FIG. 3 shows a cross section of a different region of the above embodiment. Here, as shown in FIG. 3A, the conductive connection portion D is formed at a position different from the structure equivalent to the blind via hole formed in the portion of the through hole 10a formed in the base material 10. . This conductive connection D
Connects the wiring layer 15 and the wiring layer 22, and is formed in the same manner as the conductive connection portion C described above.

In the conductive connecting portion D, the insulating material 23 is formed in the same manner as described above.
After the surface of the substrate is flattened by mechanical polishing, as shown in FIG. 3B, a step of forming insulating resists 24 and 25, a coating material 26
Is carried out in the same manner as described above. Then, a plating layer forming step and a wiring pattern forming step are performed, and a new wiring layer 27 is formed. Here, the conductive connection portion E connects the wiring layer 22 and the wiring layer 27.

In this region, the conductive connection portion D between the wiring layer 15 and the wiring layer 22 having the planar shape shown in FIG.
As shown in (c), the structure is equivalent to the inner via hole formed in the substrate. In this case, the inside of the hole is filled with an insulating material 23. Therefore, the amount of conductor is reduced in the same manner as described above, the electrical insulation with the surrounding wiring portion is improved, and the improvement of high frequency characteristics, withstand voltage and noise resistance can be expected. That is, the insulating material 14,
Due to the presence of 23, the peripheral portion of the insulating material 14 having the blind via hole structure and the wiring portion 22a formed thereon, or the peripheral portion of the insulating material 23 having the inner via hole structure and the upper layer thereof are formed. Wiring part 27a
And the electromagnetic interference between them is reduced, and the electrical characteristics are improved.

FIG. 5 shows a partial cross section of a multilayer wiring board 30 which can be formed by the method of the above embodiment. The multilayer wiring board 30 includes a wiring layer 31 inside the board.
This is a six-layer substrate having a circuit configuration of six layers of 32, 33, 34, 35, and 36. Inside this, a number of blind via hole structures 37 and inner via hole structures 38 are formed. Here, FIG. 5 shows only a via hole structure for connecting adjacent layers, but a blind via hole structure and an inner via hole structure for connecting wiring layers separated by two or more layers can also be formed.

In the multilayer board shown in FIG. 5, there is no through hole for inserting electronic components mounted on the board surface.
Instead, conductive pads (chip lands) 39 for directly connecting electronic components are formed on the substrate surface. Only through-holes 40 for wiring connection are formed on the substrate itself for wiring reasons.

As can be seen from this structure, according to the present invention, even in a high-density multilayer substrate formed by the build-up method, the capacitance between conductors can be reduced and the insulation resistance can be increased. An epoch-making multilayer wiring board having good high-frequency characteristics, high withstand voltage, and strong against noise (hard to pick up noise) can be manufactured.

[0027]

As described above, according to the present invention, the amount of conductor can be increased by forming a conductive connection structure in the opening of the base material or the insulating layer and then filling the inside of the opening with an insulating material. In addition to making reliable conductive connection without reducing the capacitance, the capacitance between the wiring layers can be reduced and the insulation resistance can be increased, so that the high-frequency characteristics and dielectric strength of the substrate can be improved, and noise resistance can be improved. Performance can also be improved. Further, by filling the insulating material so as to be substantially flat, the upper insulating layer and the wiring layer can be formed on a flat surface, so that the cross-sectional structure of the substrate can be matched and wiring defects and the like can be prevented.

[Brief description of the drawings]

FIGS. 1A to 1E are process diagrams showing an embodiment of a method for manufacturing a multilayer wiring board according to the present invention.

FIGS. 2A to 2C are process diagrams (f) to (i) showing an embodiment of a method for manufacturing a multilayer wiring board according to the present invention.

3 (a) to 3 (c) are cross-sectional views showing a cross section of another region of the embodiment.

4A is a plan view showing a part of the region shown in FIG. 2 and FIG. 4B is a plan view showing a part of the region shown in FIG.

FIG. 5 is a partial cross section showing an example of a multilayer wiring board that can be formed according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 base material 10a, 10b through hole 14, 23 insulating material 15, 16, 22, 27 wiring layer C, D, E conductive connection portion

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshiko Nakajima 4-1-25, Shinmeicho, Okaya-shi, Nagano Daiwa Industries Co., Ltd. (72) Inventor Mitsuhiko Kitamura 4-1-1, Shinmeicho, Okaya-shi, Nagano No. Daiwa Kogyo Co., Ltd. (56) References JP-A-7-162147 (JP, A) JP-A-6-302963 (JP, A) JP-A-6-275959 (JP, A) JP-A-4- 217389 (JP, A) JP-A-2-36591 (JP, A) JP-A-7-283538 (JP, A) JP-A-8-242077 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H05K 3 / 46,3 / 38

Claims (2)

(57) [Claims] 1. A method for manufacturing a multilayer wiring board formed by sequentially laminating a plurality of wiring layers on a base material via an insulating layer, wherein the wiring layer is formed through an opening formed in the base material or the insulating layer. Forming a different-layer conductive connection structure in which different wiring layers are conductively connected to each other, and thereafter, a step of filling the inside of the opening with an insulating material so that the surface of the substrate becomes substantially flat is provided. After coating, only the region connected to the upper layer is opened, and an insulating resist is applied again to open only the region, and then a large number of several μm are formed on the insulating resist.
The coating material containing the filler of about m is applied avoiding the above-mentioned area, and after being cured by heating or light irradiation, the surface is lightly polished with a buff to remove the cured layer near the surface, and thereafter, By performing sandblasting using abrasive grains of about several tens of μm, removing the polishing marks on the surface to form a uniform rough surface and exposing the filler embedded near the surface,
The filler is eluted by soft etching to form fine irregularities on the surface, two plating layers are sequentially formed on the surface, conductive connection portions are provided, and the plating layer is etched by photolithography technology to a predetermined level. A method for manufacturing a multilayer wiring board, wherein a wiring layer is formed in the pattern described above. 2. The method according to claim 1, wherein, in the step of filling the insulating material, after the insulating material is selectively applied in the opening, the surface on which the insulating material is applied is mechanically flattened. A method for manufacturing a multilayer wiring board, the method comprising: