JP2891008B2 - Setup time verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing verification method for designing a logic circuit, and more particularly to a latch setup time verification method.

[0002]

2. Description of the Related Art A conventional setup time verifying method for a latch as shown in FIG. 3 will be described. In FIG. 1, reference numeral 3 denotes a transistor, which passes a data input signal input from a data input terminal 1 based on a clock signal input to a clock signal input terminal 2. The passed data input signal is latched in the inverter gates 4 and 5, and then output from the data output terminal 7. In addition, 6 is a load capacity.

[0003] In such a latch, the setup time verification is performed in such a manner that the time difference between the clock input signal change time entering the clock signal input terminal 2 and the data input signal change time entering the data input signal 1 and the load capacitance 6 of the latch are determined. This was done by comparing fixed setup times assuming a case with a virtual constant value.

[0004]

According to such a conventional setup time verification method, when the latch load capacity 6 is larger than the virtual fixed load capacity, the setup time becomes longer than the virtual fixed setup time. As a result, the timing error cannot be found. An object of the present invention is to provide a setup time verification method capable of preventing a timing error from being overlooked in consideration of a load capacity.

[Means for Solving the Problems]
The setup time verification is performed by detecting the time difference between the clock input signal change time and the data output signal change time in the latch whose setup time depends on the load capacitance, and comparing this time difference with the setup time when the latch is unloaded. I do.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing an embodiment of the present invention, which is an example applied to the latch of FIG. First, in step S1, a wiring delay calculated in consideration of the load capacitance and the wiring length of the next connection gate is applied to the output terminals of all the gates in the circuit. Next, in step S2, the delay value of the signal path to the data output terminal 1 of the latch is calculated by adding the internal delay of all the gates on the path and the wiring delay calculated in step S1.

Further, in step S3, the delay value of the signal path up to the clock input terminal 2 of the latch is set in step S3
Calculate in the same way as 2. Then, in step S4, the difference between the delay value of the signal path to the clock input terminal 2 calculated in step S3 and the delay value of the signal path to the data output terminal 7 calculated in step S2, and the latch is unloaded. The setup is verified by comparing the setup times of the cases. At this time, if the difference between the delay values is smaller than the no-load setup time, or if the delay value of the signal path to the data output terminal 7 is larger than the delay value of the signal path to the clock input terminal 2, The setup time error is unconditionally determined regardless of the value of the setup time Tsu0 described later. Then, in a determination step S5, it is determined whether or not the verification in the step S4 is an error. If the verification is an error, an error message is issued in a step S6 and the process is terminated. If there is no error in the determination S5, the process ends.

FIG. 2 is a timing chart for explaining this embodiment, and shows an example in which the virtual load capacity is 0, that is, no load, for simplicity. 8, reference numeral 8 denotes a clock signal waveform input to the clock signal input terminal 2, 9 denotes a data input signal waveform input to the data input terminal 1, and 10 denotes an output from the inverter gate 5 when the latch is unloaded. 7, a data output signal waveform extracted from
Reference numeral 11 denotes a data output signal waveform output from the inverter gate 5 and taken out from the data output terminal 7 in consideration of the load capacitance 6. Also, Tsu0 is the setup time when there is no load capacitance, Tc is the clock input signal change time, Td is the input / output terminal change time, and Tq is the data output terminal change time.

As can be seen, the difference between the clock input signal change time Tc and the data input terminal signal change time Td is:
Since it is longer than the no-load setup time Tsu0, no error occurs in the conventional setup time verification. However, at the clock input signal change time Tc, the output signal 11 of the inverter gate 5 has a stable logic state as shown by the waveform 11 when there is no load, but the load capacitance 6
Is considered, the logic is in an unstable state, and the latch does not operate normally.

Therefore, the timing error cannot be detected unless the verification is performed using a setup time longer than the setup time Tsu0 at the time of no load. However, according to the present invention, the clock input signal change time Tc and the data output signal change time Tq are compared. , Data output terminal change time Tq
Is larger, it can be considered as an error. That is,
Since the data output signal change time Tq of the latch takes into account the delay time due to the load capacitance 6, the setup time verification is performed using a fixed setup time when the latch is unloaded, regardless of the load capacitance of the latch. It becomes possible.

[0011]

As described above, the present invention compares the time difference between the clock signal input terminal change time and the data output signal change time with the set-up time when the latch is not loaded, so that the timing verification is performed. The setup time verification in consideration of the load capacity can be performed, and the timing error can be prevented from being overlooked.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a setup time verification method of the present invention.

FIG. 2 is a timing chart when verifying a setup time in the latch of FIG. 3;

FIG. 3 is a circuit diagram of a latch circuit to be subjected to a setup time verification.

[Explanation of symbols]

 Reference Signs List 1 data input terminal 2 clock input terminal 3 transistor 4, 5 inverter 6 load capacitance 7 data output terminal Tsu0 setup time without load capacitance Td data input signal change time Tq data output terminal change time considering load capacitance Tc clock input Signal change time

Claims (1)

(57) [Claims] In a setup time verification of a latch in which a setup time in a logic circuit depends on a load capacitance, a clock input signal change time in the latch;
Detecting a time difference between the data output signal change times; and comparing the time difference with a setup time when the latch is unloaded.